From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:39393) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7ihH-0001kG-UG for qemu-devel@nongnu.org; Wed, 14 Mar 2012 03:32:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S7ihC-0007eW-QO for qemu-devel@nongnu.org; Wed, 14 Mar 2012 03:32:35 -0400 Received: from mprc.pku.edu.cn ([162.105.203.9]:54042) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7ihC-0007dy-0f for qemu-devel@nongnu.org; Wed, 14 Mar 2012 03:32:30 -0400 Message-ID: <1331710379.2389.15.camel@epip-laptop> From: Guan Xuetao Date: Wed, 14 Mar 2012 15:32:59 +0800 In-Reply-To: <1331689198-11076-1-git-send-email-afaerber@suse.de> References: <1330893156-26569-1-git-send-email-afaerber@suse.de> <1331689198-11076-1-git-send-email-afaerber@suse.de> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 0/7] QOM'ify UniCore32 CPU Reply-To: gxt@mprc.pku.edu.cn List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Andreas =?ISO-8859-1?Q?F=E4rber?= Cc: qemu-devel@nongnu.org, Anthony Liguori On Wed, 2012-03-14 at 02:39 +0100, Andreas F=C3=A4rber wrote: > Hello, >=20 > Based on qom-cpu v4 and object_class_get_list() v2, this series convert= s > the UniCore32 CPU to QOM. Code-wise, target-unicore32 is pretty close t= o > target-arm and faces a similar issue of CPU-dependent init code, so let= 's > tackle it next. >=20 > Patch 1 adds a UniCore32 CPU guest core (TCG) section to MAINTAINERS, > so that the target-unicore32 author gets notified of patches against hi= s code. >=20 > Patch 2, based on feedback from Guan Xuetao, changes the license of mos= t > target-unicore32 files from GPLv2 to GPLv2+. Anthony had contributed a > qemu_malloc() -> g_malloc() substitution that he can't relicense at thi= s time, > so leave that as GPLv2 and declare my following patches explicitly as G= PLv2+. >=20 > Patch 2 embeds CPUUniCore32State into UniCore32CPU. My new cpu-qom.h he= ader > can be GPLv2+, but into cpu.c we're moving helper.c code so make it GPL= v2 for now. >=20 > Patches 4-7 move code out of the uc32_cpu_init() function and into clas= ses. >=20 > Regards, > Andreas Thanks for your help, and I'm sorry for my procrastination. I pulled the latest qemu code, but these patches seems to rely on the former qom-cpu v4 series. Could you tell me where I can pull the testable branch/tree? BTW: are there some robots to test qemu automatically? Then, I can put binary files (from simple helloworld to complicated spec benchmark) into it, perhaps write a script for running, and receive the result daily or weekly. Thanks and Regards Guan Xuetao > Cc: Guan Xue-tao > Cc: Anthony Liguori >=20 > Changes from former repo.or.cz qom-cpu[-wip] branch: > * Drop duplicate .instance_init. >=20 > Andreas F=C3=A4rber (7): > MAINTAINERS: Add entry for UniCore32 > target-unicore32: Relicense to GPLv2+ > target-unicore32: QOM'ify CPU > target-unicore32: Store cp0 c0_cachetype in UniCore32CPUClass > target-unicore32: Store cp0 c1_sys in UniCore32CPUClass > target-unicore32: Store feature flags in UniCore32CPUClass > target-unicore32: Store ucf64 fpscr in UniCore32CPUClass >=20 > MAINTAINERS | 5 ++ > Makefile.target | 1 + > target-unicore32/cpu-qom.h | 81 ++++++++++++++++++++++++++++++ > target-unicore32/cpu.c | 112 ++++++++++++++++++++++++++++++++++= ++++++++ > target-unicore32/cpu.h | 10 +--- > target-unicore32/helper.c | 62 ++--------------------- > target-unicore32/helper.h | 5 +- > target-unicore32/op_helper.c | 5 +- > target-unicore32/translate.c | 5 +- > 9 files changed, 213 insertions(+), 73 deletions(-) > create mode 100644 target-unicore32/cpu-qom.h > create mode 100644 target-unicore32/cpu.c >=20