From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:38974) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7qed-0004tr-1k for qemu-devel@nongnu.org; Wed, 14 Mar 2012 12:02:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S7qe5-0002Ba-GF for qemu-devel@nongnu.org; Wed, 14 Mar 2012 12:02:22 -0400 Received: from cantor2.suse.de ([195.135.220.15]:44465 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7qe5-0002Af-4p for qemu-devel@nongnu.org; Wed, 14 Mar 2012 12:01:49 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Wed, 14 Mar 2012 17:01:29 +0100 Message-Id: <1331740900-5637-2-git-send-email-afaerber@suse.de> In-Reply-To: <1331740900-5637-1-git-send-email-afaerber@suse.de> References: <1330893156-26569-1-git-send-email-afaerber@suse.de> <1331740900-5637-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 01/12] target-sh4: QOM'ify CPU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= , Aurelien Jarno Embed CPUSH4State into SuperHCPU. Let cpu_state_reset() call cpu_reset(). Let sh4_cpu_list() enumerate CPU classes alphabetically. Signed-off-by: Andreas F=C3=A4rber --- Makefile.target | 1 + target-sh4/cpu-qom.h | 78 +++++++++++++++++++++++ target-sh4/cpu.c | 161 ++++++++++++++++++++++++++++++++++++++++++= ++++++ target-sh4/cpu.h | 1 + target-sh4/translate.c | 119 +++++++++++------------------------ 5 files changed, 278 insertions(+), 82 deletions(-) create mode 100644 target-sh4/cpu-qom.h create mode 100644 target-sh4/cpu.c diff --git a/Makefile.target b/Makefile.target index 7033df0..c48a849 100644 --- a/Makefile.target +++ b/Makefile.target @@ -88,6 +88,7 @@ libobj-$(TARGET_SPARC64) +=3D vis_helper.o libobj-$(CONFIG_NEED_MMU) +=3D mmu.o libobj-$(TARGET_ARM) +=3D neon_helper.o iwmmxt_helper.o libobj-$(TARGET_ARM) +=3D cpu.o +libobj-$(TARGET_SH4) +=3D cpu.o ifeq ($(TARGET_BASE_ARCH), sparc) libobj-y +=3D fop_helper.o cc_helper.o win_helper.o mmu_helper.o ldst_he= lper.o libobj-y +=3D cpu_init.o diff --git a/target-sh4/cpu-qom.h b/target-sh4/cpu-qom.h new file mode 100644 index 0000000..1441328 --- /dev/null +++ b/target-sh4/cpu-qom.h @@ -0,0 +1,78 @@ +/* + * QEMU SuperH CPU + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Library General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Library General Public License for more details. + * + * You should have received a copy of the GNU Library General Public + * License along with this library; if not, see + * + */ +#ifndef QEMU_SUPERH_CPU_QOM_H +#define QEMU_SUPERH_CPU_QOM_H + +#include "qemu-common.h" +#include "qemu/cpu.h" +#include "cpu.h" + +#define TYPE_SUPERH_CPU "superh-cpu" + +#define SUPERH_CPU_CLASS(klass) \ + OBJECT_CLASS_CHECK(SuperHCPUClass, (klass), TYPE_SUPERH_CPU) +#define SUPERH_CPU(obj) \ + OBJECT_CHECK(SuperHCPU, (obj), TYPE_SUPERH_CPU) +#define SUPERH_CPU_GET_CLASS(obj) \ + OBJECT_GET_CLASS(SuperHCPUClass, (obj), TYPE_SUPERH_CPU) + +/** + * SuperHCPUClass: + * @parent_reset: The parent class' reset handler. + * + * A SuperH CPU model. + */ +typedef struct SuperHCPUClass { + /*< private >*/ + CPUClass parent_class; + /*< public >*/ + + void (*parent_reset)(CPUState *cpu); + + int id; + uint32_t pvr; + uint32_t prr; + uint32_t cvr; + uint32_t features; +} SuperHCPUClass; + +/** + * SuperHCPU: + * @env: Legacy CPU state. + * + * A SuperH CPU. + */ +typedef struct SuperHCPU { + /*< private >*/ + CPUState parent_obj; + /*< public >*/ + + CPUSH4State env; +} SuperHCPU; + +static inline SuperHCPU *sh_env_get_cpu(CPUSH4State *env) +{ + return SUPERH_CPU(container_of(env, SuperHCPU, env)); +} + +#define ENV_GET_CPU(e) CPU(sh_env_get_cpu(e)) + + +#endif diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c new file mode 100644 index 0000000..68034b6 --- /dev/null +++ b/target-sh4/cpu.c @@ -0,0 +1,161 @@ +/* + * QEMU SuperH CPU + * + * Copyright (c) 2005 Samuel Tardieu + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Library General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Library General Public License for more details. + * + * You should have received a copy of the GNU Library General Public + * License along with this library; if not, see + * + */ + +#include "cpu-qom.h" +#include "qemu-common.h" + +static void superh_cpu_reset(CPUState *c) +{ + SuperHCPU *cpu =3D SUPERH_CPU(c); + SuperHCPUClass *klass =3D SUPERH_CPU_GET_CLASS(cpu); + CPUSH4State *env =3D &cpu->env; + + if (qemu_loglevel_mask(CPU_LOG_RESET)) { + qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); + log_cpu_state(env, 0); + } + + klass->parent_reset(c); + + memset(env, 0, offsetof(CPUSH4State, breakpoints)); + tlb_flush(env, 1); + + env->pc =3D 0xA0000000; +#if defined(CONFIG_USER_ONLY) + env->fpscr =3D FPSCR_PR; /* value for userspace according to the ker= nel */ + set_float_rounding_mode(float_round_nearest_even, &env->fp_status); = /* ?! */ +#else + env->sr =3D SR_MD | SR_RB | SR_BL | SR_I3 | SR_I2 | SR_I1 | SR_I0; + env->fpscr =3D FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value accordin= g to + SH4 manual */ + set_float_rounding_mode(float_round_to_zero, &env->fp_status); + set_flush_to_zero(1, &env->fp_status); +#endif + set_default_nan_mode(1, &env->fp_status); +} + +/* CPU models */ + +typedef struct { + const char *name; + int id; + uint32_t pvr; + uint32_t prr; + uint32_t cvr; + uint32_t features; +} SuperHCPUInfo; + +static const SuperHCPUInfo superh_cpus[] =3D { + { + .name =3D "SH7750R", + .id =3D SH_CPU_SH7750R, + .pvr =3D 0x00050000, + .prr =3D 0x00000100, + .cvr =3D 0x00110000, + .features =3D SH_FEATURE_BCR3_AND_BCR4, + }, { + .name =3D "SH7751R", + .id =3D SH_CPU_SH7751R, + .pvr =3D 0x04050005, + .prr =3D 0x00000113, + .cvr =3D 0x00110000, /* Neutered caches, should be 0x20480000= */ + .features =3D SH_FEATURE_BCR3_AND_BCR4, + }, { + .name =3D "SH7785", + .id =3D SH_CPU_SH7785, + .pvr =3D 0x10300700, + .prr =3D 0x00000200, + .cvr =3D 0x71440211, + .features =3D SH_FEATURE_SH4A, + }, +}; + +static void superh_cpu_initfn(Object *obj) +{ + SuperHCPU *cpu =3D SUPERH_CPU(obj); + SuperHCPUClass *klass =3D SUPERH_CPU_GET_CLASS(cpu); + CPUSH4State *env =3D &cpu->env; + + memset(env, 0, sizeof(CPUSH4State)); + env->cpu_model_str =3D object_get_typename(obj); + cpu_exec_init(env); + + env->id =3D klass->id; + env->pvr =3D klass->pvr; + env->prr =3D klass->prr; + env->cvr =3D klass->cvr; + env->features =3D klass->features; + + env->movcal_backup_tail =3D &(env->movcal_backup); + + cpu_reset(CPU(cpu)); +} + +static void superh_cpu_class_init(ObjectClass *klass, void *data) +{ + CPUClass *cpu_class =3D CPU_CLASS(klass); + SuperHCPUClass *k =3D SUPERH_CPU_CLASS(klass); + const SuperHCPUInfo *info =3D data; + + k->parent_reset =3D cpu_class->reset; + cpu_class->reset =3D superh_cpu_reset; + + k->id =3D info->id; + k->pvr =3D info->pvr; + k->prr =3D info->prr; + k->cvr =3D info->cvr; + k->features =3D info->features; +} + +static void cpu_register(const SuperHCPUInfo *info) +{ + TypeInfo type =3D { + .name =3D info->name, + .parent =3D TYPE_SUPERH_CPU, + .instance_size =3D sizeof(SuperHCPU), + .instance_init =3D superh_cpu_initfn, + .class_size =3D sizeof(SuperHCPUClass), + .class_init =3D superh_cpu_class_init, + .class_data =3D (void *)info, + }; + + type_register_static(&type); +} + +static const TypeInfo superh_cpu_type_info =3D { + .name =3D TYPE_SUPERH_CPU, + .parent =3D TYPE_CPU, + .instance_size =3D sizeof(SuperHCPU), + .abstract =3D true, + .class_size =3D sizeof(SuperHCPUClass), +}; + +static void superh_cpu_register_types(void) +{ + int i; + + type_register_static(&superh_cpu_type_info); + for (i =3D 0; i < ARRAY_SIZE(superh_cpus); i++) { + cpu_register(&superh_cpus[i]); + } +} + +type_init(superh_cpu_register_types) diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h index 965536d..ec5e6cf 100644 --- a/target-sh4/cpu.h +++ b/target-sh4/cpu.h @@ -255,6 +255,7 @@ static inline void cpu_clone_regs(CPUSH4State *env, t= arget_ulong newsp) #endif =20 #include "cpu-all.h" +#include "cpu-qom.h" =20 /* Memory access type */ enum { diff --git a/target-sh4/translate.c b/target-sh4/translate.c index a337beb..71434d0 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -180,107 +180,62 @@ void cpu_dump_state(CPUSH4State * env, FILE * f, =20 void cpu_state_reset(CPUSH4State *env) { - if (qemu_loglevel_mask(CPU_LOG_RESET)) { - qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); - log_cpu_state(env, 0); - } - - memset(env, 0, offsetof(CPUSH4State, breakpoints)); - tlb_flush(env, 1); - - env->pc =3D 0xA0000000; -#if defined(CONFIG_USER_ONLY) - env->fpscr =3D FPSCR_PR; /* value for userspace according to the ker= nel */ - set_float_rounding_mode(float_round_nearest_even, &env->fp_status); = /* ?! */ -#else - env->sr =3D SR_MD | SR_RB | SR_BL | SR_I3 | SR_I2 | SR_I1 | SR_I0; - env->fpscr =3D FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value accordin= g to SH4 manual */ - set_float_rounding_mode(float_round_to_zero, &env->fp_status); - set_flush_to_zero(1, &env->fp_status); -#endif - set_default_nan_mode(1, &env->fp_status); + cpu_reset(ENV_GET_CPU(env)); } =20 -typedef struct { - const char *name; - int id; - uint32_t pvr; - uint32_t prr; - uint32_t cvr; - uint32_t features; -} sh4_def_t; - -static sh4_def_t sh4_defs[] =3D { - { - .name =3D "SH7750R", - .id =3D SH_CPU_SH7750R, - .pvr =3D 0x00050000, - .prr =3D 0x00000100, - .cvr =3D 0x00110000, - .features =3D SH_FEATURE_BCR3_AND_BCR4, - }, { - .name =3D "SH7751R", - .id =3D SH_CPU_SH7751R, - .pvr =3D 0x04050005, - .prr =3D 0x00000113, - .cvr =3D 0x00110000, /* Neutered caches, should be 0x20480000 */ - .features =3D SH_FEATURE_BCR3_AND_BCR4, - }, { - .name =3D "SH7785", - .id =3D SH_CPU_SH7785, - .pvr =3D 0x10300700, - .prr =3D 0x00000200, - .cvr =3D 0x71440211, - .features =3D SH_FEATURE_SH4A, - }, -}; +typedef struct SuperHCPUListState { + fprintf_function cpu_fprintf; + FILE *file; +} SuperHCPUListState; =20 -static const sh4_def_t *cpu_sh4_find_by_name(const char *name) +static gint sh_cpu_list_compare(gconstpointer a, gconstpointer b) { - int i; - - if (strcasecmp(name, "any") =3D=3D 0) - return &sh4_defs[0]; + ObjectClass *class_a =3D (ObjectClass *)a; + ObjectClass *class_b =3D (ObjectClass *)b; =20 - for (i =3D 0; i < ARRAY_SIZE(sh4_defs); i++) - if (strcasecmp(name, sh4_defs[i].name) =3D=3D 0) - return &sh4_defs[i]; - - return NULL; + return strcasecmp(object_class_get_name(class_a), + object_class_get_name(class_b)); } =20 -void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf) +static void sh_cpu_list_entry(gpointer data, gpointer user_data) { - int i; + ObjectClass *klass =3D data; + SuperHCPUListState *s =3D user_data; =20 - for (i =3D 0; i < ARRAY_SIZE(sh4_defs); i++) - (*cpu_fprintf)(f, "%s\n", sh4_defs[i].name); + (*s->cpu_fprintf)(s->file, "%s\n", + object_class_get_name(klass)); } =20 -static void cpu_register(CPUSH4State *env, const sh4_def_t *def) +void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf) { - env->pvr =3D def->pvr; - env->prr =3D def->prr; - env->cvr =3D def->cvr; - env->id =3D def->id; + SuperHCPUListState s =3D { + .cpu_fprintf =3D cpu_fprintf, + .file =3D f, + }; + GSList *list; + + list =3D object_class_get_list(TYPE_SUPERH_CPU, false); + list =3D g_slist_sort(list, sh_cpu_list_compare); + g_slist_foreach(list, sh_cpu_list_entry, &s); + g_slist_free(list); } =20 CPUSH4State *cpu_sh4_init(const char *cpu_model) { + SuperHCPU *cpu; CPUSH4State *env; - const sh4_def_t *def; =20 - def =3D cpu_sh4_find_by_name(cpu_model); - if (!def) - return NULL; - env =3D g_malloc0(sizeof(CPUSH4State)); - env->features =3D def->features; - cpu_exec_init(env); - env->movcal_backup_tail =3D &(env->movcal_backup); + if (strcasecmp(cpu_model, "any") =3D=3D 0) { + cpu_model =3D "SH7750R"; + } + if (object_class_by_name(cpu_model) =3D=3D NULL) { + return NULL; + } + cpu =3D SUPERH_CPU(object_new(cpu_model)); + env =3D &cpu->env; + sh4_translate_init(); - env->cpu_model_str =3D cpu_model; - cpu_state_reset(env); - cpu_register(env, def); + qemu_init_vcpu(env); return env; } --=20 1.7.7