From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:38869) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7qeK-00043x-HQ for qemu-devel@nongnu.org; Wed, 14 Mar 2012 12:02:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S7qe5-0002BL-EB for qemu-devel@nongnu.org; Wed, 14 Mar 2012 12:02:04 -0400 Received: from cantor2.suse.de ([195.135.220.15]:44470 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7qe5-0002Ai-4z for qemu-devel@nongnu.org; Wed, 14 Mar 2012 12:01:49 -0400 Received: from relay2.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 7F6AE906EB for ; Wed, 14 Mar 2012 17:01:44 +0100 (CET) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Wed, 14 Mar 2012 17:01:31 +0100 Message-Id: <1331740900-5637-4-git-send-email-afaerber@suse.de> In-Reply-To: <1331740900-5637-1-git-send-email-afaerber@suse.de> References: <1330893156-26569-1-git-send-email-afaerber@suse.de> <1331740900-5637-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 03/12] hw/sh7750: Use SuperHCPU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= In place of CPUSH4State use SuperHCPU for SH7750State::cpu field. Fix tab indentation on those lines and add braces. Signed-off-by: Andreas F=C3=A4rber --- hw/sh7750.c | 69 ++++++++++++++++++++++++++++++-----------------------= ------ 1 files changed, 35 insertions(+), 34 deletions(-) diff --git a/hw/sh7750.c b/hw/sh7750.c index c7e653c..23950aa 100644 --- a/hw/sh7750.c +++ b/hw/sh7750.c @@ -44,7 +44,7 @@ typedef struct SH7750State { MemoryRegion iomem_ffc; MemoryRegion mmct_iomem; /* CPU */ - CPUSH4State *cpu; + SuperHCPU *cpu; /* Peripheral frequency in Hz */ uint32_t periph_freq; /* SDRAM controller */ @@ -79,7 +79,7 @@ typedef struct SH7750State { =20 static inline int has_bcr3_and_bcr4(SH7750State *s) { - return sh_env_get_cpu(s->cpu)->features & SH_FEATURE_BCR3_AND_BCR4; + return s->cpu->features & SH_FEATURE_BCR3_AND_BCR4; } =20 /********************************************************************** @@ -271,29 +271,29 @@ static uint32_t sh7750_mem_readl(void *opaque, targ= et_phys_addr_t addr) ignore_access("long read", addr); return 0; case SH7750_MMUCR_A7: - return s->cpu->mmucr; + return s->cpu->env.mmucr; case SH7750_PTEH_A7: - return s->cpu->pteh; + return s->cpu->env.pteh; case SH7750_PTEL_A7: - return s->cpu->ptel; + return s->cpu->env.ptel; case SH7750_TTB_A7: - return s->cpu->ttb; + return s->cpu->env.ttb; case SH7750_TEA_A7: - return s->cpu->tea; + return s->cpu->env.tea; case SH7750_TRA_A7: - return s->cpu->tra; + return s->cpu->env.tra; case SH7750_EXPEVT_A7: - return s->cpu->expevt; + return s->cpu->env.expevt; case SH7750_INTEVT_A7: - return s->cpu->intevt; + return s->cpu->env.intevt; case SH7750_CCR_A7: return s->ccr; case 0x1f000030: /* Processor version */ - return s->cpu->pvr; + return s->cpu->env.pvr; case 0x1f000040: /* Cache version */ - return s->cpu->cvr; + return s->cpu->env.cvr; case 0x1f000044: /* Processor revision */ - return s->cpu->prr; + return s->cpu->env.prr; default: error_access("long read", addr); abort(); @@ -406,36 +406,37 @@ static void sh7750_mem_writel(void *opaque, target_= phys_addr_t addr, return; case SH7750_MMUCR_A7: if (mem_value & MMUCR_TI) { - cpu_sh4_invalidate_tlb(s->cpu); + cpu_sh4_invalidate_tlb(&s->cpu->env); } - s->cpu->mmucr =3D mem_value & ~MMUCR_TI; + s->cpu->env.mmucr =3D mem_value & ~MMUCR_TI; return; case SH7750_PTEH_A7: /* If asid changes, clear all registered tlb entries. */ - if ((s->cpu->pteh & 0xff) !=3D (mem_value & 0xff)) - tlb_flush(s->cpu, 1); - s->cpu->pteh =3D mem_value; + if ((s->cpu->env.pteh & 0xff) !=3D (mem_value & 0xff)) { + tlb_flush(&s->cpu->env, 1); + } + s->cpu->env.pteh =3D mem_value; return; case SH7750_PTEL_A7: - s->cpu->ptel =3D mem_value; + s->cpu->env.ptel =3D mem_value; return; case SH7750_PTEA_A7: - s->cpu->ptea =3D mem_value & 0x0000000f; + s->cpu->env.ptea =3D mem_value & 0x0000000f; return; case SH7750_TTB_A7: - s->cpu->ttb =3D mem_value; + s->cpu->env.ttb =3D mem_value; return; case SH7750_TEA_A7: - s->cpu->tea =3D mem_value; + s->cpu->env.tea =3D mem_value; return; case SH7750_TRA_A7: - s->cpu->tra =3D mem_value & 0x000007ff; + s->cpu->env.tra =3D mem_value & 0x000007ff; return; case SH7750_EXPEVT_A7: - s->cpu->expevt =3D mem_value & 0x000007ff; + s->cpu->env.expevt =3D mem_value & 0x000007ff; return; case SH7750_INTEVT_A7: - s->cpu->intevt =3D mem_value & 0x000007ff; + s->cpu->env.intevt =3D mem_value & 0x000007ff; return; case SH7750_CCR_A7: s->ccr =3D mem_value; @@ -648,20 +649,20 @@ static uint64_t sh7750_mmct_read(void *opaque, targ= et_phys_addr_t addr, /* do nothing */ break; case MM_ITLB_ADDR: - ret =3D cpu_sh4_read_mmaped_itlb_addr(s->cpu, addr); + ret =3D cpu_sh4_read_mmaped_itlb_addr(&s->cpu->env, addr); break; case MM_ITLB_DATA: - ret =3D cpu_sh4_read_mmaped_itlb_data(s->cpu, addr); + ret =3D cpu_sh4_read_mmaped_itlb_data(&s->cpu->env, addr); break; case MM_OCACHE_ADDR: case MM_OCACHE_DATA: /* do nothing */ break; case MM_UTLB_ADDR: - ret =3D cpu_sh4_read_mmaped_utlb_addr(s->cpu, addr); + ret =3D cpu_sh4_read_mmaped_utlb_addr(&s->cpu->env, addr); break; case MM_UTLB_DATA: - ret =3D cpu_sh4_read_mmaped_utlb_data(s->cpu, addr); + ret =3D cpu_sh4_read_mmaped_utlb_data(&s->cpu->env, addr); break; default: abort(); @@ -691,10 +692,10 @@ static void sh7750_mmct_write(void *opaque, target_= phys_addr_t addr, /* do nothing */ break; case MM_ITLB_ADDR: - cpu_sh4_write_mmaped_itlb_addr(s->cpu, addr, mem_value); + cpu_sh4_write_mmaped_itlb_addr(&s->cpu->env, addr, mem_value); break; case MM_ITLB_DATA: - cpu_sh4_write_mmaped_itlb_data(s->cpu, addr, mem_value); + cpu_sh4_write_mmaped_itlb_data(&s->cpu->env, addr, mem_value); abort(); break; case MM_OCACHE_ADDR: @@ -702,10 +703,10 @@ static void sh7750_mmct_write(void *opaque, target_= phys_addr_t addr, /* do nothing */ break; case MM_UTLB_ADDR: - cpu_sh4_write_mmaped_utlb_addr(s->cpu, addr, mem_value); + cpu_sh4_write_mmaped_utlb_addr(&s->cpu->env, addr, mem_value); break; case MM_UTLB_DATA: - cpu_sh4_write_mmaped_utlb_data(s->cpu, addr, mem_value); + cpu_sh4_write_mmaped_utlb_data(&s->cpu->env, addr, mem_value); break; default: abort(); @@ -724,7 +725,7 @@ SH7750State *sh7750_init(CPUSH4State * cpu, MemoryReg= ion *sysmem) SH7750State *s; =20 s =3D g_malloc0(sizeof(SH7750State)); - s->cpu =3D cpu; + s->cpu =3D sh_env_get_cpu(cpu); s->periph_freq =3D 60000000; /* 60MHz */ memory_region_init_io(&s->iomem, &sh7750_mem_ops, s, "memory", 0x1fc01000); --=20 1.7.7