From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:38953) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7qea-0004m2-Ig for qemu-devel@nongnu.org; Wed, 14 Mar 2012 12:02:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S7qe6-0002CJ-NT for qemu-devel@nongnu.org; Wed, 14 Mar 2012 12:02:20 -0400 Received: from cantor2.suse.de ([195.135.220.15]:44478 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7qe6-0002Be-E9 for qemu-devel@nongnu.org; Wed, 14 Mar 2012 12:01:50 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Wed, 14 Mar 2012 17:01:34 +0100 Message-Id: <1331740900-5637-7-git-send-email-afaerber@suse.de> In-Reply-To: <1331740900-5637-1-git-send-email-afaerber@suse.de> References: <1330893156-26569-1-git-send-email-afaerber@suse.de> <1331740900-5637-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 06/12] target-sh4: Make find_*tlb_entry() take SuperHCPU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= , Aurelien Jarno Signed-off-by: Andreas F=C3=A4rber --- target-sh4/helper.c | 29 +++++++++++++++-------------- 1 files changed, 15 insertions(+), 14 deletions(-) diff --git a/target-sh4/helper.c b/target-sh4/helper.c index 2d5a4e4..d2186ed 100644 --- a/target-sh4/helper.c +++ b/target-sh4/helper.c @@ -243,15 +243,15 @@ static int itlb_replacement(CPUSH4State * env) /* Find the corresponding entry in the right TLB Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE */ -static int find_tlb_entry(CPUSH4State * env, target_ulong address, - tlb_t * entries, uint8_t nbtlb, int use_asid) +static int find_tlb_entry(SuperHCPU *cpu, target_ulong address, + tlb_t *entries, uint8_t nbtlb, int use_asid) { int match =3D MMU_DTLB_MISS; uint32_t start, end; uint8_t asid; int i; =20 - asid =3D env->pteh & 0xff; + asid =3D cpu->env.pteh & 0xff; =20 for (i =3D 0; i < nbtlb; i++) { if (!entries[i].v) @@ -304,31 +304,31 @@ static int copy_utlb_entry_itlb(CPUSH4State *env, i= nt utlb) /* Find itlb entry Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE */ -static int find_itlb_entry(CPUSH4State * env, target_ulong address, +static int find_itlb_entry(SuperHCPU *cpu, target_ulong address, int use_asid) { int e; =20 - e =3D find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid); + e =3D find_tlb_entry(cpu, address, cpu->env.itlb, ITLB_SIZE, use_asi= d); if (e =3D=3D MMU_DTLB_MULTIPLE) { e =3D MMU_ITLB_MULTIPLE; } else if (e =3D=3D MMU_DTLB_MISS) { e =3D MMU_ITLB_MISS; } else if (e >=3D 0) { - update_itlb_use(env, e); + update_itlb_use(&cpu->env, e); } return e; } =20 /* Find utlb entry Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */ -static int find_utlb_entry(CPUSH4State * env, target_ulong address, int = use_asid) +static int find_utlb_entry(SuperHCPU *cpu, target_ulong address, int use= _asid) { /* per utlb access */ - increment_urc(sh_env_get_cpu(env)); + increment_urc(cpu); =20 /* Return entry */ - return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid); + return find_tlb_entry(cpu, address, cpu->env.utlb, UTLB_SIZE, use_as= id); } =20 /* Match address against MMU @@ -348,7 +348,7 @@ static int get_mmu_address(CPUSH4State * env, target_= ulong * physical, use_asid =3D (env->mmucr & MMUCR_SV) =3D=3D 0 || (env->sr & SR_MD) =3D= =3D 0; =20 if (rw =3D=3D 2) { - n =3D find_itlb_entry(env, address, use_asid); + n =3D find_itlb_entry(sh_env_get_cpu(env), address, use_asid); if (n >=3D 0) { matching =3D &env->itlb[n]; if (!(env->sr & SR_MD) && !(matching->pr & 2)) @@ -356,7 +356,7 @@ static int get_mmu_address(CPUSH4State * env, target_= ulong * physical, else *prot =3D PAGE_EXEC; } else { - n =3D find_utlb_entry(env, address, use_asid); + n =3D find_utlb_entry(sh_env_get_cpu(env), address, use_asid= ); if (n >=3D 0) { n =3D copy_utlb_entry_itlb(env, n); matching =3D &env->itlb[n]; @@ -375,7 +375,7 @@ static int get_mmu_address(CPUSH4State * env, target_= ulong * physical, } } } else { - n =3D find_utlb_entry(env, address, use_asid); + n =3D find_utlb_entry(sh_env_get_cpu(env), address, use_asid); if (n >=3D 0) { matching =3D &env->utlb[n]; if (!(env->sr & SR_MD) && !(matching->pr & 2)) { @@ -801,6 +801,7 @@ void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, t= arget_phys_addr_t addr, =20 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr) { + SuperHCPU *cpu =3D sh_env_get_cpu(env); int n; int use_asid =3D (env->mmucr & MMUCR_SV) =3D=3D 0 || (env->sr & SR_M= D) =3D=3D 0; =20 @@ -832,11 +833,11 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulo= ng addr) return 1; =20 /* check TLB */ - n =3D find_tlb_entry(env, addr, env->itlb, ITLB_SIZE, use_asid); + n =3D find_tlb_entry(cpu, addr, env->itlb, ITLB_SIZE, use_asid); if (n >=3D 0) return env->itlb[n].c; =20 - n =3D find_tlb_entry(env, addr, env->utlb, UTLB_SIZE, use_asid); + n =3D find_tlb_entry(cpu, addr, env->utlb, UTLB_SIZE, use_asid); if (n >=3D 0) return env->utlb[n].c; =20 --=20 1.7.7