From mboxrd@z Thu Jan 1 00:00:00 1970 From: Eugeni Dodonov Subject: [PATCH 22/37] drm/i915: program WM_LINETIME on Haswell Date: Wed, 21 Mar 2012 22:09:57 -0300 Message-ID: <1332378612-3814-23-git-send-email-eugeni.dodonov@intel.com> References: <1332378612-3814-1-git-send-email-eugeni.dodonov@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from oproxy6-pub.bluehost.com (oproxy6-pub.bluehost.com [67.222.54.6]) by gabe.freedesktop.org (Postfix) with SMTP id 9B8BCA0D0C for ; Wed, 21 Mar 2012 18:30:50 -0700 (PDT) In-Reply-To: <1332378612-3814-1-git-send-email-eugeni.dodonov@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Eugeni Dodonov List-Id: intel-gfx@lists.freedesktop.org The line time can be programmed according to the number of horizontal pixels vs effective pixel rate ratio. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 46633fe..e056c32 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -6073,6 +6073,17 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16)); + if (IS_HASWELL(dev)) { + temp = I915_READ(PIPE_WM_LINETIME(pipe)); + temp &= ~PIPE_WM_LINETIME_LINETIME_MASK; + + /* Pipe horizontal total number of pixels / pixel rate in MHz. */ + temp |= PIPE_WM_LINETIME_LINETIME( + adjusted_mode->crtc_hdisplay / + (adjusted_mode->clock / 1000)); + I915_WRITE(PIPE_WM_LINETIME(pipe), temp); + } + /* pipesrc controls the size that is scaled from, which should * always be the user's requested size. */ -- 1.7.9.2