From mboxrd@z Thu Jan 1 00:00:00 1970 From: Eugeni Dodonov Subject: [PATCH 14/41] drm/i915: add support for SBI ops Date: Thu, 29 Mar 2012 12:32:30 -0300 Message-ID: <1333035177-19607-15-git-send-email-eugeni.dodonov@intel.com> References: <1333035177-19607-1-git-send-email-eugeni.dodonov@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from oproxy8-pub.bluehost.com (oproxy8-pub.bluehost.com [69.89.22.20]) by gabe.freedesktop.org (Postfix) with SMTP id 4B0A49E79D for ; Thu, 29 Mar 2012 09:00:47 -0700 (PDT) In-Reply-To: <1333035177-19607-1-git-send-email-eugeni.dodonov@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Eugeni Dodonov List-Id: intel-gfx@lists.freedesktop.org With Lynx Point, we need to use SBI to communicate with the display clock control. This commit adds helper functions to access the registers via SBI. v2: de-inline the function and address changes in bits names v1 Reviewed-by: Rodrigo Vivi Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c | 44 ++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index a0e3166..8e5f5be 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1220,6 +1220,50 @@ static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) POSTING_READ(reg); } +/* SBI access */ +static void +intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value) +{ + if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0, + 10)) + DRM_ERROR("timeout waiting for SBI to become ready\n"); + + I915_WRITE(SBI_ADDR, + (reg << 16)); + I915_WRITE(SBI_DATA, + value); + I915_WRITE(SBI_CTL_STAT, + SBI_BUSY | + SBI_CTL_OP_CRWR); + + if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0, + 10)) + DRM_ERROR("timeout waiting for SBI to complete write transaction\n"); +} + +static u32 +intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg) +{ + u32 value; + if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0, + 10)) + DRM_ERROR("timeout waiting for SBI to become ready\n"); + + I915_WRITE(SBI_ADDR, + (reg << 16)); + I915_WRITE(SBI_CTL_STAT, + SBI_BUSY | + SBI_CTL_OP_CRRD); + + if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0, + 10)) + DRM_ERROR("timeout waiting for SBI to complete read transaction\n"); + + value = I915_READ(SBI_DATA); + + return value; +} + /** * intel_enable_pch_pll - enable PCH PLL * @dev_priv: i915 private structure -- 1.7.9.5