From mboxrd@z Thu Jan 1 00:00:00 1970 From: Eugeni Dodonov Subject: [PATCH 15/41] drm/i915: add PIXCLK_GATE register Date: Thu, 29 Mar 2012 12:32:31 -0300 Message-ID: <1333035177-19607-16-git-send-email-eugeni.dodonov@intel.com> References: <1333035177-19607-1-git-send-email-eugeni.dodonov@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from oproxy5-pub.bluehost.com (oproxy5-pub.bluehost.com [67.222.38.55]) by gabe.freedesktop.org (Postfix) with SMTP id B87BB9F03E for ; Thu, 29 Mar 2012 09:00:58 -0700 (PDT) In-Reply-To: <1333035177-19607-1-git-send-email-eugeni.dodonov@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Eugeni Dodonov List-Id: intel-gfx@lists.freedesktop.org Pixel clock gating control for Lynx point. Reviewed-by: Rodrigo Vivi Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d6c0e36..48346ad 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3960,4 +3960,10 @@ #define SBI_RESPONSE_SUCCESS (0x0<<1) #define SBI_BUSY (0x1<<0) #define SBI_READY (0x0<<0) + +/* LPT PIXCLK_GATE */ +#define PIXCLK_GATE 0xC6020 +#define PIXCLK_GATE_UNGATE 1<<0 +#define PIXCLK_GATE_GATE 0<<0 + #endif /* _I915_REG_H_ */ -- 1.7.9.5