From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: [PATCH 6/7] drm/i915: implement async flush w/a Date: Sat, 31 Mar 2012 11:22:02 +0200 Message-ID: <1333185723-5047-7-git-send-email-daniel.vetter@ffwll.ch> References: <1333185723-5047-1-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-wi0-f171.google.com (mail-wi0-f171.google.com [209.85.212.171]) by gabe.freedesktop.org (Postfix) with ESMTP id E4C999E95D for ; Sat, 31 Mar 2012 03:26:08 -0700 (PDT) Received: by mail-wi0-f171.google.com with SMTP id hj13so958987wib.12 for ; Sat, 31 Mar 2012 03:26:08 -0700 (PDT) In-Reply-To: <1333185723-5047-1-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Intel Graphics Development Cc: Daniel Vetter List-Id: intel-gfx@lists.freedesktop.org Note that async flush also means things like VT-d IOTLB invalidation. See Bspec vol1c.4 "Render Engine Command Streamer", Section "ECOSKPD - Eco Scratch Pad". It doesn't seem to help in for any of our VT-d related bugs thoug. Signed-Off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_display.c | 3 +++ 2 files changed, 4 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a7ef74a..5b23d5c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -583,6 +583,7 @@ #define BB_ADDR 0x02140 /* 8 bytes */ #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ #define ECOSKPD 0x021d0 +#define ECO_ASYNC_FLUSH_FIX_REVERT (1<<7) #define ECO_GATING_CX_ONLY (1<<3) #define ECO_FLIP_DONE (1<<0) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index dab2381..dce64d8 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -8510,6 +8510,9 @@ static void gen6_init_clock_gating(struct drm_device *dev) I915_WRITE(WM2_LP_ILK, 0); I915_WRITE(WM1_LP_ILK, 0); + I915_WRITE(ECOSKPD, (ECO_ASYNC_FLUSH_FIX_REVERT << 16) | + ECO_ASYNC_FLUSH_FIX_REVERT); + I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | GEN6_BLBUNIT_CLOCK_GATE_DISABLE | -- 1.7.7.6