From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 1/7] drm/i915: implement ColorBlt w/a Date: Sat, 31 Mar 2012 14:15:21 +0100 Message-ID: <1333199739_170899@CP5-2952> References: <1333185723-5047-1-git-send-email-daniel.vetter@ffwll.ch> <1333185723-5047-2-git-send-email-daniel.vetter@ffwll.ch> <1333191260_169375@CP5-2952> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from fireflyinternet.com (smtp.fireflyinternet.com [109.228.6.236]) by gabe.freedesktop.org (Postfix) with ESMTP id F41929E73D for ; Sat, 31 Mar 2012 06:15:45 -0700 (PDT) In-Reply-To: <1333191260_169375@CP5-2952> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Intel Graphics Development Cc: Daniel Vetter List-Id: intel-gfx@lists.freedesktop.org On Sat, 31 Mar 2012 11:54:01 +0100, Chris Wilson wrote: > On Sat, 31 Mar 2012 11:21:57 +0200, Daniel Vetter wrote: > > According to an internal workaround master list, we need to set bit 5 > > of register 9400 to avoid issues with color blits. > > This sounds like it could be the root cause behind the FBC + BLT hangs. This looks like it could be true, I just tested the w/a with the FBC enabled and it survives! Tested-by: Chris Wilson I'm fully expecting it to blow up later, but one step forward. -Chris -- Chris Wilson, Intel Open Source Technology Centre