On Wed, 2012-04-04 at 06:54 -0400, Atlant Schmidt wrote:
> Matej:
> 
> > Artem, you said that this unstable bits only happen
> > during power cuts, is this right? Would those appear
> > also on simulated power cuts, the ones that integck
> > can produce?
> 
>   (Note: This isn't Artem replying.)
> 
>   Unstable bits can happen anytime, but *REAL* power-cuts
>   while writing are certainly a great way to produce them;
>   after all, if you've only transferred half the electrons
>   to the floating gate when power goes away, well, that
>   Flash cell is now a roll-of-the-quantum-dice each time
>   you read it.
> 
>   Simulated power cuts (that just stop the software
>   processing at arbitrary and random points) can't
>   produce this effect.
> 
>   But any time a read-disturb or write-disturb takes place,
>   there's some probability that a Flash cell will be left
>   with a "near-threshold" charge on the floating gate, so
>   unstable bits are a fact of life that must be faced by
>   any software that drives NAND Flash memory chips. This
>   is, of course, especially true of MLC chips and even
>   more-true for TLC chips (with three bits per cell).

Yeah, thanks for correcting. Yeah, read/write-disturb may make bits to
become unstable, but we assume this is a slow process which will
gradually make more and more bits flip and ECC will take care of that.
So I think Matej can exclude this.

-- 
Best Regards,
Artem Bityutskiy