From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 15/29] drm/i915: do not enable PCH PLL on pre-haswell Date: Fri, 13 Apr 2012 21:55:10 +0100 Message-ID: <1334350522_415727@CP5-2952> References: <1334347745-11743-1-git-send-email-eugeni.dodonov@intel.com> <1334347745-11743-16-git-send-email-eugeni.dodonov@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from fireflyinternet.com (smtp.fireflyinternet.com [109.228.6.236]) by gabe.freedesktop.org (Postfix) with ESMTP id 6A4639EB3C for ; Fri, 13 Apr 2012 13:55:26 -0700 (PDT) In-Reply-To: <1334347745-11743-16-git-send-email-eugeni.dodonov@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Eugeni Dodonov List-Id: intel-gfx@lists.freedesktop.org The PLL split needs to be reconsidered in light of Jesse's decoupling PLLs from the pipes. I think we want to start annotating those so that we can keep track of CPU vs PCH DP/FDI links and plls. -Chris -- Chris Wilson, Intel Open Source Technology Centre