[Qemu-devel] [PATCH qom-next 57/59] cpu: Introduce mandatory tlb_flush callback

["Andreas Färber" <afaerber@suse.de>]

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 include/qemu/cpu.h          |   12 ++++++++++++
 qom/cpu.c                   |    9 +++++++++
 target-alpha/cpu.c          |   16 ++++++++++++++++
 target-arm/cpu.c            |   10 ++++++++++
 target-cris/cpu.c           |   10 ++++++++++
 target-i386/cpu.c           |   10 ++++++++++
 target-lm32/cpu.c           |   10 ++++++++++
 target-m68k/cpu.c           |   10 ++++++++++
 target-microblaze/cpu.c     |   10 ++++++++++
 target-mips/cpu.c           |   10 ++++++++++
 target-ppc/translate_init.c |   10 ++++++++++
 target-s390x/cpu.c          |   10 ++++++++++
 target-sh4/cpu.c            |   10 ++++++++++
 target-sparc/cpu.c          |   10 ++++++++++
 target-unicore32/cpu.c      |   16 ++++++++++++++++
 target-xtensa/cpu.c         |   10 ++++++++++
 16 files changed, 173 insertions(+), 0 deletions(-)

diff --git a/include/qemu/cpu.h b/include/qemu/cpu.h
index 61b7698..7d03369 100644
--- a/include/qemu/cpu.h
+++ b/include/qemu/cpu.h
@@ -41,6 +41,7 @@ typedef struct CPUState CPUState;
 /**
  * CPUClass:
  * @reset: Callback to reset the #CPUState to its initial state.
+ * @tlb_flush: Callback to flush the TLB.
  *
  * Represents a CPU family or model.
  */
@@ -50,6 +51,8 @@ typedef struct CPUClass {
     /*< public >*/
 
     void (*reset)(CPUState *cpu);
+
+    void (*tlb_flush)(CPUState *cpu, bool flush_global);
 } CPUClass;
 
 /**
@@ -88,6 +91,15 @@ struct CPUState {
 void cpu_reset(CPUState *cpu);
 
 /**
+ * cpu_tlb_flush:
+ * @cpu: The CPU whose TLB is to be flushed.
+ * @flush_global: Whether to flush TLB entries marked as global.
+ *
+ * Flushes the TLB of the CPU.
+ */
+void cpu_tlb_flush(CPUState *cpu, bool flush_global);
+
+/**
  * qemu_cpu_has_work:
  * @cpu: The vCPU to check.
  *
diff --git a/qom/cpu.c b/qom/cpu.c
index 5b36046..729f4cf 100644
--- a/qom/cpu.c
+++ b/qom/cpu.c
@@ -34,6 +34,15 @@ static void cpu_common_reset(CPUState *cpu)
 {
 }
 
+void cpu_tlb_flush(CPUState *cpu, bool flush_global)
+{
+    CPUClass *cc = CPU_GET_CLASS(cpu);
+
+    g_assert(cc->tlb_flush != NULL);
+
+    cc->tlb_flush(cpu, flush_global);
+}
+
 static void cpu_class_init(ObjectClass *klass, void *data)
 {
     CPUClass *k = CPU_CLASS(klass);
diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c
index 11a19eb..d20f367 100644
--- a/target-alpha/cpu.c
+++ b/target-alpha/cpu.c
@@ -23,6 +23,14 @@
 #include "qemu-common.h"
 
 
+/* CPUClass::tlb_flush() */
+static void alpha_cpu_tlb_flush(CPUState *c, bool flush_global)
+{
+    AlphaCPU *cpu = ALPHA_CPU(c);
+
+    tlb_flush(&cpu->env, flush_global);
+}
+
 static void alpha_cpu_initfn(Object *obj)
 {
     AlphaCPU *cpu = ALPHA_CPU(obj);
@@ -41,6 +49,13 @@ static void alpha_cpu_initfn(Object *obj)
     env->fen = 1;
 }
 
+static void alpha_cpu_class_init(ObjectClass *oc, void *data)
+{
+    CPUClass *cc = CPU_CLASS(oc);
+
+    cc->tlb_flush = alpha_cpu_tlb_flush;
+}
+
 static const TypeInfo alpha_cpu_type_info = {
     .name = TYPE_ALPHA_CPU,
     .parent = TYPE_CPU,
@@ -48,6 +63,7 @@ static const TypeInfo alpha_cpu_type_info = {
     .instance_init = alpha_cpu_initfn,
     .abstract = false,
     .class_size = sizeof(AlphaCPUClass),
+    .class_init = alpha_cpu_class_init,
 };
 
 static void alpha_cpu_register_types(void)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 7eb323a..abcf158 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -120,6 +120,14 @@ static void arm_cpu_reset(CPUState *s)
     tb_flush(env);
 }
 
+/* CPUClass::tlb_flush() */
+static void arm_cpu_tlb_flush(CPUState *c, bool flush_global)
+{
+    ARMCPU *cpu = ARM_CPU(c);
+
+    tlb_flush(&cpu->env, flush_global);
+}
+
 static inline void set_feature(CPUARMState *env, int feature)
 {
     env->features |= 1u << feature;
@@ -637,6 +645,8 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
 
     acc->parent_reset = cc->reset;
     cc->reset = arm_cpu_reset;
+
+    cc->tlb_flush = arm_cpu_tlb_flush;
 }
 
 static void cpu_register(const ARMCPUInfo *info)
diff --git a/target-cris/cpu.c b/target-cris/cpu.c
index c596609..167ba30 100644
--- a/target-cris/cpu.c
+++ b/target-cris/cpu.c
@@ -55,6 +55,14 @@ static void cris_cpu_reset(CPUState *s)
 #endif
 }
 
+/* CPUClass::tlb_flush() */
+static void cris_cpu_tlb_flush(CPUState *c, bool flush_global)
+{
+    CRISCPU *cpu = CRIS_CPU(c);
+
+    tlb_flush(&cpu->env, flush_global);
+}
+
 static void cris_cpu_initfn(Object *obj)
 {
     CRISCPU *cpu = CRIS_CPU(obj);
@@ -70,6 +78,8 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
 
     ccc->parent_reset = cc->reset;
     cc->reset = cris_cpu_reset;
+
+    cc->tlb_flush = cris_cpu_tlb_flush;
 }
 
 static const TypeInfo cris_cpu_type_info = {
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 89b4ac7..c8e6b80 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -1706,6 +1706,14 @@ static void x86_cpu_reset(CPUState *s)
     cpu_watchpoint_remove_all(env, BP_CPU);
 }
 
+/* CPUClass::tlb_flush() */
+static void x86_cpu_tlb_flush(CPUState *c, bool flush_global)
+{
+    X86CPU *cpu = X86_CPU(c);
+
+    tlb_flush(&cpu->env, flush_global);
+}
+
 static void mce_init(X86CPU *cpu)
 {
     CPUX86State *cenv = &cpu->env;
@@ -1772,6 +1780,8 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
 
     xcc->parent_reset = cc->reset;
     cc->reset = x86_cpu_reset;
+
+    cc->tlb_flush = x86_cpu_tlb_flush;
 }
 
 static const TypeInfo x86_cpu_type_info = {
diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c
index caa4834..a58369e 100644
--- a/target-lm32/cpu.c
+++ b/target-lm32/cpu.c
@@ -42,6 +42,14 @@ static void lm32_cpu_reset(CPUState *s)
     memset(env, 0, offsetof(CPULM32State, breakpoints));
 }
 
+/* CPUClass::tlb_flush() */
+static void lm32_cpu_tlb_flush(CPUState *c, bool flush_global)
+{
+    LM32CPU *cpu = LM32_CPU(c);
+
+    tlb_flush(&cpu->env, flush_global);
+}
+
 static void lm32_cpu_initfn(Object *obj)
 {
     LM32CPU *cpu = LM32_CPU(obj);
@@ -61,6 +69,8 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
 
     lcc->parent_reset = cc->reset;
     cc->reset = lm32_cpu_reset;
+
+    cc->tlb_flush = lm32_cpu_tlb_flush;
 }
 
 static const TypeInfo lm32_cpu_type_info = {
diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c
index 3e70bb0..e1daeff 100644
--- a/target-m68k/cpu.c
+++ b/target-m68k/cpu.c
@@ -53,6 +53,14 @@ static void m68k_cpu_reset(CPUState *s)
     tlb_flush(env, 1);
 }
 
+/* CPUClass::tlb_flush() */
+static void m68k_cpu_tlb_flush(CPUState *c, bool flush_global)
+{
+    M68kCPU *cpu = M68K_CPU(c);
+
+    tlb_flush(&cpu->env, flush_global);
+}
+
 /* CPU models */
 
 static void m5206_cpu_initfn(Object *obj)
@@ -134,6 +142,8 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
 
     mcc->parent_reset = cc->reset;
     cc->reset = m68k_cpu_reset;
+
+    cc->tlb_flush = m68k_cpu_tlb_flush;
 }
 
 static void register_cpu_type(const M68kCPUInfo *info)
diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index 9c3b74e..a850d8f 100644
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -83,6 +83,14 @@ static void mb_cpu_reset(CPUState *s)
 #endif
 }
 
+/* CPUClass::tlb_flush() */
+static void mb_cpu_tlb_flush(CPUState *c, bool flush_global)
+{
+    MicroBlazeCPU *cpu = MICROBLAZE_CPU(c);
+
+    tlb_flush(&cpu->env, flush_global);
+}
+
 static void mb_cpu_initfn(Object *obj)
 {
     MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj);
@@ -100,6 +108,8 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
 
     mcc->parent_reset = cc->reset;
     cc->reset = mb_cpu_reset;
+
+    cc->tlb_flush = mb_cpu_tlb_flush;
 }
 
 static const TypeInfo mb_cpu_type_info = {
diff --git a/target-mips/cpu.c b/target-mips/cpu.c
index 0044062..7e51a2b 100644
--- a/target-mips/cpu.c
+++ b/target-mips/cpu.c
@@ -34,6 +34,14 @@ static void mips_cpu_reset(CPUState *s)
     cpu_state_reset(env);
 }
 
+/* CPUClass::tlb_flush() */
+static void mips_cpu_tlb_flush(CPUState *c, bool flush_global)
+{
+    MIPSCPU *cpu = MIPS_CPU(c);
+
+    tlb_flush(&cpu->env, flush_global);
+}
+
 static void mips_cpu_initfn(Object *obj)
 {
     MIPSCPU *cpu = MIPS_CPU(obj);
@@ -49,6 +57,8 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
 
     mcc->parent_reset = cc->reset;
     cc->reset = mips_cpu_reset;
+
+    cc->tlb_flush = mips_cpu_tlb_flush;
 }
 
 static const TypeInfo mips_cpu_type_info = {
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 6f61175..5bebd84 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -10266,6 +10266,14 @@ static void ppc_cpu_reset(CPUState *s)
     tlb_flush(env, 1);
 }
 
+/* CPUClass::tlb_flush() */
+static void ppc_cpu_tlb_flush(CPUState *c, bool flush_global)
+{
+    PowerPCCPU *cpu = POWERPC_CPU(c);
+
+    tlb_flush(&cpu->env, flush_global);
+}
+
 static void ppc_cpu_initfn(Object *obj)
 {
     PowerPCCPU *cpu = POWERPC_CPU(obj);
@@ -10281,6 +10289,8 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
 
     pcc->parent_reset = cc->reset;
     cc->reset = ppc_cpu_reset;
+
+    cc->tlb_flush = ppc_cpu_tlb_flush;
 }
 
 static const TypeInfo ppc_cpu_type_info = {
diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c
index 619b202..b87e307 100644
--- a/target-s390x/cpu.c
+++ b/target-s390x/cpu.c
@@ -45,6 +45,14 @@ static void s390_cpu_reset(CPUState *s)
     s390_add_running_cpu(env);
 }
 
+/* CPUClass::tlb_flush() */
+static void s390_cpu_tlb_flush(CPUState *c, bool flush_global)
+{
+    S390CPU *cpu = S390_CPU(c);
+
+    tlb_flush(&cpu->env, flush_global);
+}
+
 static void s390_cpu_initfn(Object *obj)
 {
     S390CPU *cpu = S390_CPU(obj);
@@ -76,6 +84,8 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
 
     scc->parent_reset = cc->reset;
     cc->reset = s390_cpu_reset;
+
+    cc->tlb_flush = s390_cpu_tlb_flush;
 }
 
 static const TypeInfo s390_cpu_type_info = {
diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
index a1a177f..a0727bc 100644
--- a/target-sh4/cpu.c
+++ b/target-sh4/cpu.c
@@ -53,6 +53,14 @@ static void superh_cpu_reset(CPUState *s)
     set_default_nan_mode(1, &env->fp_status);
 }
 
+/* CPUClass::tlb_flush() */
+static void superh_cpu_tlb_flush(CPUState *c, bool flush_global)
+{
+    SuperHCPU *cpu = SUPERH_CPU(c);
+
+    tlb_flush(&cpu->env, flush_global);
+}
+
 static void superh_cpu_initfn(Object *obj)
 {
     SuperHCPU *cpu = SUPERH_CPU(obj);
@@ -70,6 +78,8 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
 
     scc->parent_reset = cc->reset;
     cc->reset = superh_cpu_reset;
+
+    cc->tlb_flush = superh_cpu_tlb_flush;
 }
 
 static const TypeInfo superh_cpu_type_info = {
diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
index f7c004c..7216b42 100644
--- a/target-sparc/cpu.c
+++ b/target-sparc/cpu.c
@@ -74,6 +74,14 @@ static void sparc_cpu_reset(CPUState *s)
     env->cache_control = 0;
 }
 
+/* CPUClass::tlb_flush() */
+static void sparc_cpu_tlb_flush(CPUState *c, bool flush_global)
+{
+    SPARCCPU *cpu = SPARC_CPU(c);
+
+    tlb_flush(&cpu->env, flush_global);
+}
+
 static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model)
 {
     sparc_def_t def1, *def = &def1;
@@ -875,6 +883,8 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
 
     scc->parent_reset = cc->reset;
     cc->reset = sparc_cpu_reset;
+
+    cc->tlb_flush = sparc_cpu_tlb_flush;
 }
 
 static const TypeInfo sparc_cpu_type_info = {
diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
index 5467728..cc00bc2 100644
--- a/target-unicore32/cpu.c
+++ b/target-unicore32/cpu.c
@@ -20,6 +20,14 @@ static inline void set_feature(CPUUniCore32State *env, int feature)
     env->features |= feature;
 }
 
+/* CPUClass::tlb_flush() */
+static void uc32_cpu_tlb_flush(CPUState *c, bool flush_global)
+{
+    UniCore32CPU *cpu = UNICORE32_CPU(c);
+
+    tlb_flush(&cpu->env, flush_global);
+}
+
 /* CPU models */
 
 typedef struct UniCore32CPUInfo {
@@ -71,6 +79,13 @@ static void uc32_cpu_initfn(Object *obj)
     tlb_flush(env, 1);
 }
 
+static void uc32_cpu_class_init(ObjectClass *oc, void *data)
+{
+    CPUClass *cc = CPU_CLASS(oc);
+
+    cc->tlb_flush = uc32_cpu_tlb_flush;
+}
+
 static void uc32_register_cpu_type(const UniCore32CPUInfo *info)
 {
     TypeInfo type_info = {
@@ -89,6 +104,7 @@ static const TypeInfo uc32_cpu_type_info = {
     .instance_init = uc32_cpu_initfn,
     .abstract = true,
     .class_size = sizeof(UniCore32CPUClass),
+    .class_init = uc32_cpu_class_init,
 };
 
 static void uc32_cpu_register_types(void)
diff --git a/target-xtensa/cpu.c b/target-xtensa/cpu.c
index 9d01983..59671c1 100644
--- a/target-xtensa/cpu.c
+++ b/target-xtensa/cpu.c
@@ -53,6 +53,14 @@ static void xtensa_cpu_reset(CPUState *s)
     reset_mmu(env);
 }
 
+/* CPUClass::tlb_flush() */
+static void xtensa_cpu_tlb_flush(CPUState *c, bool flush_global)
+{
+    XtensaCPU *cpu = XTENSA_CPU(c);
+
+    tlb_flush(&cpu->env, flush_global);
+}
+
 static void xtensa_cpu_initfn(Object *obj)
 {
     XtensaCPU *cpu = XTENSA_CPU(obj);
@@ -68,6 +76,8 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
 
     xcc->parent_reset = cc->reset;
     cc->reset = xtensa_cpu_reset;
+
+    cc->tlb_flush = xtensa_cpu_tlb_flush;
 }
 
 static const TypeInfo xtensa_cpu_type_info = {
-- 
1.7.7