From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:44819) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SX1wf-0000KG-Pq for qemu-devel@nongnu.org; Tue, 22 May 2012 23:09:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SX1wc-0005ad-KO for qemu-devel@nongnu.org; Tue, 22 May 2012 23:09:05 -0400 Received: from cantor2.suse.de ([195.135.220.15]:35555 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SX1wc-0005ZS-7t for qemu-devel@nongnu.org; Tue, 22 May 2012 23:09:02 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Wed, 23 May 2012 05:07:28 +0200 Message-Id: <1337742502-28565-6-git-send-email-afaerber@suse.de> In-Reply-To: <1337742502-28565-1-git-send-email-afaerber@suse.de> References: <1337742502-28565-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH qom-next 05/59] apic: Replace cpu_env pointer by X86CPU link List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Anthony Liguori , =?UTF-8?q?Andreas=20F=C3=A4rber?= Needed for converting cpu_is_bsp(). Signed-off-by: Andreas F=C3=A4rber Cc: Paolo Bonzini --- hw/apic.c | 34 +++++++++++++++++++--------------- hw/apic_common.c | 14 +++++++++++--- hw/apic_internal.h | 2 +- hw/kvm/apic.c | 9 +++++---- hw/pc.c | 9 ++++++++- 5 files changed, 44 insertions(+), 24 deletions(-) diff --git a/hw/apic.c b/hw/apic.c index 4eeaf88..1207c33 100644 --- a/hw/apic.c +++ b/hw/apic.c @@ -114,7 +114,7 @@ static void apic_sync_vapic(APICCommonState *s, int s= ync_type) length =3D offsetof(VAPICState, enabled) - offsetof(VAPICState, = isr); =20 if (sync_type & SYNC_TO_VAPIC) { - assert(qemu_cpu_is_self(s->cpu_env)); + assert(qemu_cpu_is_self(&s->cpu->env)); =20 vapic_state.tpr =3D s->tpr; vapic_state.enabled =3D 1; @@ -158,15 +158,15 @@ static void apic_local_deliver(APICCommonState *s, = int vector) =20 switch ((lvt >> 8) & 7) { case APIC_DM_SMI: - cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SMI); + cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_SMI); break; =20 case APIC_DM_NMI: - cpu_interrupt(s->cpu_env, CPU_INTERRUPT_NMI); + cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_NMI); break; =20 case APIC_DM_EXTINT: - cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); + cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD); break; =20 case APIC_DM_FIXED: @@ -194,7 +194,7 @@ void apic_deliver_pic_intr(DeviceState *d, int level) reset_bit(s->irr, lvt & 0xff); /* fall through */ case APIC_DM_EXTINT: - cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); + cpu_reset_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD); break; } } @@ -255,18 +255,22 @@ static void apic_bus_deliver(const uint32_t *delive= r_bitmask, =20 case APIC_DM_SMI: foreach_apic(apic_iter, deliver_bitmask, - cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) ); + cpu_interrupt(&apic_iter->cpu->env, CPU_INTERRUPT_SMI) + ); return; =20 case APIC_DM_NMI: foreach_apic(apic_iter, deliver_bitmask, - cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) ); + cpu_interrupt(&apic_iter->cpu->env, CPU_INTERRUPT_NMI) + ); return; =20 case APIC_DM_INIT: /* normal INIT IPI sent to processors */ foreach_apic(apic_iter, deliver_bitmask, - cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT= _INIT) ); + cpu_interrupt(&apic_iter->cpu->env, + CPU_INTERRUPT_INIT) + ); return; =20 case APIC_DM_EXTINT: @@ -300,7 +304,7 @@ static void apic_set_base(APICCommonState *s, uint64_= t val) /* if disabled, cannot be enabled again */ if (!(val & MSR_IA32_APICBASE_ENABLE)) { s->apicbase &=3D ~MSR_IA32_APICBASE_ENABLE; - cpu_clear_apic_feature(s->cpu_env); + cpu_clear_apic_feature(&s->cpu->env); s->spurious_vec &=3D ~APIC_SV_ENABLE; } } @@ -370,7 +374,7 @@ static void apic_update_irq(APICCommonState *s) return; } if (apic_irq_pending(s) > 0) { - cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); + cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD); } else if (apic_accept_pic_intr(&s->busdev.qdev) && pic_get_output(isa_pic)) { apic_deliver_pic_intr(&s->busdev.qdev, 1); @@ -480,18 +484,18 @@ static void apic_get_delivery_bitmask(uint32_t *del= iver_bitmask, static void apic_startup(APICCommonState *s, int vector_num) { s->sipi_vector =3D vector_num; - cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI); + cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_SIPI); } =20 void apic_sipi(DeviceState *d) { APICCommonState *s =3D DO_UPCAST(APICCommonState, busdev.qdev, d); =20 - cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI); + cpu_reset_interrupt(&s->cpu->env, CPU_INTERRUPT_SIPI); =20 if (!s->wait_for_sipi) return; - cpu_x86_load_seg_cache_sipi(s->cpu_env, s->sipi_vector); + cpu_x86_load_seg_cache_sipi(&s->cpu->env, s->sipi_vector); s->wait_for_sipi =3D 0; } =20 @@ -666,7 +670,7 @@ static uint32_t apic_mem_readl(void *opaque, target_p= hys_addr_t addr) case 0x08: apic_sync_vapic(s, SYNC_FROM_VAPIC); if (apic_report_tpr_access) { - cpu_report_tpr_access(s->cpu_env, TPR_ACCESS_READ); + cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_READ); } val =3D s->tpr; break; @@ -768,7 +772,7 @@ static void apic_mem_writel(void *opaque, target_phys= _addr_t addr, uint32_t val) break; case 0x08: if (apic_report_tpr_access) { - cpu_report_tpr_access(s->cpu_env, TPR_ACCESS_WRITE); + cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_WRITE); } s->tpr =3D val; apic_sync_vapic(s, SYNC_TO_VAPIC); diff --git a/hw/apic_common.c b/hw/apic_common.c index 60b8259..46a9ff7 100644 --- a/hw/apic_common.c +++ b/hw/apic_common.c @@ -103,7 +103,7 @@ void apic_handle_tpr_access_report(DeviceState *d, ta= rget_ulong ip, { APICCommonState *s =3D DO_UPCAST(APICCommonState, busdev.qdev, d); =20 - vapic_report_tpr_access(s->vapic, s->cpu_env, ip, access); + vapic_report_tpr_access(s->vapic, &s->cpu->env, ip, access); } =20 void apic_report_irq_delivered(int delivered) @@ -207,7 +207,7 @@ static void apic_reset_common(DeviceState *d) APICCommonClass *info =3D APIC_COMMON_GET_CLASS(s); bool bsp; =20 - bsp =3D cpu_is_bsp(s->cpu_env); + bsp =3D cpu_is_bsp(&s->cpu->env); s->apicbase =3D 0xfee00000 | (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE; =20 @@ -354,9 +354,16 @@ static const VMStateDescription vmstate_apic_common = =3D { } }; =20 +static void apic_common_initfn(Object *obj) +{ + APICCommonState *s =3D APIC_COMMON(obj); + + object_property_add_link(obj, "cpu", TYPE_X86_CPU, (Object **)&s->cp= u, + NULL); +} + static Property apic_properties_common[] =3D { DEFINE_PROP_UINT8("id", APICCommonState, id, -1), - DEFINE_PROP_PTR("cpu_env", APICCommonState, cpu_env), DEFINE_PROP_BIT("vapic", APICCommonState, vapic_control, VAPIC_ENABL= E_BIT, true), DEFINE_PROP_END_OF_LIST(), @@ -378,6 +385,7 @@ static TypeInfo apic_common_type =3D { .name =3D TYPE_APIC_COMMON, .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(APICCommonState), + .instance_init =3D apic_common_initfn, .class_size =3D sizeof(APICCommonClass), .class_init =3D apic_common_class_init, .abstract =3D true, diff --git a/hw/apic_internal.h b/hw/apic_internal.h index 60a6a8b..645718c 100644 --- a/hw/apic_internal.h +++ b/hw/apic_internal.h @@ -96,7 +96,7 @@ typedef struct APICCommonClass struct APICCommonState { SysBusDevice busdev; MemoryRegion io_memory; - void *cpu_env; + X86CPU *cpu; uint32_t apicbase; uint8_t id; uint8_t arb_id; diff --git a/hw/kvm/apic.c b/hw/kvm/apic.c index ffe7a52..cf52bb2 100644 --- a/hw/kvm/apic.c +++ b/hw/kvm/apic.c @@ -103,7 +103,7 @@ static void kvm_apic_enable_tpr_reporting(APICCommonS= tate *s, bool enable) .enabled =3D enable }; =20 - kvm_vcpu_ioctl(s->cpu_env, KVM_TPR_ACCESS_REPORTING, &ctl); + kvm_vcpu_ioctl(&s->cpu->env, KVM_TPR_ACCESS_REPORTING, &ctl); } =20 static void kvm_apic_vapic_base_update(APICCommonState *s) @@ -113,7 +113,7 @@ static void kvm_apic_vapic_base_update(APICCommonStat= e *s) }; int ret; =20 - ret =3D kvm_vcpu_ioctl(s->cpu_env, KVM_SET_VAPIC_ADDR, &vapid_addr); + ret =3D kvm_vcpu_ioctl(&s->cpu->env, KVM_SET_VAPIC_ADDR, &vapid_addr= ); if (ret < 0) { fprintf(stderr, "KVM: setting VAPIC address failed (%s)\n", strerror(-ret)); @@ -124,7 +124,8 @@ static void kvm_apic_vapic_base_update(APICCommonStat= e *s) static void do_inject_external_nmi(void *data) { APICCommonState *s =3D data; - CPUX86State *env =3D s->cpu_env; + X86CPU *cpu =3D s->cpu; + CPUX86State *env =3D &cpu->env; uint32_t lvt; int ret; =20 @@ -142,7 +143,7 @@ static void do_inject_external_nmi(void *data) =20 static void kvm_apic_external_nmi(APICCommonState *s) { - run_on_cpu(s->cpu_env, do_inject_external_nmi, s); + run_on_cpu(&s->cpu->env, do_inject_external_nmi, s); } =20 static void kvm_apic_init(APICCommonState *s) diff --git a/hw/pc.c b/hw/pc.c index e9d7e05..6bb3d2a 100644 --- a/hw/pc.c +++ b/hw/pc.c @@ -888,6 +888,7 @@ DeviceState *cpu_get_current_apic(void) static DeviceState *apic_init(void *env, uint8_t apic_id) { DeviceState *dev; + Error *error =3D NULL; static int apic_mapped; =20 if (kvm_irqchip_in_kernel()) { @@ -899,7 +900,13 @@ static DeviceState *apic_init(void *env, uint8_t api= c_id) } =20 qdev_prop_set_uint8(dev, "id", apic_id); - qdev_prop_set_ptr(dev, "cpu_env", env); + object_property_set_link(OBJECT(dev), OBJECT(ENV_GET_CPU(env)), "cpu= ", + &error); + if (error_is_set(&error)) { + qerror_report_err(error); + error_free(error); + exit(1); + } qdev_init_nofail(dev); =20 /* XXX: mapping more APICs at the same memory location */ --=20 1.7.7