From mboxrd@z Thu Jan 1 00:00:00 1970 From: Valentin Longchamp Date: Thu, 7 Jun 2012 12:06:55 +0200 Subject: [U-Boot] [PATCH 15/20] arm/km: support the 2 PCIe fpga resets In-Reply-To: <1339063620-8890-1-git-send-email-valentin.longchamp@keymile.com> References: <1339063620-8890-1-git-send-email-valentin.longchamp@keymile.com> Message-ID: <1339063620-8890-16-git-send-email-valentin.longchamp@keymile.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de The PCIe FPGAs now have to support 2 resets: one for the non traffic affecting part (PCIe) and one for the traffic affecting part. When the FPGA is not reconfigured, we only reset the PCIe part. Signed-off-by: Valentin Longchamp --- board/keymile/km_arm/fpga_config.c | 13 +++++++++---- 1 files changed, 9 insertions(+), 4 deletions(-) diff --git a/board/keymile/km_arm/fpga_config.c b/board/keymile/km_arm/fpga_config.c index 8ac6393..fcc5fe6 100644 --- a/board/keymile/km_arm/fpga_config.c +++ b/board/keymile/km_arm/fpga_config.c @@ -99,7 +99,7 @@ static int boco_set_bits(u8 reg, u8 flags) #define FPGA_INIT_B 0x10 #define FPGA_DONE 0x20 -static int fpga_done() +static int fpga_done(void) { int ret = 0; u8 regval; @@ -206,25 +206,30 @@ int wait_for_fpga_config(void) } #define PRST1 0x4 -#define BRIDGE_RST 0x4 +#define PCIE_RST 0x10 +#define TRAFFIC_RST 0x04 int fpga_reset(void) { int ret = 0; + u8 resets; if (!check_boco2()) { /* we do not have BOCO2, this is not really used */ return 0; } - ret = boco_clear_bits(PRST1, BRIDGE_RST); + /* if we have skipped, we only want to reset the PCIe part */ + resets = skip ? PCIE_RST : PCIE_RST | TRAFFIC_RST; + + ret = boco_clear_bits(PRST1, resets); if (ret) return ret; /* small delay for the pulse */ udelay(10); - ret = boco_set_bits(PRST1, BRIDGE_RST); + ret = boco_set_bits(PRST1, resets); if (ret) return ret; -- 1.7.1