From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756417Ab2FNQvr (ORCPT ); Thu, 14 Jun 2012 12:51:47 -0400 Received: from mail.work-microwave.de ([62.245.205.51]:29133 "EHLO work-microwave.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932134Ab2FNQve (ORCPT ); Thu, 14 Jun 2012 12:51:34 -0400 From: Roland Stigge To: arm@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kevin.wells@nxp.com, srinivas.bakki@nxp.com, aletes.xgr@gmail.com Cc: Roland Stigge Subject: [PATCH v2 06/23] ARM: LPC32xx: Add dts for EA3250 reference board Date: Thu, 14 Jun 2012 18:50:56 +0200 Message-Id: <1339692673-7848-7-git-send-email-stigge@antcom.de> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1339692673-7848-1-git-send-email-stigge@antcom.de> References: <1339692673-7848-1-git-send-email-stigge@antcom.de> X-FEAS-SYSTEM-WL: rst@work-microwave.de, 192.168.11.78 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org There is another reference/development board for the LPC32xx SoC (besides the Phytec 3250): The Embedded Artists LPC3250 board. This patch adds a default dts file for it. Signed-off-by: Roland Stigge Acked-by: Alexandre Pereira da Silva --- arch/arm/boot/dts/ea3250.dts | 157 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 157 insertions(+) --- /dev/null +++ linux-2.6/arch/arm/boot/dts/ea3250.dts @@ -0,0 +1,157 @@ +/* + * Embedded Artists LPC3250 board + * + * Copyright 2012 Roland Stigge + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "lpc32xx.dtsi" + +/ { + model = "Embedded Artists LPC3250 board based on NXP LPC3250"; + compatible = "ea,ea3250", "nxp,lpc3250"; + #address-cells = <1>; + #size-cells = <1>; + + memory { + device_type = "memory"; + reg = <0 0x4000000>; + }; + + ahb { + mac: ethernet@31060000 { + phy-mode = "rmii"; + use-iram; + }; + + /* Here, choose exactly one from: ohci, usbd */ + ohci@31020000 { + transceiver = <&isp1301>; + status = "okay"; + }; + +/* + usbd@31020000 { + transceiver = <&isp1301>; + status = "okay"; + }; +*/ + + /* 128MB Flash via SLC NAND controller */ + slc: flash@20020000 { + status = "okay"; + #address-cells = <1>; + #size-cells = <1>; + + nxp,wdr-clks = <14>; + nxp,wwidth = <260000000>; + nxp,whold = <104000000>; + nxp,wsetup = <200000000>; + nxp,rdr-clks = <14>; + nxp,rwidth = <34666666>; + nxp,rhold = <104000000>; + nxp,rsetup = <200000000>; + nand-on-flash-bbt; + gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ + + mtd0@00000000 { + label = "ea3250-boot"; + reg = <0x00000000 0x00080000>; + read-only; + }; + + mtd1@00080000 { + label = "ea3250-uboot"; + reg = <0x00080000 0x000c0000>; + read-only; + }; + + mtd2@00140000 { + label = "ea3250-kernel"; + reg = <0x00140000 0x00400000>; + }; + + mtd3@00540000 { + label = "ea3250-rootfs"; + reg = <0x00540000 0x07ac0000>; + }; + }; + + apb { + uart5: serial@40090000 { + status = "okay"; + }; + + uart3: serial@40080000 { + status = "okay"; + }; + + uart6: serial@40098000 { + status = "okay"; + }; + + i2c1: i2c@400A0000 { + clock-frequency = <100000>; + + eeprom@50 { + compatible = "at,24c256"; + reg = <0x50>; + }; + + eeprom@57 { + compatible = "at,24c64"; + reg = <0x57>; + }; + + uda1380: uda1380@18 { + compatible = "nxp,uda1380"; + reg = <0x18>; + power-gpio = <&gpio 0x59 0>; + reset-gpio = <&gpio 0x51 0>; + dac-clk = "wspll"; + }; + + pca9532: pca9532@60 { + compatible = "nxp,pca9532"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x60>; + }; + }; + + i2c2: i2c@400A8000 { + clock-frequency = <100000>; + }; + + i2cusb: i2c@31020300 { + clock-frequency = <100000>; + + isp1301: usb-transceiver@2d { + compatible = "nxp,isp1301"; + reg = <0x2d>; + }; + }; + + sd@20098000 { + wp-gpios = <&pca9532 5 0>; + cd-gpios = <&pca9532 4 0>; + cd-inverted; + bus-width = <4>; + status = "okay"; + }; + }; + + fab { + uart1: serial@40014000 { + status = "okay"; + }; + }; + }; +}; From mboxrd@z Thu Jan 1 00:00:00 1970 From: stigge@antcom.de (Roland Stigge) Date: Thu, 14 Jun 2012 18:50:56 +0200 Subject: [PATCH v2 06/23] ARM: LPC32xx: Add dts for EA3250 reference board In-Reply-To: <1339692673-7848-1-git-send-email-stigge@antcom.de> References: <1339692673-7848-1-git-send-email-stigge@antcom.de> Message-ID: <1339692673-7848-7-git-send-email-stigge@antcom.de> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org There is another reference/development board for the LPC32xx SoC (besides the Phytec 3250): The Embedded Artists LPC3250 board. This patch adds a default dts file for it. Signed-off-by: Roland Stigge Acked-by: Alexandre Pereira da Silva --- arch/arm/boot/dts/ea3250.dts | 157 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 157 insertions(+) --- /dev/null +++ linux-2.6/arch/arm/boot/dts/ea3250.dts @@ -0,0 +1,157 @@ +/* + * Embedded Artists LPC3250 board + * + * Copyright 2012 Roland Stigge + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "lpc32xx.dtsi" + +/ { + model = "Embedded Artists LPC3250 board based on NXP LPC3250"; + compatible = "ea,ea3250", "nxp,lpc3250"; + #address-cells = <1>; + #size-cells = <1>; + + memory { + device_type = "memory"; + reg = <0 0x4000000>; + }; + + ahb { + mac: ethernet at 31060000 { + phy-mode = "rmii"; + use-iram; + }; + + /* Here, choose exactly one from: ohci, usbd */ + ohci at 31020000 { + transceiver = <&isp1301>; + status = "okay"; + }; + +/* + usbd at 31020000 { + transceiver = <&isp1301>; + status = "okay"; + }; +*/ + + /* 128MB Flash via SLC NAND controller */ + slc: flash at 20020000 { + status = "okay"; + #address-cells = <1>; + #size-cells = <1>; + + nxp,wdr-clks = <14>; + nxp,wwidth = <260000000>; + nxp,whold = <104000000>; + nxp,wsetup = <200000000>; + nxp,rdr-clks = <14>; + nxp,rwidth = <34666666>; + nxp,rhold = <104000000>; + nxp,rsetup = <200000000>; + nand-on-flash-bbt; + gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ + + mtd0 at 00000000 { + label = "ea3250-boot"; + reg = <0x00000000 0x00080000>; + read-only; + }; + + mtd1 at 00080000 { + label = "ea3250-uboot"; + reg = <0x00080000 0x000c0000>; + read-only; + }; + + mtd2 at 00140000 { + label = "ea3250-kernel"; + reg = <0x00140000 0x00400000>; + }; + + mtd3 at 00540000 { + label = "ea3250-rootfs"; + reg = <0x00540000 0x07ac0000>; + }; + }; + + apb { + uart5: serial at 40090000 { + status = "okay"; + }; + + uart3: serial at 40080000 { + status = "okay"; + }; + + uart6: serial at 40098000 { + status = "okay"; + }; + + i2c1: i2c at 400A0000 { + clock-frequency = <100000>; + + eeprom at 50 { + compatible = "at,24c256"; + reg = <0x50>; + }; + + eeprom at 57 { + compatible = "at,24c64"; + reg = <0x57>; + }; + + uda1380: uda1380 at 18 { + compatible = "nxp,uda1380"; + reg = <0x18>; + power-gpio = <&gpio 0x59 0>; + reset-gpio = <&gpio 0x51 0>; + dac-clk = "wspll"; + }; + + pca9532: pca9532 at 60 { + compatible = "nxp,pca9532"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x60>; + }; + }; + + i2c2: i2c at 400A8000 { + clock-frequency = <100000>; + }; + + i2cusb: i2c at 31020300 { + clock-frequency = <100000>; + + isp1301: usb-transceiver at 2d { + compatible = "nxp,isp1301"; + reg = <0x2d>; + }; + }; + + sd at 20098000 { + wp-gpios = <&pca9532 5 0>; + cd-gpios = <&pca9532 4 0>; + cd-inverted; + bus-width = <4>; + status = "okay"; + }; + }; + + fab { + uart1: serial at 40014000 { + status = "okay"; + }; + }; + }; +};