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[174.21.70.228]) by smtp.gmail.com with ESMTPSA id u28sm1199340pfl.140.2021.05.23.21.47.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 23 May 2021 21:47:27 -0700 (PDT) Subject: Re: [PATCH 00/24] target/ppc: Clean up mmu translation To: David Gibson References: <20210518201146.794854-1-richard.henderson@linaro.org> <7a4c91d4-c813-2803-e5e7-4f8fe6d6f05d@linaro.org> <6bc68cda-a6aa-68c9-2c6f-f7c6ff95b7db@linaro.org> From: Richard Henderson Message-ID: <133f0451-9083-b57e-20d5-019a8aec89ba@linaro.org> Date: Sun, 23 May 2021 23:47:25 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 5/23/21 10:26 PM, David Gibson wrote: > On Wed, May 19, 2021 at 05:47:05PM -0500, Richard Henderson wrote: >> On 5/19/21 3:37 PM, Richard Henderson wrote: >>> On 5/18/21 9:52 PM, David Gibson wrote: >>>> I've applied 1..15, still looking at the rest. >>> >>> Please dequeue.  I want to create a new mmu-internal.h, which affects >>> all the patches from #1. >> >> Alternately, don't. I can move the function later, and it may be a while >> before I can get back to this. > > Ok, I'll leave them in, since they're good cleanups even without the > rest of the series. > >> >> Two outstanding bugs: >> >> (1) mmu-radix64.c vs hypervisors. You'll not see these unless you run kvm >> inside of tcg. >> >> Basically, all usage of msr_{hv,pr,ir,dr} within ppc_*_xlate is incorrect. >> We should be pulling these from the 3 bits of mmu_idx, as outlined in the >> table in hreg_compute_hflags_value. > > Ah, that's probably my fault. I reworked those substantially from the > original code (closer to mmu_helper.c). I guess I didn't (and I > suspect I still don't) really understand how the softmmu works. > >> When you start propagating that around, you see that the second-level >> translation for loading the pte (2 of the 3 calls to >> ppc_radix64_partition_scoped_xlate) should not be using the mmu_idx related >> to the user-mode guest access, but should be using the mmu_idx of the >> kernel/hypervisor that owns the page table. >> >> I can't see that mmu-radix64.c has the same problem. I'm not really sure >> how the second-level translation for hypervisors works there. Is it by the >> hypervisor altering the hash table as it is loaded? > > Uh.. you started by saying mmu-radix64.c then talked about the hash > table, so I'm not sure which model you're talking about. radix64 definitely has a problem. Then I wondered if hash64 had the same problem. > > For hash + hypervisor, then yes, there is no hardware 2-level > translation, it all works by paravirtualizing updates to the hash > table (this is the H_ENTER etc. code in hw/ppc/spapr_softmmu.c). Ah, gotcha. So, no, hash64 is unaffected. > Indeed. Direct store segments are basically ancient history of the > POWER architecture which Linux never used, and I don't think much else > did either. So I'm inclined to go with > > (D) Just rip out all the direct store segment code and replace with > some LOG_UNIMPs. Re-adding it working can be the job of the > probably non-existent person who has an actual use case using > them. Fair enough. r~