From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:39726) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ShKSp-0004GH-DF for qemu-devel@nongnu.org; Wed, 20 Jun 2012 08:56:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ShKSi-00026d-Ns for qemu-devel@nongnu.org; Wed, 20 Jun 2012 08:56:50 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:59525) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ShKSi-00025V-Fw for qemu-devel@nongnu.org; Wed, 20 Jun 2012 08:56:44 -0400 From: Peter Maydell Date: Wed, 20 Jun 2012 13:27:18 +0100 Message-Id: <1340195241-16620-31-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1340195241-16620-1-git-send-email-peter.maydell@linaro.org> References: <1340195241-16620-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 30/33] target-arm: Remove c0_cachetype CPUARMState field List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Blue Swirl Cc: qemu-devel@nongnu.org, Anthony Liguori , Paul Brook Remove the no-longer-used CPUARMState c0_cachetype field. Although this was a constant register we had it in our migration state. Drop this (with resulting version bump) because for ARM currently we prefer cleaner migration code and have not stabilised migration format yet. Signed-off-by: Peter Maydell --- target-arm/cpu.h | 3 +-- target-arm/machine.c | 2 -- 2 files changed, 1 insertions(+), 4 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 2630fe7..27e398b 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -107,7 +107,6 @@ typedef struct CPUARMState { /* System control coprocessor (cp15) */ struct { uint32_t c0_cpuid; - uint32_t c0_cachetype; uint32_t c0_cssel; /* Cache size selection. */ uint32_t c1_sys; /* System control register. */ uint32_t c1_coproc; /* Coprocessor access register. */ @@ -664,7 +663,7 @@ static inline CPUARMState *cpu_init(const char *cpu_model) #define cpu_signal_handler cpu_arm_signal_handler #define cpu_list arm_cpu_list -#define CPU_SAVE_VERSION 6 +#define CPU_SAVE_VERSION 7 /* MMU modes definitions */ #define MMU_MODE0_SUFFIX _kernel diff --git a/target-arm/machine.c b/target-arm/machine.c index f66b8df..a2a75fb 100644 --- a/target-arm/machine.c +++ b/target-arm/machine.c @@ -21,7 +21,6 @@ void cpu_save(QEMUFile *f, void *opaque) qemu_put_be32(f, env->fiq_regs[i]); } qemu_put_be32(f, env->cp15.c0_cpuid); - qemu_put_be32(f, env->cp15.c0_cachetype); qemu_put_be32(f, env->cp15.c0_cssel); qemu_put_be32(f, env->cp15.c1_sys); qemu_put_be32(f, env->cp15.c1_coproc); @@ -139,7 +138,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) env->fiq_regs[i] = qemu_get_be32(f); } env->cp15.c0_cpuid = qemu_get_be32(f); - env->cp15.c0_cachetype = qemu_get_be32(f); env->cp15.c0_cssel = qemu_get_be32(f); env->cp15.c1_sys = qemu_get_be32(f); env->cp15.c1_coproc = qemu_get_be32(f); -- 1.7.1