From mboxrd@z Thu Jan 1 00:00:00 1970 From: mathieu.poirier at linaro.org Date: Wed, 4 Jul 2012 08:58:35 -0600 Subject: [U-Boot] [RESEND 11/11] snowball: Adding board specific cache cleanup routine In-Reply-To: <1341413915-7944-1-git-send-email-mathieu.poirier@linaro.org> References: <1341413915-7944-1-git-send-email-mathieu.poirier@linaro.org> Message-ID: <1341413915-7944-12-git-send-email-mathieu.poirier@linaro.org> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: "Mathieu J. Poirier" Following ARM's reference manuel for initializing the cache - the kernel won't boot otherwise. Signed-off-by: Mathieu Poirier Signed-off-by: John Rigby --- Changes for v2: - Correcting cache maintenance register address. - Invalidating all 16 bits in cache maintenance register. - Polling cache maintenance register for cleared bits. - Added comments to the code. - Re-worked commit description. --- arch/arm/cpu/armv7/u8500/cpu.c | 16 ++++++++++++++++ 1 files changed, 16 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/u8500/cpu.c b/arch/arm/cpu/armv7/u8500/cpu.c index 02bb332..50d5a83 100644 --- a/arch/arm/cpu/armv7/u8500/cpu.c +++ b/arch/arm/cpu/armv7/u8500/cpu.c @@ -73,6 +73,22 @@ static unsigned int read_asicid(void) return readl(address); } +void cpu_cache_initialization(void) +{ + /* invalidate all cache entries */ + *((volatile unsigned int *)(0xA041277C)) = 0xFFFF; + + /* ways are set to '0' when they are totally + * cleaned and invalidated + */ + while (*((volatile unsigned int *)(0xA041277C)) & 0xFF) + ; + + /* Invalidate register 9 D and I lockdown */ + *((volatile unsigned int *)(0xA0412900)) = 0xFF; + *((volatile unsigned int *)(0xA0412904)) = 0xFF; +} + #ifdef CONFIG_ARCH_CPU_INIT /* * SOC specific cpu init -- 1.7.5.4