From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 04/10] drm/i915: add RPS configuration for Haswell Date: Wed, 04 Jul 2012 22:34:20 +0100 Message-ID: <1341437721_170803@CP5-2952> References: <1341240671-5843-1-git-send-email-eugeni.dodonov@intel.com> <1341240671-5843-5-git-send-email-eugeni.dodonov@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from fireflyinternet.com (smtp.fireflyinternet.com [109.228.6.236]) by gabe.freedesktop.org (Postfix) with ESMTP id 4A394A0C21 for ; Wed, 4 Jul 2012 14:35:31 -0700 (PDT) In-Reply-To: <1341240671-5843-5-git-send-email-eugeni.dodonov@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Eugeni Dodonov List-Id: intel-gfx@lists.freedesktop.org On Mon, 2 Jul 2012 11:51:05 -0300, Eugeni Dodonov wrote: > I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); > I915_WRITE(GEN6_RP_CONTROL, > GEN6_RP_MEDIA_TURBO | > @@ -2444,7 +2457,7 @@ static void gen6_enable_rps(struct drm_device *dev) > GEN6_RP_MEDIA_IS_GFX | > GEN6_RP_ENABLE | > GEN6_RP_UP_BUSY_AVG | > - GEN6_RP_DOWN_IDLE_CONT); > + (IS_HASWELL(dev)) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT); And with one small typo does everything break... -Chris -- Chris Wilson, Intel Open Source Technology Centre