Re: [PATCH 3/3] drm/i915: Export ability of changing cache levels to userspace

[Chris Wilson <chris@chris-wilson.co.uk>]

On Tue, 10 Jul 2012 10:54:02 +0200, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Mon, Jul 09, 2012 at 12:34:39PM +0100, Chris Wilson wrote:
> >  enum i915_cache_level {
> > -	I915_CACHE_NONE,
> > -	I915_CACHE_LLC,
> > -	I915_CACHE_LLC_MLC, /* gen6+ */
> > +	I915_CACHE_NONE = I915_CACHE_LEVEL_NONE,
> > +	I915_CACHE_LLC = I915_CACHE_LEVEL_LLC,
> > +	I915_CACHE_LLC_MLC = I915_CACHE_LEVEL_LLC_MLC, /* gen6+ */
> 
> LLC_MLC is a lie, it doesn't exist on gen6. And gen7 has something else
> called l3$ cache, but that seems to be more special-purpose in nature
> (hence I have a feeling it's better if userspace just sets the desired
> caching in the surface state).
> 
> The other thing that's irking me is whether we want different names for
> different kinds of caching or not, i.e. whether we should split out
> pre-gen6 coherent mem from gen6+ coherent stuff. Also, on vlv we don't
> have a llc cache, but we can still support coherent memory like on gen6+
> with llc (it's just a bit slower for gpu-only use, hence not the default).

"Just a bit" will be an understatement judging by the snoopable
architectures upon which it is based. :-p

> I guess I'd bikeshed less if we color this I915_CACHE_LEVEL_CPU_COHERENT
> (and maybe add more specific variants in the future if we need them).

I was half thinking towards extensibility, but we are more likely to
need new ioctls rather than just add to this set of "cache levels".

I am happy with just having two levels in the userspace for this:
uncached, snoopable. They are generic enough to cover the last 7
generations, good enough for the next 3?
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre