All of lore.kernel.org
 help / color / mirror / Atom feed
* Semantics of lv1_pause()
@ 2012-07-10  3:20 Benjamin Herrenschmidt
  2012-07-10 19:36 ` Geoff Levand
  0 siblings, 1 reply; 2+ messages in thread
From: Benjamin Herrenschmidt @ 2012-07-10  3:20 UTC (permalink / raw)
  To: Geoff Levand; +Cc: linuxppc-dev

Hi Geoff !

Do you have access to any kind of documentation regarding the precise
semantics of lv1_pause() ?

I'm fixing various issues with our idle loops, among other things,
because we are soft-disabled when we hit ppc_md.powersave() but not
hard-disabled, there could be an interrupt marked as pending and not
taken yet.

Will that work properly ? I have this understanding that it might
not ... but heh.

Also if I call lv1_pause() with MSR_EE off, will it work ? Will it
return with MSR_EE on like H_CEDE does on pseries ?

Cheers,
Ben.

^ permalink raw reply	[flat|nested] 2+ messages in thread

* Re: Semantics of lv1_pause()
  2012-07-10  3:20 Semantics of lv1_pause() Benjamin Herrenschmidt
@ 2012-07-10 19:36 ` Geoff Levand
  0 siblings, 0 replies; 2+ messages in thread
From: Geoff Levand @ 2012-07-10 19:36 UTC (permalink / raw)
  To: Benjamin Herrenschmidt; +Cc: linuxppc-dev

Hi Ben,

On Tue, 2012-07-10 at 13:20 +1000, Benjamin Herrenschmidt wrote:
> regarding the precise semantics of lv1_pause() ?

Here's what's in PS3's setup.c:

static void ps3_power_save(void)
{
	/*
	 * lv1_pause() puts the PPE thread into inactive state until an
	 * irq on an unmasked plug exists. MSR[EE] has no effect.
	 * flags: 0 = wake on DEC interrupt, 1 = ignore DEC interrupt.
	 */

	lv1_pause(0);
}

Just FYI, setup.c is here:

  http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=blob;f=arch/powerpc/platforms/ps3/setup.c;hb=HEAD#l72

> I'm fixing various issues with our idle loops, among other things,
> because we are soft-disabled when we hit ppc_md.powersave() but not
> hard-disabled, there could be an interrupt marked as pending and not
> taken yet.
> 
> Will that work properly ? I have this understanding that it might
> not ... but heh.

The (virtual) HW thread that called lv1_pause() should become active
when any virq that had irq_chip.irq_unmask() called for it occurs.

I'm not sure what 'become active' means if that virq is setup to be
handled by the 'paused' HW thread.  I guess the behavior depends on
if MSR_EE was set?
 
> Also if I call lv1_pause() with MSR_EE off, will it work ? Will it
> return with MSR_EE on like H_CEDE does on pseries ?

As above, the value of MSR_EE has no effect on activating the HW
thread, and I assume MSR_EE will still be off when lv1_pause() returns.
We can try some experiments if needed.

-Geoff

^ permalink raw reply	[flat|nested] 2+ messages in thread

end of thread, other threads:[~2012-07-10 19:36 UTC | newest]

Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2012-07-10  3:20 Semantics of lv1_pause() Benjamin Herrenschmidt
2012-07-10 19:36 ` Geoff Levand

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.