[PATCH 0/9] Versatile Express updates for 3.6

[PATCH 0/9] Versatile Express updates for 3.6

[Pawel Moll]

Hi All,

This series is a set of updates of Versatile Express code I'd like
to get into 3.6 window. If there are no issues I'll create a v3.5-rc6
based branch and ask Arnd and/or Olof to pull it by the end of this
week.

There's nothing revolutionary here, really. The common clock change
has been posted already over a month ago and lives happily in the
Linaro's kernel tree since.

One note - the "Make plat-versatile clock optional" simply replicates
part of Linus Walleij's "Integrator common clock" patch and can be
dropped if one has this change already pulled in.

Regards

Pawel

Pawel Moll (8):
  ARM: vexpress: Check master site in daughterboard's sysctl operations
  ARM: versatile: Make plat-versatile clock optional
  ARM: vexpress: Initial common clock support
  ARM: vexpress: Add missing SP804 interrupt in motherboard's DTS files
  ARM: vexpress: Add fixed regulator for SMSC
  ARM: vexpress: Convert V2P-CA15 Device Tree to 64 bit addresses
  ARM: vexpress: Add Device Tree for V2P-CA15_CA7 core tile
  ARM: vexpress: Config option for early printk console

Will Deacon (1):
  ARM: vexpress: remove automatic errata workaround selection

 arch/arm/Kconfig                                  |    6 +-
 arch/arm/Kconfig.debug                            |   26 ++
 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi           |   11 +
 arch/arm/boot/dts/vexpress-v2m.dtsi               |   11 +
 arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts       |   36 +--
 arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts        |  188 +++++++++++++
 arch/arm/configs/vexpress_defconfig               |   25 +-
 arch/arm/mach-vexpress/Kconfig                    |   13 -
 arch/arm/mach-vexpress/Makefile.boot              |    3 +-
 arch/arm/mach-vexpress/ct-ca9x4.c                 |   64 ++---
 arch/arm/mach-vexpress/include/mach/clkdev.h      |   15 --
 arch/arm/mach-vexpress/include/mach/debug-macro.S |   44 ++++
 arch/arm/mach-vexpress/include/mach/motherboard.h |   28 +-
 arch/arm/mach-vexpress/include/mach/uncompress.h  |   14 +
 arch/arm/mach-vexpress/v2m.c                      |  292 ++++++++++-----------
 arch/arm/plat-versatile/Kconfig                   |    3 +
 arch/arm/plat-versatile/Makefile                  |    2 +-
 17 files changed, 512 insertions(+), 269 deletions(-)
 create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
 delete mode 100644 arch/arm/mach-vexpress/include/mach/clkdev.h

-- 
1.7.9.5

[PATCH 1/9] ARM: vexpress: remove automatic errata workaround selection

[Pawel Moll]

From: Will Deacon <will.deacon@arm.com>

The vexpress Kconfig setup tries to be clever^Whelpful and selects some
errata workarounds for certain revisions of the Cortex-A9 and PL310,
which may be required depending on the coretile.

Since the mach-vexpress can support A5, A7 and A15 coretiles, let's
defer errata workaround selection to the user and instead propose
recommended workarounds in the defconfig. Note that the use of the
savedefconfig target removed some unrelated, redundant entries from the
file.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
 arch/arm/configs/vexpress_defconfig |   25 +++++++------------------
 arch/arm/mach-vexpress/Kconfig      |   13 -------------
 2 files changed, 7 insertions(+), 31 deletions(-)

diff --git a/arch/arm/configs/vexpress_defconfig b/arch/arm/configs/vexpress_defconfig
index f2de51f..8af0213 100644
--- a/arch/arm/configs/vexpress_defconfig
+++ b/arch/arm/configs/vexpress_defconfig
@@ -8,11 +8,9 @@ CONFIG_CGROUPS=y
 CONFIG_CPUSETS=y
 # CONFIG_UTS_NS is not set
 # CONFIG_IPC_NS is not set
-# CONFIG_USER_NS is not set
 # CONFIG_PID_NS is not set
 # CONFIG_NET_NS is not set
 CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_PROFILING=y
 CONFIG_OPROFILE=y
 CONFIG_MODULES=y
@@ -24,9 +22,14 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_ARCH_VEXPRESS=y
 CONFIG_ARCH_VEXPRESS_CA9X4=y
 # CONFIG_SWP_EMULATE is not set
+CONFIG_ARM_ERRATA_720789=y
+CONFIG_ARM_ERRATA_751472=y
+CONFIG_PL310_ERRATA_753970=y
+CONFIG_ARM_ERRATA_754327=y
+CONFIG_ARM_ERRATA_764369=y
+CONFIG_PL310_ERRATA_769419=y
 CONFIG_SMP=y
 CONFIG_VMSPLIT_2G=y
-CONFIG_HOTPLUG_CPU=y
 CONFIG_AEABI=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
@@ -46,33 +49,26 @@ CONFIG_IP_PNP_BOOTP=y
 # CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_ARM_INTEGRATOR=y
-CONFIG_MISC_DEVICES=y
 # CONFIG_SCSI_PROC_FS is not set
 CONFIG_BLK_DEV_SD=y
 # CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_ATA=y
 # CONFIG_SATA_PMP is not set
 CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
 CONFIG_SMSC911X=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
 # CONFIG_WLAN is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_SERIO_SERPORT is not set
 CONFIG_SERIO_AMBAKMI=y
+CONFIG_LEGACY_PTY_COUNT=16
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-CONFIG_LEGACY_PTY_COUNT=16
 # CONFIG_HW_RANDOM is not set
 # CONFIG_HWMON is not set
 CONFIG_FB=y
@@ -103,7 +99,6 @@ CONFIG_HID_THRUSTMASTER=y
 CONFIG_HID_ZEROPLUS=y
 CONFIG_USB=y
 CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-# CONFIG_USB_DEVICE_CLASS is not set
 CONFIG_USB_MON=y
 CONFIG_USB_ISP1760_HCD=y
 CONFIG_USB_STORAGE=y
@@ -120,9 +115,7 @@ CONFIG_TMPFS=y
 CONFIG_JFFS2_FS=y
 CONFIG_CRAMFS=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_ROOT_NFS=y
-# CONFIG_RPCSEC_GSS_KRB5 is not set
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_MAGIC_SYSRQ=y
@@ -131,10 +124,6 @@ CONFIG_DEBUG_KERNEL=y
 CONFIG_DETECT_HUNG_TASK=y
 # CONFIG_SCHED_DEBUG is not set
 CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_LL=y
 CONFIG_EARLY_PRINTK=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_HW is not set
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index cf8730d..6a165fa7 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -1,20 +1,8 @@
 menu "Versatile Express platform type"
 	depends on ARCH_VEXPRESS
 
-config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
-	bool
-	select ARM_ERRATA_720789
-	select ARM_ERRATA_751472
-	select PL310_ERRATA_753970 if CACHE_PL310
-	help
-	  Provides common dependencies for Versatile Express platforms
-	  based on Cortex-A5 and Cortex-A9 processors. In order to
-	  build a working kernel, you must also enable relevant core
-	  tile support or Flattened Device Tree based support options.
-
 config ARCH_VEXPRESS_CA9X4
 	bool "Versatile Express Cortex-A9x4 tile"
-	select ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
 	select ARM_GIC
 	select CPU_V7
 	select HAVE_SMP
@@ -22,7 +10,6 @@ config ARCH_VEXPRESS_CA9X4
 
 config ARCH_VEXPRESS_DT
 	bool "Device Tree support for Versatile Express platforms"
-	select ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
 	select ARM_GIC
 	select ARM_PATCH_PHYS_VIRT
 	select AUTO_ZRELADDR
-- 
1.7.9.5

[PATCH 2/9] ARM: vexpress: Check master site in daughterboard's sysctl operations

[Pawel Moll]

With recent enough motherboard firmware, core tile can be fitted
in either of the two daughterboard sites. The non-DT tile code for
V2P-CA9 did not check that when configuring DVI output nor setting
CLCD pixel clock.

Fixed now, providing "get master site" API in motherboard's code.

Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
 arch/arm/mach-vexpress/ct-ca9x4.c                 |   15 ++++++++++++---
 arch/arm/mach-vexpress/include/mach/motherboard.h |    9 ++++++---
 arch/arm/mach-vexpress/v2m.c                      |   18 +++++++++++++-----
 3 files changed, 31 insertions(+), 11 deletions(-)

diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index c65cc3b..ab15a55 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -66,8 +66,15 @@ static void __init ct_ca9x4_init_irq(void)
 
 static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
 {
-	v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0);
-	v2m_cfg_write(SYS_CFG_DVIMODE | SYS_CFG_SITE_DB1, 2);
+	u32 site = v2m_get_master_site();
+
+	/*
+	 * Old firmware was using the "site" component of the command
+	 * to control the DVI muxer (while it should be always 0 ie. MB).
+	 * Newer firmware uses the data register. Keep both for compatibility.
+	 */
+	v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE(site), site);
+	v2m_cfg_write(SYS_CFG_DVIMODE | SYS_CFG_SITE(SYS_CFG_SITE_MB), 2);
 }
 
 static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
@@ -112,7 +119,9 @@ static long ct_round(struct clk *clk, unsigned long rate)
 
 static int ct_set(struct clk *clk, unsigned long rate)
 {
-	return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE_DB1 | 1, rate);
+	u32 site = v2m_get_master_site();
+
+	return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE(site) | 1, rate);
 }
 
 static const struct clk_ops osc1_clk_ops = {
diff --git a/arch/arm/mach-vexpress/include/mach/motherboard.h b/arch/arm/mach-vexpress/include/mach/motherboard.h
index 31a9289..f004ec9 100644
--- a/arch/arm/mach-vexpress/include/mach/motherboard.h
+++ b/arch/arm/mach-vexpress/include/mach/motherboard.h
@@ -104,9 +104,10 @@
 #define SYS_CFG_REBOOT		(9 << 20)
 #define SYS_CFG_DVIMODE		(11 << 20)
 #define SYS_CFG_POWER		(12 << 20)
-#define SYS_CFG_SITE_MB		(0 << 16)
-#define SYS_CFG_SITE_DB1	(1 << 16)
-#define SYS_CFG_SITE_DB2	(2 << 16)
+#define SYS_CFG_SITE(n)		((n) << 16)
+#define SYS_CFG_SITE_MB		0
+#define SYS_CFG_SITE_DB1	1
+#define SYS_CFG_SITE_DB2	2
 #define SYS_CFG_STACK(n)	((n) << 12)
 
 #define SYS_CFG_ERR		(1 << 1)
@@ -122,6 +123,8 @@ void v2m_flags_set(u32 data);
 #define SYS_MISC_MASTERSITE	(1 << 14)
 #define SYS_PROCIDx_HBI_MASK	0xfff
 
+int v2m_get_master_site(void);
+
 /*
  * Core tile IDs
  */
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index fde26ad..bb18592 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -147,6 +147,13 @@ void __init v2m_flags_set(u32 data)
 	writel(data, v2m_sysreg_base + V2M_SYS_FLAGSSET);
 }
 
+int v2m_get_master_site(void)
+{
+	u32 misc = readl(v2m_sysreg_base + V2M_SYS_MISC);
+
+	return misc & SYS_MISC_MASTERSITE ? SYS_CFG_SITE_DB2 : SYS_CFG_SITE_DB1;
+}
+
 
 static struct resource v2m_pcie_i2c_resource = {
 	.start	= V2M_SERIAL_BUS_PCI,
@@ -326,7 +333,8 @@ static long v2m_osc_round(struct clk *clk, unsigned long rate)
 
 static int v2m_osc1_set(struct clk *clk, unsigned long rate)
 {
-	return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE_MB | 1, rate);
+	return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE(SYS_CFG_SITE_MB) | 1,
+			rate);
 }
 
 static const struct clk_ops osc1_clk_ops = {
@@ -404,13 +412,13 @@ static void __init v2m_init_early(void)
 
 static void v2m_power_off(void)
 {
-	if (v2m_cfg_write(SYS_CFG_SHUTDOWN | SYS_CFG_SITE_MB, 0))
+	if (v2m_cfg_write(SYS_CFG_SHUTDOWN | SYS_CFG_SITE(SYS_CFG_SITE_MB), 0))
 		printk(KERN_EMERG "Unable to shutdown\n");
 }
 
 static void v2m_restart(char str, const char *cmd)
 {
-	if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0))
+	if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE(SYS_CFG_SITE_MB), 0))
 		printk(KERN_EMERG "Unable to reboot\n");
 }
 
@@ -605,8 +613,8 @@ void __init v2m_dt_init_early(void)
 
 	/* Confirm board type against DT property, if available */
 	if (of_property_read_u32(allnodes, "arm,hbi", &dt_hbi) == 0) {
-		u32 misc = readl(v2m_sysreg_base + V2M_SYS_MISC);
-		u32 id = readl(v2m_sysreg_base + (misc & SYS_MISC_MASTERSITE ?
+		int site = v2m_get_master_site();
+		u32 id = readl(v2m_sysreg_base + (site == SYS_CFG_SITE_DB2 ?
 				V2M_SYS_PROCID1 : V2M_SYS_PROCID0));
 		u32 hbi = id & SYS_PROCIDx_HBI_MASK;
 
-- 
1.7.9.5

[PATCH 3/9] ARM: versatile: Make plat-versatile clock optional

[Pawel Moll]

... in preparation for common clock coming for Integrator
and Versatile Express.

Based on Linus Walleij's "ARM: integrator: convert to common
clock" patch.

Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
 arch/arm/Kconfig                 |    4 ++++
 arch/arm/plat-versatile/Kconfig  |    3 +++
 arch/arm/plat-versatile/Makefile |    2 +-
 3 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a91009c..17beb66 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -260,6 +260,7 @@ config ARCH_INTEGRATOR
 	select ICST
 	select GENERIC_CLOCKEVENTS
 	select PLAT_VERSATILE
+	select PLAT_VERSATILE_CLOCK
 	select PLAT_VERSATILE_FPGA_IRQ
 	select NEED_MACH_IO_H
 	select NEED_MACH_MEMORY_H
@@ -277,6 +278,7 @@ config ARCH_REALVIEW
 	select GENERIC_CLOCKEVENTS
 	select ARCH_WANT_OPTIONAL_GPIOLIB
 	select PLAT_VERSATILE
+	select PLAT_VERSATILE_CLOCK
 	select PLAT_VERSATILE_CLCD
 	select ARM_TIMER_SP804
 	select GPIO_PL061 if GPIOLIB
@@ -295,6 +297,7 @@ config ARCH_VERSATILE
 	select ARCH_WANT_OPTIONAL_GPIOLIB
 	select NEED_MACH_IO_H if PCI
 	select PLAT_VERSATILE
+	select PLAT_VERSATILE_CLOCK
 	select PLAT_VERSATILE_CLCD
 	select PLAT_VERSATILE_FPGA_IRQ
 	select ARM_TIMER_SP804
@@ -314,6 +317,7 @@ config ARCH_VEXPRESS
 	select ICST
 	select NO_IOPORT
 	select PLAT_VERSATILE
+	select PLAT_VERSATILE_CLOCK
 	select PLAT_VERSATILE_CLCD
 	help
 	  This enables support for the ARM Ltd Versatile Express boards.
diff --git a/arch/arm/plat-versatile/Kconfig b/arch/arm/plat-versatile/Kconfig
index 81ee7cc..8d5c10a 100644
--- a/arch/arm/plat-versatile/Kconfig
+++ b/arch/arm/plat-versatile/Kconfig
@@ -1,5 +1,8 @@
 if PLAT_VERSATILE
 
+config PLAT_VERSATILE_CLOCK
+	bool
+
 config PLAT_VERSATILE_CLCD
 	bool
 
diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile
index a5cb194..272769a8 100644
--- a/arch/arm/plat-versatile/Makefile
+++ b/arch/arm/plat-versatile/Makefile
@@ -1,4 +1,4 @@
-obj-y	:= clock.o
+obj-$(CONFIG_PLAT_VERSATILE_CLOCK) += clock.o
 obj-$(CONFIG_PLAT_VERSATILE_CLCD) += clcd.o
 obj-$(CONFIG_PLAT_VERSATILE_FPGA_IRQ) += fpga-irq.o
 obj-$(CONFIG_PLAT_VERSATILE_LEDS) += leds.o
-- 
1.7.9.5

[PATCH 4/9] ARM: vexpress: Initial common clock support

[Pawel Moll]

This patch makes Versatile Express use the common clock framework
instead of the plat-versatile implementation.

It defines clock provider for VE's OSCs (clock generators) and
registers all required fixed and variable clock sources (for both
motherboard and core tile).

This is a simple conversion of the existing state and will be
extended (and migrated to drivers/clk) in the near future.

Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
 arch/arm/Kconfig                                  |    3 +-
 arch/arm/mach-vexpress/ct-ca9x4.c                 |   55 +----
 arch/arm/mach-vexpress/include/mach/clkdev.h      |   15 --
 arch/arm/mach-vexpress/include/mach/motherboard.h |   19 ++
 arch/arm/mach-vexpress/v2m.c                      |  256 +++++++++------------
 5 files changed, 141 insertions(+), 207 deletions(-)
 delete mode 100644 arch/arm/mach-vexpress/include/mach/clkdev.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 17beb66..6374a08 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -310,14 +310,13 @@ config ARCH_VEXPRESS
 	select ARM_AMBA
 	select ARM_TIMER_SP804
 	select CLKDEV_LOOKUP
-	select HAVE_MACH_CLKDEV
+	select COMMON_CLK
 	select GENERIC_CLOCKEVENTS
 	select HAVE_CLK
 	select HAVE_PATA_PLATFORM
 	select ICST
 	select NO_IOPORT
 	select PLAT_VERSATILE
-	select PLAT_VERSATILE_CLOCK
 	select PLAT_VERSATILE_CLCD
 	help
 	  This enables support for the ARM Ltd Versatile Express boards.
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index ab15a55..61c4924 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -112,45 +112,11 @@ static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {
 };
 
 
-static long ct_round(struct clk *clk, unsigned long rate)
-{
-	return rate;
-}
-
-static int ct_set(struct clk *clk, unsigned long rate)
-{
-	u32 site = v2m_get_master_site();
-
-	return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE(site) | 1, rate);
-}
-
-static const struct clk_ops osc1_clk_ops = {
-	.round	= ct_round,
-	.set	= ct_set,
-};
-
-static struct clk osc1_clk = {
-	.ops	= &osc1_clk_ops,
-	.rate	= 24000000,
-};
-
-static struct clk ct_sp804_clk = {
-	.rate	= 1000000,
-};
-
-static struct clk_lookup lookups[] = {
-	{	/* CLCD */
-		.dev_id		= "ct:clcd",
-		.clk		= &osc1_clk,
-	}, {	/* SP804 timers */
-		.dev_id		= "sp804",
-		.con_id		= "ct-timer0",
-		.clk		= &ct_sp804_clk,
-	}, {	/* SP804 timers */
-		.dev_id		= "sp804",
-		.con_id		= "ct-timer1",
-		.clk		= &ct_sp804_clk,
-	},
+static struct v2m_osc ct_osc1 = {
+	.osc = 1,
+	.rate_min = 10000000,
+	.rate_max = 80000000,
+	.rate_default = 23750000,
 };
 
 static struct resource pmu_resources[] = {
@@ -183,14 +149,10 @@ static struct platform_device pmu_device = {
 	.resource	= pmu_resources,
 };
 
-static void __init ct_ca9x4_init_early(void)
-{
-	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-}
-
 static void __init ct_ca9x4_init(void)
 {
 	int i;
+	struct clk *clk;
 
 #ifdef CONFIG_CACHE_L2X0
 	void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K);
@@ -202,6 +164,10 @@ static void __init ct_ca9x4_init(void)
 	l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
 #endif
 
+	ct_osc1.site = v2m_get_master_site();
+	clk = v2m_osc_register("ct:osc1", &ct_osc1);
+	clk_register_clkdev(clk, NULL, "ct:clcd");
+
 	for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
 		amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);
 
@@ -243,7 +209,6 @@ struct ct_desc ct_ca9x4_desc __initdata = {
 	.id		= V2M_CT_ID_CA9,
 	.name		= "CA9x4",
 	.map_io		= ct_ca9x4_map_io,
-	.init_early	= ct_ca9x4_init_early,
 	.init_irq	= ct_ca9x4_init_irq,
 	.init_tile	= ct_ca9x4_init,
 #ifdef CONFIG_SMP
diff --git a/arch/arm/mach-vexpress/include/mach/clkdev.h b/arch/arm/mach-vexpress/include/mach/clkdev.h
deleted file mode 100644
index 3f8307d..0000000
--- a/arch/arm/mach-vexpress/include/mach/clkdev.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef __ASM_MACH_CLKDEV_H
-#define __ASM_MACH_CLKDEV_H
-
-#include <plat/clock.h>
-
-struct clk {
-	const struct clk_ops	*ops;
-	unsigned long		rate;
-	const struct icst_params *params;
-};
-
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do { } while (0)
-
-#endif
diff --git a/arch/arm/mach-vexpress/include/mach/motherboard.h b/arch/arm/mach-vexpress/include/mach/motherboard.h
index f004ec9..1e388c7 100644
--- a/arch/arm/mach-vexpress/include/mach/motherboard.h
+++ b/arch/arm/mach-vexpress/include/mach/motherboard.h
@@ -1,6 +1,8 @@
 #ifndef __MACH_MOTHERBOARD_H
 #define __MACH_MOTHERBOARD_H
 
+#include <linux/clk-provider.h>
+
 /*
  * Physical addresses, offset from V2M_PA_CS0-3
  */
@@ -147,4 +149,21 @@ struct ct_desc {
 
 extern struct ct_desc *ct_desc;
 
+/*
+ * OSC clock provider
+ */
+struct v2m_osc {
+	struct clk_hw hw;
+	u8 site; /* 0 = motherboard, 1 = site 1, 2 = site 2 */
+	u8 stack; /* board stack position */
+	u16 osc;
+	unsigned long rate_min;
+	unsigned long rate_max;
+	unsigned long rate_default;
+};
+
+#define to_v2m_osc(osc) container_of(osc, struct v2m_osc, hw)
+
+struct clk *v2m_osc_register(const char *name, struct v2m_osc *osc);
+
 #endif
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index bb18592..8a64402 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -16,6 +16,7 @@
 #include <linux/spinlock.h>
 #include <linux/usb/isp1760.h>
 #include <linux/clkdev.h>
+#include <linux/clk-provider.h>
 #include <linux/mtd/physmap.h>
 
 #include <asm/arch_timer.h>
@@ -81,16 +82,6 @@ static void __init v2m_sp804_init(void __iomem *base, unsigned int irq)
 	sp804_clockevents_init(base + TIMER_1_BASE, irq, "v2m-timer0");
 }
 
-static void __init v2m_timer_init(void)
-{
-	v2m_sysctl_init(ioremap(V2M_SYSCTL, SZ_4K));
-	v2m_sp804_init(ioremap(V2M_TIMER01, SZ_4K), IRQ_V2M_TIMER0);
-}
-
-static struct sys_timer v2m_timer = {
-	.init	= v2m_timer_init,
-};
-
 
 static DEFINE_SPINLOCK(v2m_cfg_lock);
 
@@ -326,99 +317,145 @@ static struct amba_device *v2m_amba_devs[] __initdata = {
 };
 
 
-static long v2m_osc_round(struct clk *clk, unsigned long rate)
+static unsigned long v2m_osc_recalc_rate(struct clk_hw *hw,
+		unsigned long parent_rate)
+{
+	struct v2m_osc *osc = to_v2m_osc(hw);
+
+	return !parent_rate ? osc->rate_default : parent_rate;
+}
+
+static long v2m_osc_round_rate(struct clk_hw *hw, unsigned long rate,
+		unsigned long *parent_rate)
 {
+	struct v2m_osc *osc = to_v2m_osc(hw);
+
+	if (WARN_ON(rate < osc->rate_min))
+		rate = osc->rate_min;
+
+	if (WARN_ON(rate > osc->rate_max))
+		rate = osc->rate_max;
+
 	return rate;
 }
 
-static int v2m_osc1_set(struct clk *clk, unsigned long rate)
+static int v2m_osc_set_rate(struct clk_hw *hw, unsigned long rate,
+		unsigned long parent_rate)
 {
-	return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE(SYS_CFG_SITE_MB) | 1,
-			rate);
+	struct v2m_osc *osc = to_v2m_osc(hw);
+
+	v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE(osc->site) |
+			SYS_CFG_STACK(osc->stack) | osc->osc, rate);
+
+	return 0;
 }
 
-static const struct clk_ops osc1_clk_ops = {
-	.round	= v2m_osc_round,
-	.set	= v2m_osc1_set,
+static struct clk_ops v2m_osc_ops = {
+	.recalc_rate = v2m_osc_recalc_rate,
+	.round_rate = v2m_osc_round_rate,
+	.set_rate = v2m_osc_set_rate,
 };
 
-static struct clk osc1_clk = {
-	.ops	= &osc1_clk_ops,
-	.rate	= 24000000,
+struct clk * __init v2m_osc_register(const char *name, struct v2m_osc *osc)
+{
+	struct clk_init_data init;
+
+	WARN_ON(osc->site > 2);
+	WARN_ON(osc->stack > 15);
+	WARN_ON(osc->osc > 4095);
+
+	init.name = name;
+	init.ops = &v2m_osc_ops;
+	init.flags = CLK_IS_ROOT;
+	init.num_parents = 0;
+
+	osc->hw.init = &init;
+
+	return clk_register(NULL, &osc->hw);
+}
+
+static struct v2m_osc v2m_mb_osc1 = {
+	.site = SYS_CFG_SITE_MB,
+	.osc = 1,
+	.rate_min = 23750000,
+	.rate_max = 63500000,
+	.rate_default = 23750000,
 };
 
-static struct clk osc2_clk = {
-	.rate	= 24000000,
+static const char *v2m_ref_clk_periphs[] __initconst = {
+	"mb:wdt",   "1000f000.wdt",  "1c0f0000.wdt",	/* SP805 WDT */
 };
 
-static struct clk v2m_sp804_clk = {
-	.rate	= 1000000,
+static const char *v2m_osc1_periphs[] __initconst = {
+	"mb:clcd",  "1001f000.clcd", "1c1f0000.clcd",	/* PL111 CLCD */
 };
 
-static struct clk v2m_ref_clk = {
-	.rate   = 32768,
+static const char *v2m_osc2_periphs[] __initconst = {
+	"mb:mmci",  "10005000.mmci", "1c050000.mmci",	/* PL180 MMCI */
+	"mb:kmi0",  "10006000.kmi",  "1c060000.kmi",	/* PL050 KMI0 */
+	"mb:kmi1",  "10007000.kmi",  "1c070000.kmi",	/* PL050 KMI1 */
+	"mb:uart0", "10009000.uart", "1c090000.uart",	/* PL011 UART0 */
+	"mb:uart1", "1000a000.uart", "1c0a0000.uart",	/* PL011 UART1 */
+	"mb:uart2", "1000b000.uart", "1c0b0000.uart",	/* PL011 UART2 */
+	"mb:uart3", "1000c000.uart", "1c0c0000.uart",	/* PL011 UART3 */
 };
 
-static struct clk dummy_apb_pclk;
-
-static struct clk_lookup v2m_lookups[] = {
-	{	/* AMBA bus clock */
-		.con_id		= "apb_pclk",
-		.clk		= &dummy_apb_pclk,
-	}, {	/* UART0 */
-		.dev_id		= "mb:uart0",
-		.clk		= &osc2_clk,
-	}, {	/* UART1 */
-		.dev_id		= "mb:uart1",
-		.clk		= &osc2_clk,
-	}, {	/* UART2 */
-		.dev_id		= "mb:uart2",
-		.clk		= &osc2_clk,
-	}, {	/* UART3 */
-		.dev_id		= "mb:uart3",
-		.clk		= &osc2_clk,
-	}, {	/* KMI0 */
-		.dev_id		= "mb:kmi0",
-		.clk		= &osc2_clk,
-	}, {	/* KMI1 */
-		.dev_id		= "mb:kmi1",
-		.clk		= &osc2_clk,
-	}, {	/* MMC0 */
-		.dev_id		= "mb:mmci",
-		.clk		= &osc2_clk,
-	}, {	/* CLCD */
-		.dev_id		= "mb:clcd",
-		.clk		= &osc1_clk,
-	}, {	/* SP805 WDT */
-		.dev_id		= "mb:wdt",
-		.clk		= &v2m_ref_clk,
-	}, {	/* SP804 timers */
-		.dev_id		= "sp804",
-		.con_id		= "v2m-timer0",
-		.clk		= &v2m_sp804_clk,
-	}, {	/* SP804 timers */
-		.dev_id		= "sp804",
-		.con_id		= "v2m-timer1",
-		.clk		= &v2m_sp804_clk,
-	},
+static void __init v2m_clk_init(void)
+{
+	struct clk *clk;
+	int i;
+
+	clk = clk_register_fixed_rate(NULL, "dummy_apb_pclk", NULL,
+			CLK_IS_ROOT, 0);
+	WARN_ON(clk_register_clkdev(clk, "apb_pclk", NULL));
+
+	clk = clk_register_fixed_rate(NULL, "mb:ref_clk", NULL,
+			CLK_IS_ROOT, 32768);
+	for (i = 0; i < ARRAY_SIZE(v2m_ref_clk_periphs); i++)
+		WARN_ON(clk_register_clkdev(clk, NULL, v2m_ref_clk_periphs[i]));
+
+	clk = clk_register_fixed_rate(NULL, "mb:sp804_clk", NULL,
+			CLK_IS_ROOT, 1000000);
+	WARN_ON(clk_register_clkdev(clk, "v2m-timer0", "sp804"));
+	WARN_ON(clk_register_clkdev(clk, "v2m-timer1", "sp804"));
+
+	clk = v2m_osc_register("mb:osc1", &v2m_mb_osc1);
+	for (i = 0; i < ARRAY_SIZE(v2m_osc1_periphs); i++)
+		WARN_ON(clk_register_clkdev(clk, NULL, v2m_osc1_periphs[i]));
+
+	clk = clk_register_fixed_rate(NULL, "mb:osc2", NULL,
+			CLK_IS_ROOT, 24000000);
+	for (i = 0; i < ARRAY_SIZE(v2m_osc2_periphs); i++)
+		WARN_ON(clk_register_clkdev(clk, NULL, v2m_osc2_periphs[i]));
+}
+
+static void __init v2m_timer_init(void)
+{
+	v2m_sysctl_init(ioremap(V2M_SYSCTL, SZ_4K));
+	v2m_clk_init();
+	v2m_sp804_init(ioremap(V2M_TIMER01, SZ_4K), IRQ_V2M_TIMER0);
+}
+
+static struct sys_timer v2m_timer = {
+	.init	= v2m_timer_init,
 };
 
 static void __init v2m_init_early(void)
 {
-	ct_desc->init_early();
-	clkdev_add_table(v2m_lookups, ARRAY_SIZE(v2m_lookups));
+	if (ct_desc->init_early)
+		ct_desc->init_early();
 	versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
 }
 
 static void v2m_power_off(void)
 {
-	if (v2m_cfg_write(SYS_CFG_SHUTDOWN | SYS_CFG_SITE(SYS_CFG_SITE_MB), 0))
+	if (v2m_cfg_write(SYS_CFG_SHUTDOWN | SYS_CFG_SITE_MB, 0))
 		printk(KERN_EMERG "Unable to shutdown\n");
 }
 
 static void v2m_restart(char str, const char *cmd)
 {
-	if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE(SYS_CFG_SITE_MB), 0))
+	if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0))
 		printk(KERN_EMERG "Unable to reboot\n");
 }
 
@@ -530,77 +567,6 @@ void __init v2m_dt_map_io(void)
 #endif
 }
 
-static struct clk_lookup v2m_dt_lookups[] = {
-	{	/* AMBA bus clock */
-		.con_id		= "apb_pclk",
-		.clk		= &dummy_apb_pclk,
-	}, {	/* SP804 timers */
-		.dev_id		= "sp804",
-		.con_id		= "v2m-timer0",
-		.clk		= &v2m_sp804_clk,
-	}, {	/* SP804 timers */
-		.dev_id		= "sp804",
-		.con_id		= "v2m-timer1",
-		.clk		= &v2m_sp804_clk,
-	}, {	/* PL180 MMCI */
-		.dev_id		= "mb:mmci", /* 10005000.mmci */
-		.clk		= &osc2_clk,
-	}, {	/* PL050 KMI0 */
-		.dev_id		= "10006000.kmi",
-		.clk		= &osc2_clk,
-	}, {	/* PL050 KMI1 */
-		.dev_id		= "10007000.kmi",
-		.clk		= &osc2_clk,
-	}, {	/* PL011 UART0 */
-		.dev_id		= "10009000.uart",
-		.clk		= &osc2_clk,
-	}, {	/* PL011 UART1 */
-		.dev_id		= "1000a000.uart",
-		.clk		= &osc2_clk,
-	}, {	/* PL011 UART2 */
-		.dev_id		= "1000b000.uart",
-		.clk		= &osc2_clk,
-	}, {	/* PL011 UART3 */
-		.dev_id		= "1000c000.uart",
-		.clk		= &osc2_clk,
-	}, {	/* SP805 WDT */
-		.dev_id		= "1000f000.wdt",
-		.clk		= &v2m_ref_clk,
-	}, {	/* PL111 CLCD */
-		.dev_id		= "1001f000.clcd",
-		.clk		= &osc1_clk,
-	},
-	/* RS1 memory map */
-	{	/* PL180 MMCI */
-		.dev_id		= "mb:mmci", /* 1c050000.mmci */
-		.clk		= &osc2_clk,
-	}, {	/* PL050 KMI0 */
-		.dev_id		= "1c060000.kmi",
-		.clk		= &osc2_clk,
-	}, {	/* PL050 KMI1 */
-		.dev_id		= "1c070000.kmi",
-		.clk		= &osc2_clk,
-	}, {	/* PL011 UART0 */
-		.dev_id		= "1c090000.uart",
-		.clk		= &osc2_clk,
-	}, {	/* PL011 UART1 */
-		.dev_id		= "1c0a0000.uart",
-		.clk		= &osc2_clk,
-	}, {	/* PL011 UART2 */
-		.dev_id		= "1c0b0000.uart",
-		.clk		= &osc2_clk,
-	}, {	/* PL011 UART3 */
-		.dev_id		= "1c0c0000.uart",
-		.clk		= &osc2_clk,
-	}, {	/* SP805 WDT */
-		.dev_id		= "1c0f0000.wdt",
-		.clk		= &v2m_ref_clk,
-	}, {	/* PL111 CLCD */
-		.dev_id		= "1c1f0000.clcd",
-		.clk		= &osc1_clk,
-	},
-};
-
 void __init v2m_dt_init_early(void)
 {
 	struct device_node *node;
@@ -622,8 +588,6 @@ void __init v2m_dt_init_early(void)
 			pr_warning("vexpress: DT HBI (%x) is not matching "
 					"hardware (%x)!\n", dt_hbi, hbi);
 	}
-
-	clkdev_add_table(v2m_dt_lookups, ARRAY_SIZE(v2m_dt_lookups));
 }
 
 static  struct of_device_id vexpress_irq_match[] __initdata = {
@@ -645,6 +609,8 @@ static void __init v2m_dt_timer_init(void)
 	node = of_find_compatible_node(NULL, NULL, "arm,sp810");
 	v2m_sysctl_init(of_iomap(node, 0));
 
+	v2m_clk_init();
+
 	err = of_property_read_string(of_aliases, "arm,v2m_timer", &path);
 	if (WARN_ON(err))
 		return;
-- 
1.7.9.5

[PATCH 5/9] ARM: vexpress: Add missing SP804 interrupt in motherboard's DTS files

[Pawel Moll]

Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi |    1 +
 arch/arm/boot/dts/vexpress-v2m.dtsi     |    1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
index 16076e2..142c72a 100644
--- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
@@ -157,6 +157,7 @@
 			v2m_timer23: timer at 120000 {
 				compatible = "arm,sp804", "arm,primecell";
 				reg = <0x120000 0x1000>;
+				interrupts = <3>;
 			};
 
 			/* DVI I2C bus */
diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi
index a6c9c7c..47ee307 100644
--- a/arch/arm/boot/dts/vexpress-v2m.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m.dtsi
@@ -156,6 +156,7 @@
 			v2m_timer23: timer at 12000 {
 				compatible = "arm,sp804", "arm,primecell";
 				reg = <0x12000 0x1000>;
+				interrupts = <3>;
 			};
 
 			/* DVI I2C bus */
-- 
1.7.9.5

[PATCH 6/9] ARM: vexpress: Add fixed regulator for SMSC

[Pawel Moll]

SMSC driver requires "vdd33a" and "vddvario" regulator supplies now.

Add fixed regulator describing 3V3 power line (in both motherboard's
Device Trees and the non-DT code) and force fixed regulator config
option if regulators framework is enabled.

Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
 arch/arm/Kconfig                        |    1 +
 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi |   10 ++++++++++
 arch/arm/boot/dts/vexpress-v2m.dtsi     |   10 ++++++++++
 arch/arm/mach-vexpress/v2m.c            |   10 ++++++++++
 4 files changed, 31 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6374a08..cb15fca 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -318,6 +318,7 @@ config ARCH_VEXPRESS
 	select NO_IOPORT
 	select PLAT_VERSATILE
 	select PLAT_VERSATILE_CLCD
+	select REGULATOR_FIXED_VOLTAGE if REGULATOR
 	help
 	  This enables support for the ARM Ltd Versatile Express boards.
 
diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
index 142c72a..d8a827b 100644
--- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
@@ -55,6 +55,8 @@
 			reg-io-width = <4>;
 			smsc,irq-active-high;
 			smsc,irq-push-pull;
+			vdd33a-supply = <&v2m_fixed_3v3>;
+			vddvario-supply = <&v2m_fixed_3v3>;
 		};
 
 		usb at 2,03000000 {
@@ -198,5 +200,13 @@
 				interrupts = <14>;
 			};
 		};
+
+		v2m_fixed_3v3: fixedregulator at 0 {
+			compatible = "regulator-fixed";
+			regulator-name = "3V3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi
index 47ee307..dba53fd 100644
--- a/arch/arm/boot/dts/vexpress-v2m.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m.dtsi
@@ -54,6 +54,8 @@
 			reg-io-width = <4>;
 			smsc,irq-active-high;
 			smsc,irq-push-pull;
+			vdd33a-supply = <&v2m_fixed_3v3>;
+			vddvario-supply = <&v2m_fixed_3v3>;
 		};
 
 		usb at 3,03000000 {
@@ -197,5 +199,13 @@
 				interrupts = <14>;
 			};
 		};
+
+		v2m_fixed_3v3: fixedregulator at 0 {
+			compatible = "regulator-fixed";
+			regulator-name = "3V3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
 	};
 };
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 8a64402..bf7832d 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -18,6 +18,8 @@
 #include <linux/clkdev.h>
 #include <linux/clk-provider.h>
 #include <linux/mtd/physmap.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
 
 #include <asm/arch_timer.h>
 #include <asm/mach-types.h>
@@ -199,6 +201,11 @@ static struct platform_device v2m_eth_device = {
 	.dev.platform_data = &v2m_eth_config,
 };
 
+static struct regulator_consumer_supply v2m_eth_supplies[] = {
+	REGULATOR_SUPPLY("vddvario", "smsc911x"),
+	REGULATOR_SUPPLY("vdd33a", "smsc911x"),
+};
+
 static struct resource v2m_usb_resources[] = {
 	{
 		.start	= V2M_ISP1761,
@@ -503,6 +510,9 @@ static void __init v2m_init(void)
 {
 	int i;
 
+	regulator_register_fixed(0, v2m_eth_supplies,
+			ARRAY_SIZE(v2m_eth_supplies));
+
 	platform_device_register(&v2m_pcie_i2c_device);
 	platform_device_register(&v2m_ddc_i2c_device);
 	platform_device_register(&v2m_flash_device);
-- 
1.7.9.5

[PATCH 7/9] ARM: vexpress: Convert V2P-CA15 Device Tree to 64 bit addresses

[Pawel Moll]

... to enable use of LPAE, which extends physical address space
to 40 bits.

Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
 arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts |   36 +++++++++++++--------------
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
index 7e1091d..d12b34c 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
@@ -14,8 +14,8 @@
 	arm,hbi = <0x237>;
 	compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
 	interrupt-parent = <&gic>;
-	#address-cells = <1>;
-	#size-cells = <1>;
+	#address-cells = <2>;
+	#size-cells = <2>;
 
 	chosen { };
 
@@ -47,23 +47,23 @@
 
 	memory at 80000000 {
 		device_type = "memory";
-		reg = <0x80000000 0x40000000>;
+		reg = <0 0x80000000 0 0x40000000>;
 	};
 
 	hdlcd at 2b000000 {
 		compatible = "arm,hdlcd";
-		reg = <0x2b000000 0x1000>;
+		reg = <0 0x2b000000 0 0x1000>;
 		interrupts = <0 85 4>;
 	};
 
 	memory-controller at 2b0a0000 {
 		compatible = "arm,pl341", "arm,primecell";
-		reg = <0x2b0a0000 0x1000>;
+		reg = <0 0x2b0a0000 0 0x1000>;
 	};
 
 	wdt at 2b060000 {
 		compatible = "arm,sp805", "arm,primecell";
-		reg = <0x2b060000 0x1000>;
+		reg = <0 0x2b060000 0 0x1000>;
 		interrupts = <98>;
 	};
 
@@ -72,23 +72,23 @@
 		#interrupt-cells = <3>;
 		#address-cells = <0>;
 		interrupt-controller;
-		reg = <0x2c001000 0x1000>,
-		      <0x2c002000 0x1000>,
-		      <0x2c004000 0x2000>,
-		      <0x2c006000 0x2000>;
+		reg = <0 0x2c001000 0 0x1000>,
+		      <0 0x2c002000 0 0x1000>,
+		      <0 0x2c004000 0 0x2000>,
+		      <0 0x2c006000 0 0x2000>;
 		interrupts = <1 9 0xf04>;
 	};
 
 	memory-controller at 7ffd0000 {
 		compatible = "arm,pl354", "arm,primecell";
-		reg = <0x7ffd0000 0x1000>;
+		reg = <0 0x7ffd0000 0 0x1000>;
 		interrupts = <0 86 4>,
 			     <0 87 4>;
 	};
 
 	dma at 7ffb0000 {
 		compatible = "arm,pl330", "arm,primecell";
-		reg = <0x7ffb0000 0x1000>;
+		reg = <0 0x7ffb0000 0 0x1000>;
 		interrupts = <0 92 4>,
 			     <0 88 4>,
 			     <0 89 4>,
@@ -111,12 +111,12 @@
 	};
 
 	motherboard {
-		ranges = <0 0 0x08000000 0x04000000>,
-			 <1 0 0x14000000 0x04000000>,
-			 <2 0 0x18000000 0x04000000>,
-			 <3 0 0x1c000000 0x04000000>,
-			 <4 0 0x0c000000 0x04000000>,
-			 <5 0 0x10000000 0x04000000>;
+		ranges = <0 0 0 0x08000000 0x04000000>,
+			 <1 0 0 0x14000000 0x04000000>,
+			 <2 0 0 0x18000000 0x04000000>,
+			 <3 0 0 0x1c000000 0x04000000>,
+			 <4 0 0 0x0c000000 0x04000000>,
+			 <5 0 0 0x10000000 0x04000000>;
 
 		interrupt-map-mask = <0 0 63>;
 		interrupt-map = <0 0  0 &gic 0  0 4>,
-- 
1.7.9.5

[PATCH 8/9] ARM: vexpress: Add Device Tree for V2P-CA15_CA7 core tile

[Pawel Moll]

This patch adds Device Tree file for the CoreTile Express
A15x2 A7x3 (V2P-CA15_CA7).

Note that the A7 cpu nodes are commented out, as the
big.LITTLE-relevant patches are not upstreamed yet. Till
this time one can use the board with two A15 cores only,
keeping the A7s in reset by adding the following setting
to the board.txt file in Versatile Express configuration
tree:

SCC: 0x018 0x00001FFF

Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
 arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts |  188 ++++++++++++++++++++++++++++
 arch/arm/mach-vexpress/Makefile.boot       |    3 +-
 2 files changed, 190 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts

diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
new file mode 100644
index 0000000..4890a81
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -0,0 +1,188 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * CoreTile Express A15x2 A7x3
+ * Cortex-A15_A7 MPCore (V2P-CA15_A7)
+ *
+ * HBI-0249A
+ */
+
+/dts-v1/;
+
+/ {
+	model = "V2P-CA15_CA7";
+	arm,hbi = <0x249>;
+	compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	chosen { };
+
+	aliases {
+		serial0 = &v2m_serial0;
+		serial1 = &v2m_serial1;
+		serial2 = &v2m_serial2;
+		serial3 = &v2m_serial3;
+		i2c0 = &v2m_i2c_dvi;
+		i2c1 = &v2m_i2c_pcie;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <0>;
+		};
+
+		cpu1: cpu at 1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <1>;
+		};
+
+/* A7s disabled till big.LITTLE patches are available...
+		cpu2: cpu at 2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x100>;
+		};
+
+		cpu3: cpu at 3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x101>;
+		};
+
+		cpu4: cpu at 4 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x102>;
+		};
+*/
+	};
+
+	memory at 80000000 {
+		device_type = "memory";
+		reg = <0 0x80000000 0 0x40000000>;
+	};
+
+	wdt at 2a490000 {
+		compatible = "arm,sp805", "arm,primecell";
+		reg = <0 0x2a490000 0 0x1000>;
+		interrupts = <98>;
+	};
+
+	hdlcd at 2b000000 {
+		compatible = "arm,hdlcd";
+		reg = <0 0x2b000000 0 0x1000>;
+		interrupts = <0 85 4>;
+	};
+
+	memory-controller at 2b0a0000 {
+		compatible = "arm,pl341", "arm,primecell";
+		reg = <0 0x2b0a0000 0 0x1000>;
+	};
+
+	gic: interrupt-controller at 2c001000 {
+		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+		#interrupt-cells = <3>;
+		#address-cells = <0>;
+		interrupt-controller;
+		reg = <0 0x2c001000 0 0x1000>,
+		      <0 0x2c002000 0 0x1000>,
+		      <0 0x2c004000 0 0x2000>,
+		      <0 0x2c006000 0 0x2000>;
+		interrupts = <1 9 0xf04>;
+	};
+
+	memory-controller at 7ffd0000 {
+		compatible = "arm,pl354", "arm,primecell";
+		reg = <0 0x7ffd0000 0 0x1000>;
+		interrupts = <0 86 4>,
+			     <0 87 4>;
+	};
+
+	dma at 7ff00000 {
+		compatible = "arm,pl330", "arm,primecell";
+		reg = <0 0x7ff00000 0 0x1000>;
+		interrupts = <0 92 4>,
+			     <0 88 4>,
+			     <0 89 4>,
+			     <0 90 4>,
+			     <0 91 4>;
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts = <1 13 0xf08>,
+			     <1 14 0xf08>,
+			     <1 11 0xf08>,
+			     <1 10 0xf08>;
+	};
+
+	pmu {
+		compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
+		interrupts = <0 68 4>,
+			     <0 69 4>;
+	};
+
+	motherboard {
+		ranges = <0 0 0 0x08000000 0x04000000>,
+			 <1 0 0 0x14000000 0x04000000>,
+			 <2 0 0 0x18000000 0x04000000>,
+			 <3 0 0 0x1c000000 0x04000000>,
+			 <4 0 0 0x0c000000 0x04000000>,
+			 <5 0 0 0x10000000 0x04000000>;
+
+		interrupt-map-mask = <0 0 63>;
+		interrupt-map = <0 0  0 &gic 0  0 4>,
+				<0 0  1 &gic 0  1 4>,
+				<0 0  2 &gic 0  2 4>,
+				<0 0  3 &gic 0  3 4>,
+				<0 0  4 &gic 0  4 4>,
+				<0 0  5 &gic 0  5 4>,
+				<0 0  6 &gic 0  6 4>,
+				<0 0  7 &gic 0  7 4>,
+				<0 0  8 &gic 0  8 4>,
+				<0 0  9 &gic 0  9 4>,
+				<0 0 10 &gic 0 10 4>,
+				<0 0 11 &gic 0 11 4>,
+				<0 0 12 &gic 0 12 4>,
+				<0 0 13 &gic 0 13 4>,
+				<0 0 14 &gic 0 14 4>,
+				<0 0 15 &gic 0 15 4>,
+				<0 0 16 &gic 0 16 4>,
+				<0 0 17 &gic 0 17 4>,
+				<0 0 18 &gic 0 18 4>,
+				<0 0 19 &gic 0 19 4>,
+				<0 0 20 &gic 0 20 4>,
+				<0 0 21 &gic 0 21 4>,
+				<0 0 22 &gic 0 22 4>,
+				<0 0 23 &gic 0 23 4>,
+				<0 0 24 &gic 0 24 4>,
+				<0 0 25 &gic 0 25 4>,
+				<0 0 26 &gic 0 26 4>,
+				<0 0 27 &gic 0 27 4>,
+				<0 0 28 &gic 0 28 4>,
+				<0 0 29 &gic 0 29 4>,
+				<0 0 30 &gic 0 30 4>,
+				<0 0 31 &gic 0 31 4>,
+				<0 0 32 &gic 0 32 4>,
+				<0 0 33 &gic 0 33 4>,
+				<0 0 34 &gic 0 34 4>,
+				<0 0 35 &gic 0 35 4>,
+				<0 0 36 &gic 0 36 4>,
+				<0 0 37 &gic 0 37 4>,
+				<0 0 38 &gic 0 38 4>,
+				<0 0 39 &gic 0 39 4>,
+				<0 0 40 &gic 0 40 4>,
+				<0 0 41 &gic 0 41 4>,
+				<0 0 42 &gic 0 42 4>;
+	};
+};
+
+/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/mach-vexpress/Makefile.boot b/arch/arm/mach-vexpress/Makefile.boot
index 909f85e..318d308 100644
--- a/arch/arm/mach-vexpress/Makefile.boot
+++ b/arch/arm/mach-vexpress/Makefile.boot
@@ -6,4 +6,5 @@ initrd_phys-y	:= 0x60800000
 
 dtb-$(CONFIG_ARCH_VEXPRESS_DT)	+= vexpress-v2p-ca5s.dtb \
 				   vexpress-v2p-ca9.dtb \
-				   vexpress-v2p-ca15-tc1.dtb
+				   vexpress-v2p-ca15-tc1.dtb \
+				   vexpress-v2p-ca15_a7.dtb
-- 
1.7.9.5

[PATCH 9/9] ARM: vexpress: Config option for early printk console

[Pawel Moll]

Versatile Express platform can be used in different configuartion,
the console UART used by early printk may be located at different
addresses in the address space.

This patch makes it possible to select base address of a PL011 UART
to be used as a console output in the kernel configuration. The
default behaviour is still the heuristic detecting memory map
on Cortex-A core tiles.

The zImage decompressor will use the same configuration values
or print out nothing if DEBUG_LL is not enabled.

Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
 arch/arm/Kconfig.debug                            |   26 ++++++++++++
 arch/arm/mach-vexpress/include/mach/debug-macro.S |   44 +++++++++++++++++++++
 arch/arm/mach-vexpress/include/mach/uncompress.h  |   14 +++++++
 3 files changed, 84 insertions(+)

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 01a1341..12eee87 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -310,6 +310,32 @@ choice
 		  The uncompressor code port configuration is now handled
 		  by CONFIG_S3C_LOWLEVEL_UART_PORT.
 
+	config DEBUG_VEXPRESS_UART0_DETECT
+		bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
+		depends on ARCH_VEXPRESS
+		help
+		  This option enables simple heuristic which tries to determine
+		  motherboard's memory map variant (original or RS1) and then
+		  choose relevant UART0 base address.
+
+		  Note that this will only work with standard A-class core tiles,
+		  and may fail with non-standard SMM or custom software model.
+
+	config DEBUG_VEXPRESS_UART0_CA9
+		bool "Use PL011 UART0 at 0x10009000 (V2P-CA9 core tile)"
+		depends on ARCH_VEXPRESS
+		help
+		  This option selects UART0 at 0x10009000. Except for custom models,
+		  this applies only to V2P-CA9 tile.
+
+	config DEBUG_VEXPRESS_UART0_RS1
+		bool "Use PL011 UART0 at 0x1c090000 (RS1 complaint tiles)"
+		depends on ARCH_VEXPRESS
+		help
+		  This option selects UART0 at 0x1c090000. This applies to most
+		  of the tiles using RS1 memory map, including all new A-class
+		  core tiles, FPGA-based SMMs and software models.
+
 	config DEBUG_LL_UART_NONE
 		bool "No low-level debugging UART"
 		help
diff --git a/arch/arm/mach-vexpress/include/mach/debug-macro.S b/arch/arm/mach-vexpress/include/mach/debug-macro.S
index fa82247..1980239 100644
--- a/arch/arm/mach-vexpress/include/mach/debug-macro.S
+++ b/arch/arm/mach-vexpress/include/mach/debug-macro.S
@@ -18,6 +18,8 @@
 
 #define DEBUG_LL_VIRT_BASE		0xf8000000
 
+#if defined(CONFIG_DEBUG_VEXPRESS_UART0_DETECT)
+
 		.macro	addruart,rp,rv,tmp
 
 		@ Make an educated guess regarding the memory map:
@@ -41,3 +43,45 @@
 		.endm
 
 #include <asm/hardware/debug-pl01x.S>
+
+#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_CA9)
+
+		.macro	addruart,rp,rv,tmp
+		mov	\rp, #DEBUG_LL_UART_OFFSET
+		orr	\rv, \rp, #DEBUG_LL_VIRT_BASE
+		orr	\rp, \rp, #DEBUG_LL_PHYS_BASE
+		.endm
+
+#include <asm/hardware/debug-pl01x.S>
+
+#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_RS1)
+
+		.macro	addruart,rp,rv,tmp
+		mov	\rp, #DEBUG_LL_UART_OFFSET_RS1
+		orr	\rv, \rp, #DEBUG_LL_VIRT_BASE
+		orr	\rp, \rp, #DEBUG_LL_PHYS_BASE_RS1
+		.endm
+
+#include <asm/hardware/debug-pl01x.S>
+
+#else /* CONFIG_DEBUG_LL_UART_NONE */
+
+		.macro	addruart, rp, rv, tmp
+		/*
+		 * Have to provide reasonable dummy values,
+		 * otherwise code in head.S crashes badly...
+		 */
+		mov	\rp, #0
+		mov	\rv, #0
+		.endm
+
+		.macro	senduart,rd,rx
+		.endm
+
+		.macro	waituart,rd,rx
+		.endm
+
+		.macro	busyuart,rd,rx
+		.endm
+
+#endif
diff --git a/arch/arm/mach-vexpress/include/mach/uncompress.h b/arch/arm/mach-vexpress/include/mach/uncompress.h
index 7dab559..1e472eb 100644
--- a/arch/arm/mach-vexpress/include/mach/uncompress.h
+++ b/arch/arm/mach-vexpress/include/mach/uncompress.h
@@ -27,6 +27,7 @@
 
 static unsigned long get_uart_base(void)
 {
+#if defined(CONFIG_DEBUG_VEXPRESS_UART0_DETECT)
 	unsigned long mpcore_periph;
 
 	/*
@@ -42,6 +43,13 @@ static unsigned long get_uart_base(void)
 		return UART_BASE;
 	else
 		return UART_BASE_RS1;
+#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_CA9)
+	return UART_BASE;
+#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_RS1)
+	return UART_BASE_RS1;
+#else
+	return 0;
+#endif
 }
 
 /*
@@ -51,6 +59,9 @@ static inline void putc(int c)
 {
 	unsigned long base = get_uart_base();
 
+	if (!base)
+		return;
+
 	while (AMBA_UART_FR(base) & (1 << 5))
 		barrier();
 
@@ -61,6 +72,9 @@ static inline void flush(void)
 {
 	unsigned long base = get_uart_base();
 
+	if (!base)
+		return;
+
 	while (AMBA_UART_FR(base) & (1 << 3))
 		barrier();
 }
-- 
1.7.9.5

[PATCH 9/9] ARM: vexpress: Config option for early printk console

[Will Deacon]

Hi Pawel,

On Wed, Jul 11, 2012 at 02:36:31PM +0100, Pawel Moll wrote:
> +#else /* CONFIG_DEBUG_LL_UART_NONE */
> +
> +		.macro	addruart, rp, rv, tmp
> +		/*
> +		 * Have to provide reasonable dummy values,
> +		 * otherwise code in head.S crashes badly...
> +		 */
> +		mov	\rp, #0
> +		mov	\rv, #0
> +		.endm

Eek, this means we take out an I/O section mapping at zero, doesn't it?
Is that really a good idea? It scares me because (a) it's below PAGE_OFFSET
and (b) we don't know consistently what's at physical address 0.

Perhaps we could change head.S to avoid the mapping if addruart returns a
NULL virtual address?

Will

[PATCH 9/9] ARM: vexpress: Config option for early printk console

[Pawel Moll]

On Wed, 2012-07-11 at 15:09 +0100, Will Deacon wrote:
> > +#else /* CONFIG_DEBUG_LL_UART_NONE */
> > +
> > +		.macro	addruart, rp, rv, tmp
> > +		/*
> > +		 * Have to provide reasonable dummy values,
> > +		 * otherwise code in head.S crashes badly...
> > +		 */
> > +		mov	\rp, #0
> > +		mov	\rv, #0
> > +		.endm
> 
> Eek, this means we take out an I/O section mapping at zero, doesn't it?
> Is that really a good idea? It scares me because (a) it's below PAGE_OFFSET
> and (b) we don't know consistently what's at physical address 0.
> 
> Perhaps we could change head.S to avoid the mapping if addruart returns a
> NULL virtual address?

Sure (care to prepare a patch? ;-), but this will have to go through
Russell not arm-soc, so it won't be a part of this update. And I'll
remove the comment...

Cheers!

Pawe?

[PATCH 9/9] ARM: vexpress: Config option for early printk console

[Jonathan Austin]

Hi Pawel,

On 11/07/12 14:36, Pawel Moll wrote:
> diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
> index 01a1341..12eee87 100644
> --- a/arch/arm/Kconfig.debug
> +++ b/arch/arm/Kconfig.debug
> @@ -310,6 +310,32 @@ choice
>  		  The uncompressor code port configuration is now handled
>  		  by CONFIG_S3C_LOWLEVEL_UART_PORT.
>  
> +	config DEBUG_VEXPRESS_UART0_DETECT
> +		bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
> +		depends on ARCH_VEXPRESS
> +		help
> +		  This option enables simple heuristic which tries to determine
> +		  motherboard's memory map variant (original or RS1) and then
> +		  choose relevant UART0 base address.
> +
> +		  Note that this will only work with standard A-class core tiles,
> +		  and may fail with non-standard SMM or custom software model.
> +

Is it possible to make this depend on something like CPU_CP15_MMU,
instead of ARCH_VEXPRESS? Seems like a reasonable way to ensure that
this isn't used on some of the core tiles that don't have the required
cp15 registers to read the Configuration Base Address Register.

Jonny

[PATCH 9/9] ARM: vexpress: Config option for early printk console

[Pawel Moll]

On Wed, 2012-07-11 at 15:16 +0100, Pawel Moll wrote:
> On Wed, 2012-07-11 at 15:09 +0100, Will Deacon wrote:
> > > +#else /* CONFIG_DEBUG_LL_UART_NONE */
> > > +
> > > +		.macro	addruart, rp, rv, tmp
> > > +		/*
> > > +		 * Have to provide reasonable dummy values,
> > > +		 * otherwise code in head.S crashes badly...
> > > +		 */
> > > +		mov	\rp, #0
> > > +		mov	\rv, #0
> > > +		.endm
> > 
> > Eek, this means we take out an I/O section mapping at zero, doesn't it?
> > Is that really a good idea? It scares me because (a) it's below PAGE_OFFSET
> > and (b) we don't know consistently what's at physical address 0.
> > 
> > Perhaps we could change head.S to avoid the mapping if addruart returns a
> > NULL virtual address?
> 
> Sure (care to prepare a patch? ;-), but this will have to go through
> Russell not arm-soc, so it won't be a part of this update. And I'll
> remove the comment...

... and use DEBUG_LL_VIRT_BASE as the \rv for now, before the change in
head.S happen. Physical 0 on VE is always flash, so it's not a problem.

Pawel

[PATCH 9/9] ARM: vexpress: Config option for early printk console

[Pawel Moll]

On Wed, 2012-07-11 at 15:23 +0100, Jonathan Austin wrote:
> Hi Pawel,
> 
> On 11/07/12 14:36, Pawel Moll wrote:
> > diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
> > index 01a1341..12eee87 100644
> > --- a/arch/arm/Kconfig.debug
> > +++ b/arch/arm/Kconfig.debug
> > @@ -310,6 +310,32 @@ choice
> >  		  The uncompressor code port configuration is now handled
> >  		  by CONFIG_S3C_LOWLEVEL_UART_PORT.
> >  
> > +	config DEBUG_VEXPRESS_UART0_DETECT
> > +		bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
> > +		depends on ARCH_VEXPRESS
> > +		help
> > +		  This option enables simple heuristic which tries to determine
> > +		  motherboard's memory map variant (original or RS1) and then
> > +		  choose relevant UART0 base address.
> > +
> > +		  Note that this will only work with standard A-class core tiles,
> > +		  and may fail with non-standard SMM or custom software model.
> > +
> 
> Is it possible to make this depend on something like CPU_CP15_MMU,
> instead of ARCH_VEXPRESS? Seems like a reasonable way to ensure that
> this isn't used on some of the core tiles that don't have the required
> cp15 registers to read the Configuration Base Address Register.

Yes, sure, I forgot about this! Sorry, will post v2 in a second.

Pawel

[PATCH 1/9] ARM: vexpress: remove automatic errata workaround selection

[Rob Herring]

On 07/11/2012 08:36 AM, Pawel Moll wrote:
> From: Will Deacon <will.deacon@arm.com>
> 
> The vexpress Kconfig setup tries to be clever^Whelpful and selects some
> errata workarounds for certain revisions of the Cortex-A9 and PL310,
> which may be required depending on the coretile.
> 
> Since the mach-vexpress can support A5, A7 and A15 coretiles, let's
> defer errata workaround selection to the user and instead propose
> recommended workarounds in the defconfig. Note that the use of the
> savedefconfig target removed some unrelated, redundant entries from the
> file.

Most workarounds are runtime conditioned or don't have significant
impact, so why not leave them enabled? For a single kernel image, we're
going to have to basically turn on every errata work-around. Perhaps we
should only have config options if they are not runtime enabled and have
significant performance impact. I think having the settings in the
defconfig is error prone, not mention if threats from Linus to remove
all defconfigs actually happened it would be lost. In general, I don't
think end users have enough information to determine what needs to be
turned on. You need the errata list as well which is not public. Some of
the errata help text says "rXpY and all later revisions" which changes
when a new core revision comes out.

Rob

> 
> Signed-off-by: Will Deacon <will.deacon@arm.com>
> Signed-off-by: Pawel Moll <pawel.moll@arm.com>
> ---
>  arch/arm/configs/vexpress_defconfig |   25 +++++++------------------
>  arch/arm/mach-vexpress/Kconfig      |   13 -------------
>  2 files changed, 7 insertions(+), 31 deletions(-)
> 
> diff --git a/arch/arm/configs/vexpress_defconfig b/arch/arm/configs/vexpress_defconfig
> index f2de51f..8af0213 100644
> --- a/arch/arm/configs/vexpress_defconfig
> +++ b/arch/arm/configs/vexpress_defconfig
> @@ -8,11 +8,9 @@ CONFIG_CGROUPS=y
>  CONFIG_CPUSETS=y
>  # CONFIG_UTS_NS is not set
>  # CONFIG_IPC_NS is not set
> -# CONFIG_USER_NS is not set
>  # CONFIG_PID_NS is not set
>  # CONFIG_NET_NS is not set
>  CONFIG_BLK_DEV_INITRD=y
> -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
>  CONFIG_PROFILING=y
>  CONFIG_OPROFILE=y
>  CONFIG_MODULES=y
> @@ -24,9 +22,14 @@ CONFIG_MODULE_UNLOAD=y
>  CONFIG_ARCH_VEXPRESS=y
>  CONFIG_ARCH_VEXPRESS_CA9X4=y
>  # CONFIG_SWP_EMULATE is not set
> +CONFIG_ARM_ERRATA_720789=y
> +CONFIG_ARM_ERRATA_751472=y
> +CONFIG_PL310_ERRATA_753970=y
> +CONFIG_ARM_ERRATA_754327=y
> +CONFIG_ARM_ERRATA_764369=y
> +CONFIG_PL310_ERRATA_769419=y
>  CONFIG_SMP=y
>  CONFIG_VMSPLIT_2G=y
> -CONFIG_HOTPLUG_CPU=y
>  CONFIG_AEABI=y
>  CONFIG_ZBOOT_ROM_TEXT=0x0
>  CONFIG_ZBOOT_ROM_BSS=0x0
> @@ -46,33 +49,26 @@ CONFIG_IP_PNP_BOOTP=y
>  # CONFIG_WIRELESS is not set
>  CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
>  CONFIG_MTD=y
> -CONFIG_MTD_CONCAT=y
> -CONFIG_MTD_PARTITIONS=y
>  CONFIG_MTD_CMDLINE_PARTS=y
>  CONFIG_MTD_CHAR=y
>  CONFIG_MTD_BLOCK=y
>  CONFIG_MTD_CFI=y
>  CONFIG_MTD_CFI_INTELEXT=y
>  CONFIG_MTD_CFI_AMDSTD=y
> -CONFIG_MTD_ARM_INTEGRATOR=y
> -CONFIG_MISC_DEVICES=y
>  # CONFIG_SCSI_PROC_FS is not set
>  CONFIG_BLK_DEV_SD=y
>  # CONFIG_SCSI_LOWLEVEL is not set
>  CONFIG_ATA=y
>  # CONFIG_SATA_PMP is not set
>  CONFIG_NETDEVICES=y
> -CONFIG_NET_ETHERNET=y
>  CONFIG_SMSC911X=y
> -# CONFIG_NETDEV_1000 is not set
> -# CONFIG_NETDEV_10000 is not set
>  # CONFIG_WLAN is not set
>  CONFIG_INPUT_EVDEV=y
>  # CONFIG_SERIO_SERPORT is not set
>  CONFIG_SERIO_AMBAKMI=y
> +CONFIG_LEGACY_PTY_COUNT=16
>  CONFIG_SERIAL_AMBA_PL011=y
>  CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
> -CONFIG_LEGACY_PTY_COUNT=16
>  # CONFIG_HW_RANDOM is not set
>  # CONFIG_HWMON is not set
>  CONFIG_FB=y
> @@ -103,7 +99,6 @@ CONFIG_HID_THRUSTMASTER=y
>  CONFIG_HID_ZEROPLUS=y
>  CONFIG_USB=y
>  CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
> -# CONFIG_USB_DEVICE_CLASS is not set
>  CONFIG_USB_MON=y
>  CONFIG_USB_ISP1760_HCD=y
>  CONFIG_USB_STORAGE=y
> @@ -120,9 +115,7 @@ CONFIG_TMPFS=y
>  CONFIG_JFFS2_FS=y
>  CONFIG_CRAMFS=y
>  CONFIG_NFS_FS=y
> -CONFIG_NFS_V3=y
>  CONFIG_ROOT_NFS=y
> -# CONFIG_RPCSEC_GSS_KRB5 is not set
>  CONFIG_NLS_CODEPAGE_437=y
>  CONFIG_NLS_ISO8859_1=y
>  CONFIG_MAGIC_SYSRQ=y
> @@ -131,10 +124,6 @@ CONFIG_DEBUG_KERNEL=y
>  CONFIG_DETECT_HUNG_TASK=y
>  # CONFIG_SCHED_DEBUG is not set
>  CONFIG_DEBUG_INFO=y
> -# CONFIG_RCU_CPU_STALL_DETECTOR is not set
>  CONFIG_DEBUG_USER=y
> -CONFIG_DEBUG_ERRORS=y
>  CONFIG_DEBUG_LL=y
>  CONFIG_EARLY_PRINTK=y
> -# CONFIG_CRYPTO_ANSI_CPRNG is not set
> -# CONFIG_CRYPTO_HW is not set
> diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
> index cf8730d..6a165fa7 100644
> --- a/arch/arm/mach-vexpress/Kconfig
> +++ b/arch/arm/mach-vexpress/Kconfig
> @@ -1,20 +1,8 @@
>  menu "Versatile Express platform type"
>  	depends on ARCH_VEXPRESS
>  
> -config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
> -	bool
> -	select ARM_ERRATA_720789
> -	select ARM_ERRATA_751472
> -	select PL310_ERRATA_753970 if CACHE_PL310
> -	help
> -	  Provides common dependencies for Versatile Express platforms
> -	  based on Cortex-A5 and Cortex-A9 processors. In order to
> -	  build a working kernel, you must also enable relevant core
> -	  tile support or Flattened Device Tree based support options.
> -
>  config ARCH_VEXPRESS_CA9X4
>  	bool "Versatile Express Cortex-A9x4 tile"
> -	select ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
>  	select ARM_GIC
>  	select CPU_V7
>  	select HAVE_SMP
> @@ -22,7 +10,6 @@ config ARCH_VEXPRESS_CA9X4
>  
>  config ARCH_VEXPRESS_DT
>  	bool "Device Tree support for Versatile Express platforms"
> -	select ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
>  	select ARM_GIC
>  	select ARM_PATCH_PHYS_VIRT
>  	select AUTO_ZRELADDR
> 

[PATCH 1/9] ARM: vexpress: remove automatic errata workaround selection

[Will Deacon]

On Wed, Jul 11, 2012 at 04:02:05PM +0100, Rob Herring wrote:
> On 07/11/2012 08:36 AM, Pawel Moll wrote:
> > From: Will Deacon <will.deacon@arm.com>
> > 
> > The vexpress Kconfig setup tries to be clever^Whelpful and selects some
> > errata workarounds for certain revisions of the Cortex-A9 and PL310,
> > which may be required depending on the coretile.
> > 
> > Since the mach-vexpress can support A5, A7 and A15 coretiles, let's
> > defer errata workaround selection to the user and instead propose
> > recommended workarounds in the defconfig. Note that the use of the
> > savedefconfig target removed some unrelated, redundant entries from the
> > file.
> 
> Most workarounds are runtime conditioned or don't have significant
> impact, so why not leave them enabled? For a single kernel image, we're
> going to have to basically turn on every errata work-around. Perhaps we
> should only have config options if they are not runtime enabled and have
> significant performance impact. I think having the settings in the
> defconfig is error prone, not mention if threats from Linus to remove
> all defconfigs actually happened it would be lost. In general, I don't
> think end users have enough information to determine what needs to be
> turned on. You need the errata list as well which is not public. Some of
> the errata help text says "rXpY and all later revisions" which changes
> when a new core revision comes out.

The problem I have with the current scheme for vexpress is that you can't
disable the workarounds when you know they are not needed. The Kconfig
*forces* them to be enabled -- that's certainly not right. Of the
workarounds in question, ARM_ERRATA_720789 is not runtime enabled and I
would like to deselect if when running on my A5, A7 or A15 cores. The
description clearly states it's an A9 erratum, so I don't think users will
have any difficulty knowing that they don't need it for other cores
(although I agree that it should be enabled for single zimage).

The defconfig changes were just a courtesy to reflect the change in the
Kconfig, I'm happy for them to be dropped.

Will

[PATCH 1/9] ARM: vexpress: remove automatic errata workaround selection

[Rob Herring]

On 07/11/2012 10:18 AM, Will Deacon wrote:
> On Wed, Jul 11, 2012 at 04:02:05PM +0100, Rob Herring wrote:
>> On 07/11/2012 08:36 AM, Pawel Moll wrote:
>>> From: Will Deacon <will.deacon@arm.com>
>>>
>>> The vexpress Kconfig setup tries to be clever^Whelpful and selects some
>>> errata workarounds for certain revisions of the Cortex-A9 and PL310,
>>> which may be required depending on the coretile.
>>>
>>> Since the mach-vexpress can support A5, A7 and A15 coretiles, let's
>>> defer errata workaround selection to the user and instead propose
>>> recommended workarounds in the defconfig. Note that the use of the
>>> savedefconfig target removed some unrelated, redundant entries from the
>>> file.
>>
>> Most workarounds are runtime conditioned or don't have significant
>> impact, so why not leave them enabled? For a single kernel image, we're
>> going to have to basically turn on every errata work-around. Perhaps we
>> should only have config options if they are not runtime enabled and have
>> significant performance impact. I think having the settings in the
>> defconfig is error prone, not mention if threats from Linus to remove
>> all defconfigs actually happened it would be lost. In general, I don't
>> think end users have enough information to determine what needs to be
>> turned on. You need the errata list as well which is not public. Some of
>> the errata help text says "rXpY and all later revisions" which changes
>> when a new core revision comes out.
> 
> The problem I have with the current scheme for vexpress is that you can't
> disable the workarounds when you know they are not needed. The Kconfig
> *forces* them to be enabled -- that's certainly not right. Of the
> workarounds in question, ARM_ERRATA_720789 is not runtime enabled and I
> would like to deselect if when running on my A5, A7 or A15 cores. The
> description clearly states it's an A9 erratum, so I don't think users will
> have any difficulty knowing that they don't need it for other cores
> (although I agree that it should be enabled for single zimage).
> 
> The defconfig changes were just a courtesy to reflect the change in the
> Kconfig, I'm happy for them to be dropped.

It's not a courtesy. It's the only place it remains documented other
than git history.

What if you just make the existing config option user selectable?

That doesn't solve the problem with this errata. Obviously on my newer
A9, I wouldn't want this errata enabled either (assuming there is
measurable impact). So we should come up with a better solution for
single kernel image.

Rob

> Will
> 

[PATCH 1/9] ARM: vexpress: remove automatic errata workaround selection

[Will Deacon]

On Wed, Jul 11, 2012 at 04:45:03PM +0100, Rob Herring wrote:
> On 07/11/2012 10:18 AM, Will Deacon wrote:
> > The problem I have with the current scheme for vexpress is that you can't
> > disable the workarounds when you know they are not needed. The Kconfig
> > *forces* them to be enabled -- that's certainly not right. Of the
> > workarounds in question, ARM_ERRATA_720789 is not runtime enabled and I
> > would like to deselect if when running on my A5, A7 or A15 cores. The
> > description clearly states it's an A9 erratum, so I don't think users will
> > have any difficulty knowing that they don't need it for other cores
> > (although I agree that it should be enabled for single zimage).
> > 
> > The defconfig changes were just a courtesy to reflect the change in the
> > Kconfig, I'm happy for them to be dropped.
> 
> It's not a courtesy. It's the only place it remains documented other
> than git history.

Sorry, I also meant to say that we could select them for the CA9X4 platform,
so the information wouldn't be lost.

> What if you just make the existing config option user selectable?

I think that's harder than it sounds. How would you do this without adding
vexpress-specific dependencies to the erratum config option itself? I
suppose you could make them default y for multi-platform kernels (I can't
remember if Arnd's single zImage changes had a config option for that).

> That doesn't solve the problem with this errata. Obviously on my newer
> A9, I wouldn't want this errata enabled either (assuming there is
> measurable impact). So we should come up with a better solution for
> single kernel image.

Agreed, and I think that's a discussion we should have with a wider
audience. For some of the simpler workarounds we could probably use code
patching like we do for the SMP/UP stuff and like (I think) powerpc does
too.

Will

[PATCH v2] ARM: vexpress: Config option for early printk console

[Pawel Moll]

Versatile Express platform can be used in different configurations,
the console UART used by early printk may be located at different
addresses in the address space.

This patch makes it possible to select the base address of a PL011
UART to be used as a console output in the kernel configuration.
The default behaviour is still the heuristic detecting memory map
on Cortex-A core tiles.

The zImage decompressor will use the same configuration values
or print out nothing if DEBUG_LL is not enabled.

Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
 arch/arm/Kconfig.debug                            |   26 +++++++++++++
 arch/arm/mach-vexpress/include/mach/debug-macro.S |   41 +++++++++++++++++++++
 arch/arm/mach-vexpress/include/mach/uncompress.h  |   14 +++++++
 3 files changed, 81 insertions(+)

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 01a1341..a03b5a7 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -310,6 +310,32 @@ choice
 		  The uncompressor code port configuration is now handled
 		  by CONFIG_S3C_LOWLEVEL_UART_PORT.
 
+	config DEBUG_VEXPRESS_UART0_DETECT
+		bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
+		depends on ARCH_VEXPRESS && CPU_CP15_MMU
+		help
+		  This option enables a simple heuristic which tries to determine
+		  the motherboard's memory map variant (original or RS1) and then
+		  choose the relevant UART0 base address.
+
+		  Note that this will only work with standard A-class core tiles,
+		  and may fail with non-standard SMM or custom software models.
+
+	config DEBUG_VEXPRESS_UART0_CA9
+		bool "Use PL011 UART0 at 0x10009000 (V2P-CA9 core tile)"
+		depends on ARCH_VEXPRESS
+		help
+		  This option selects UART0 at 0x10009000. Except for custom models,
+		  this applies only to the V2P-CA9 tile.
+
+	config DEBUG_VEXPRESS_UART0_RS1
+		bool "Use PL011 UART0 at 0x1c090000 (RS1 complaint tiles)"
+		depends on ARCH_VEXPRESS
+		help
+		  This option selects UART0 at 0x1c090000. This applies to most
+		  of the tiles using the RS1 memory map, including all new A-class
+		  core tiles, FPGA-based SMMs and software models.
+
 	config DEBUG_LL_UART_NONE
 		bool "No low-level debugging UART"
 		help
diff --git a/arch/arm/mach-vexpress/include/mach/debug-macro.S b/arch/arm/mach-vexpress/include/mach/debug-macro.S
index fa82247..9f509f5 100644
--- a/arch/arm/mach-vexpress/include/mach/debug-macro.S
+++ b/arch/arm/mach-vexpress/include/mach/debug-macro.S
@@ -18,6 +18,8 @@
 
 #define DEBUG_LL_VIRT_BASE		0xf8000000
 
+#if defined(CONFIG_DEBUG_VEXPRESS_UART0_DETECT)
+
 		.macro	addruart,rp,rv,tmp
 
 		@ Make an educated guess regarding the memory map:
@@ -41,3 +43,42 @@
 		.endm
 
 #include <asm/hardware/debug-pl01x.S>
+
+#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_CA9)
+
+		.macro	addruart,rp,rv,tmp
+		mov	\rp, #DEBUG_LL_UART_OFFSET
+		orr	\rv, \rp, #DEBUG_LL_VIRT_BASE
+		orr	\rp, \rp, #DEBUG_LL_PHYS_BASE
+		.endm
+
+#include <asm/hardware/debug-pl01x.S>
+
+#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_RS1)
+
+		.macro	addruart,rp,rv,tmp
+		mov	\rp, #DEBUG_LL_UART_OFFSET_RS1
+		orr	\rv, \rp, #DEBUG_LL_VIRT_BASE
+		orr	\rp, \rp, #DEBUG_LL_PHYS_BASE_RS1
+		.endm
+
+#include <asm/hardware/debug-pl01x.S>
+
+#else /* CONFIG_DEBUG_LL_UART_NONE */
+
+		.macro	addruart, rp, rv, tmp
+		/* Safe dummy values */
+		mov	\rp, #0
+		mov	\rv, #DEBUG_LL_VIRT_BASE
+		.endm
+
+		.macro	senduart,rd,rx
+		.endm
+
+		.macro	waituart,rd,rx
+		.endm
+
+		.macro	busyuart,rd,rx
+		.endm
+
+#endif
diff --git a/arch/arm/mach-vexpress/include/mach/uncompress.h b/arch/arm/mach-vexpress/include/mach/uncompress.h
index 7dab559..1e472eb 100644
--- a/arch/arm/mach-vexpress/include/mach/uncompress.h
+++ b/arch/arm/mach-vexpress/include/mach/uncompress.h
@@ -27,6 +27,7 @@
 
 static unsigned long get_uart_base(void)
 {
+#if defined(CONFIG_DEBUG_VEXPRESS_UART0_DETECT)
 	unsigned long mpcore_periph;
 
 	/*
@@ -42,6 +43,13 @@ static unsigned long get_uart_base(void)
 		return UART_BASE;
 	else
 		return UART_BASE_RS1;
+#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_CA9)
+	return UART_BASE;
+#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_RS1)
+	return UART_BASE_RS1;
+#else
+	return 0;
+#endif
 }
 
 /*
@@ -51,6 +59,9 @@ static inline void putc(int c)
 {
 	unsigned long base = get_uart_base();
 
+	if (!base)
+		return;
+
 	while (AMBA_UART_FR(base) & (1 << 5))
 		barrier();
 
@@ -61,6 +72,9 @@ static inline void flush(void)
 {
 	unsigned long base = get_uart_base();
 
+	if (!base)
+		return;
+
 	while (AMBA_UART_FR(base) & (1 << 3))
 		barrier();
 }
-- 
1.7.9.5

[PATCH 3/9] ARM: versatile: Make plat-versatile clock optional

[Linus Walleij]

On Wed, Jul 11, 2012 at 3:36 PM, Pawel Moll <pawel.moll@arm.com> wrote:

> ... in preparation for common clock coming for Integrator
> and Versatile Express.
>
> Based on Linus Walleij's "ARM: integrator: convert to common
> clock" patch.
>
> Signed-off-by: Pawel Moll <pawel.moll@arm.com>

I think Mike is already queueing my patch, so if you're changing
anything you should build on top of that and submit it to the
clk tree.

Mike, is the Integrator patches making it into your for-next branch?

The merge window is closing in you know...

Yours,
Linus Walleij

[PATCH 4/9] ARM: vexpress: Initial common clock support

[Linus Walleij]

Hi Pawel,

can you please move the vexpress clock implementation to
drivers/clk/versatile/clk-vexpress.c as per the pattern from the
Integrator rework?

Clock drivers go into the drivers/* hierarchy just like any other
driver these days.

You need to base that on top of the Integrator patches of course,
these are here, but I think Mike did some alterations though:
http://git.kernel.org/?p=linux/kernel/git/linusw/linux-integrator.git;a=shortlog;h=refs/heads/integrator-clk

Yours,
Linus Walleij

[PATCH 4/9] ARM: vexpress: Initial common clock support

[Pawel Moll]

On Wed, 2012-07-11 at 17:51 +0100, Linus Walleij wrote:
> Hi Pawel,
> 
> can you please move the vexpress clock implementation to
> drivers/clk/versatile/clk-vexpress.c as per the pattern from the
> Integrator rework?
>
> Clock drivers go into the drivers/* hierarchy just like any other
> driver these days.

I will, but I'd rather avoid doing this right now.

> >This is a simple conversion of the existing state and will be
> > extended (and migrated to drivers/clk) in the near future.
> 
This patch is only a first step. I'm working now on a major rework of
the VE control infrastructure, and I do have drivers/clk/vexpress (can
be versatile, I don't really mind) directory in my local repo. This will
happen in time for the next merge window.

Cheers!

Pawel

[PATCH 3/9] ARM: versatile: Make plat-versatile clock optional

[Pawel Moll]

On Wed, 2012-07-11 at 17:43 +0100, Linus Walleij wrote:
> On Wed, Jul 11, 2012 at 3:36 PM, Pawel Moll <pawel.moll@arm.com> wrote:
> 
> > ... in preparation for common clock coming for Integrator
> > and Versatile Express.
> >
> > Based on Linus Walleij's "ARM: integrator: convert to common
> > clock" patch.
> >
> > Signed-off-by: Pawel Moll <pawel.moll@arm.com>
> 
> I think Mike is already queueing my patch, so if you're changing
> anything you should build on top of that and submit it to the
> clk tree.

That's why I split this part to a separate patch. When it comes to merge
the arm-soc people will be able to drop it completely.

Pawe?

[PATCH 1/9] ARM: vexpress: remove automatic errata workaround selection

[Rob Herring]

On 07/11/2012 10:53 AM, Will Deacon wrote:
> On Wed, Jul 11, 2012 at 04:45:03PM +0100, Rob Herring wrote:
>> On 07/11/2012 10:18 AM, Will Deacon wrote:
>>> The problem I have with the current scheme for vexpress is that you can't
>>> disable the workarounds when you know they are not needed. The Kconfig
>>> *forces* them to be enabled -- that's certainly not right. Of the
>>> workarounds in question, ARM_ERRATA_720789 is not runtime enabled and I
>>> would like to deselect if when running on my A5, A7 or A15 cores. The
>>> description clearly states it's an A9 erratum, so I don't think users will
>>> have any difficulty knowing that they don't need it for other cores
>>> (although I agree that it should be enabled for single zimage).
>>>
>>> The defconfig changes were just a courtesy to reflect the change in the
>>> Kconfig, I'm happy for them to be dropped.
>>
>> It's not a courtesy. It's the only place it remains documented other
>> than git history.
> 
> Sorry, I also meant to say that we could select them for the CA9X4 platform,
> so the information wouldn't be lost.
> 
>> What if you just make the existing config option user selectable?
> 
> I think that's harder than it sounds. How would you do this without adding
> vexpress-specific dependencies to the erratum config option itself? I
> suppose you could make them default y for multi-platform kernels (I can't
> remember if Arnd's single zImage changes had a config option for that).
> 

You're not following what I meant. Something like this:

diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index cf8730d..fc3730f 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -2,7 +2,8 @@ menu "Versatile Express platform type"
        depends on ARCH_VEXPRESS

 config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
-       bool
+       bool "Enable A5 and A9 only errata work-arounds"
+       default y
        select ARM_ERRATA_720789
        select ARM_ERRATA_751472
        select PL310_ERRATA_753970 if CACHE_PL310
@@ -14,7 +15,6 @@ config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA

 config ARCH_VEXPRESS_CA9X4
        bool "Versatile Express Cortex-A9x4 tile"
-       select ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
        select ARM_GIC
        select CPU_V7
        select HAVE_SMP
@@ -22,7 +22,6 @@ config ARCH_VEXPRESS_CA9X4

 config ARCH_VEXPRESS_DT
        bool "Device Tree support for Versatile Express platforms"
-       select ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
        select ARM_GIC
        select ARM_PATCH_PHYS_VIRT
        select AUTO_ZRELADDR

>> That doesn't solve the problem with this errata. Obviously on my newer
>> A9, I wouldn't want this errata enabled either (assuming there is
>> measurable impact). So we should come up with a better solution for
>> single kernel image.
> 
> Agreed, and I think that's a discussion we should have with a wider
> audience. For some of the simpler workarounds we could probably use code
> patching like we do for the SMP/UP stuff and like (I think) powerpc does
> too.
> 
> Will
> 

[PATCH 1/9] ARM: vexpress: remove automatic errata workaround selection

[Will Deacon]

On Wed, Jul 11, 2012 at 07:06:29PM +0100, Rob Herring wrote:
> On 07/11/2012 10:53 AM, Will Deacon wrote:
> > On Wed, Jul 11, 2012 at 04:45:03PM +0100, Rob Herring wrote:
> >> What if you just make the existing config option user selectable?
> > 
> > I think that's harder than it sounds. How would you do this without adding
> > vexpress-specific dependencies to the erratum config option itself? I
> > suppose you could make them default y for multi-platform kernels (I can't
> > remember if Arnd's single zImage changes had a config option for that).
> > 
> 
> You're not following what I meant. Something like this:

Indeed, I thought you were referring to the workaround options themselves.

> diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
> index cf8730d..fc3730f 100644
> --- a/arch/arm/mach-vexpress/Kconfig
> +++ b/arch/arm/mach-vexpress/Kconfig
> @@ -2,7 +2,8 @@ menu "Versatile Express platform type"
>         depends on ARCH_VEXPRESS
> 
>  config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
> -       bool
> +       bool "Enable A5 and A9 only errata work-arounds"
> +       default y
>         select ARM_ERRATA_720789
>         select ARM_ERRATA_751472
>         select PL310_ERRATA_753970 if CACHE_PL310
> @@ -14,7 +15,6 @@ config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
> 
>  config ARCH_VEXPRESS_CA9X4
>         bool "Versatile Express Cortex-A9x4 tile"
> -       select ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
>         select ARM_GIC
>         select CPU_V7
>         select HAVE_SMP
> @@ -22,7 +22,6 @@ config ARCH_VEXPRESS_CA9X4
> 
>  config ARCH_VEXPRESS_DT
>         bool "Device Tree support for Versatile Express platforms"
> -       select ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
>         select ARM_GIC
>         select ARM_PATCH_PHYS_VIRT
>         select AUTO_ZRELADDR

Gotcha, thanks for the diff. That works nicely for the current situation and
we can revisit the whole errata workaround config options issue when the
single zimage changes are in.

Cheers,

Will

[PATCH 3/9] ARM: versatile: Make plat-versatile clock optional

[Mike Turquette]

On 20120711-18:43, Linus Walleij wrote:
> On Wed, Jul 11, 2012 at 3:36 PM, Pawel Moll <pawel.moll@arm.com> wrote:
> 
> > ... in preparation for common clock coming for Integrator
> > and Versatile Express.
> >
> > Based on Linus Walleij's "ARM: integrator: convert to common
> > clock" patch.
> >
> > Signed-off-by: Pawel Moll <pawel.moll@arm.com>
> 
> I think Mike is already queueing my patch, so if you're changing
> anything you should build on top of that and submit it to the
> clk tree.
> 
> Mike, is the Integrator patches making it into your for-next branch?
> 

They are there locally and will be pushed in the next hour.

> The merge window is closing in you know...
> 

Oh I'm well aware.  I ended up rebasing clk-3.6 (sigh) so that it would
be on top v3.5-rc6 and pull in the clk-fixes stuff that way.  But this
way I'm getting all of my ducks in a row for the 3.6 merge window.

Regards,
Mike

> Yours,
> Linus Walleij

[PATCH v2] ARM: vexpress: remove automatic errata workaround selection

[Pawel Moll]

From: Will Deacon <will.deacon@arm.com>

The vexpress Kconfig setup tries to be clever^Whelpful and selects some
errata workarounds for certain revisions of the Cortex-A9 and PL310,
which may be required depending on the core tile.

Since the mach-vexpress can support A5, A7 and A15 coretiles, let's
make errata workaround selection optional.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
 arch/arm/mach-vexpress/Kconfig |    5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

Hi Both,

Here it is. I've kept Will's Signed-off-by for now, but it seems to me
Rob should be signing this off. If you don't mind that I'll put Rob's
name in the final version for arm-soc folk.

Cheers!

Pawel

diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index cf8730d..fc3730f 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -2,7 +2,8 @@ menu "Versatile Express platform type"
 	depends on ARCH_VEXPRESS
 
 config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
-	bool
+	bool "Enable A5 and A9 only errata work-arounds"
+	default y
 	select ARM_ERRATA_720789
 	select ARM_ERRATA_751472
 	select PL310_ERRATA_753970 if CACHE_PL310
@@ -14,7 +15,6 @@ config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
 
 config ARCH_VEXPRESS_CA9X4
 	bool "Versatile Express Cortex-A9x4 tile"
-	select ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
 	select ARM_GIC
 	select CPU_V7
 	select HAVE_SMP
@@ -22,7 +22,6 @@ config ARCH_VEXPRESS_CA9X4
 
 config ARCH_VEXPRESS_DT
 	bool "Device Tree support for Versatile Express platforms"
-	select ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
 	select ARM_GIC
 	select ARM_PATCH_PHYS_VIRT
 	select AUTO_ZRELADDR
-- 
1.7.9.5

[PATCH v2] ARM: vexpress: remove automatic errata workaround selection

[Will Deacon]

On Thu, Jul 12, 2012 at 11:17:16AM +0100, Pawel Moll wrote:
> Hi Both,
> 
> Here it is. I've kept Will's Signed-off-by for now, but it seems to me
> Rob should be signing this off. If you don't mind that I'll put Rob's
> name in the final version for arm-soc folk.

Fine by me, I just want to flush my TLB by ASID again :)

Will

[PATCH v2] ARM: vexpress: remove automatic errata workaround selection

[Rob Herring]

On 07/12/2012 05:17 AM, Pawel Moll wrote:
> From: Will Deacon <will.deacon@arm.com>
> 
> The vexpress Kconfig setup tries to be clever^Whelpful and selects some
> errata workarounds for certain revisions of the Cortex-A9 and PL310,
> which may be required depending on the core tile.
> 
> Since the mach-vexpress can support A5, A7 and A15 coretiles, let's
> make errata workaround selection optional.
> 
> Signed-off-by: Will Deacon <will.deacon@arm.com>
> Signed-off-by: Pawel Moll <pawel.moll@arm.com>
> ---
>  arch/arm/mach-vexpress/Kconfig |    5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
> 
> Hi Both,
> 
> Here it is. I've kept Will's Signed-off-by for now, but it seems to me
> Rob should be signing this off. If you don't mind that I'll put Rob's
> name in the final version for arm-soc folk.

Well, Will wrote the commit message so both should be.

Rob

> 
> Cheers!
> 
> Pawel
> 
> diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
> index cf8730d..fc3730f 100644
> --- a/arch/arm/mach-vexpress/Kconfig
> +++ b/arch/arm/mach-vexpress/Kconfig
> @@ -2,7 +2,8 @@ menu "Versatile Express platform type"
>  	depends on ARCH_VEXPRESS
>  
>  config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
> -	bool
> +	bool "Enable A5 and A9 only errata work-arounds"
> +	default y
>  	select ARM_ERRATA_720789
>  	select ARM_ERRATA_751472
>  	select PL310_ERRATA_753970 if CACHE_PL310
> @@ -14,7 +15,6 @@ config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
>  
>  config ARCH_VEXPRESS_CA9X4
>  	bool "Versatile Express Cortex-A9x4 tile"
> -	select ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
>  	select ARM_GIC
>  	select CPU_V7
>  	select HAVE_SMP
> @@ -22,7 +22,6 @@ config ARCH_VEXPRESS_CA9X4
>  
>  config ARCH_VEXPRESS_DT
>  	bool "Device Tree support for Versatile Express platforms"
> -	select ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
>  	select ARM_GIC
>  	select ARM_PATCH_PHYS_VIRT
>  	select AUTO_ZRELADDR
> 

[PATCH 4/9] ARM: vexpress: Initial common clock support

[Turquette, Mike]

On Wed, Jul 11, 2012 at 9:57 AM, Pawel Moll <pawel.moll@arm.com> wrote:
> On Wed, 2012-07-11 at 17:51 +0100, Linus Walleij wrote:
>> Hi Pawel,
>>
>> can you please move the vexpress clock implementation to
>> drivers/clk/versatile/clk-vexpress.c as per the pattern from the
>> Integrator rework?
>>
>> Clock drivers go into the drivers/* hierarchy just like any other
>> driver these days.
>
> I will, but I'd rather avoid doing this right now.
>
>> >This is a simple conversion of the existing state and will be
>> > extended (and migrated to drivers/clk) in the near future.
>>
> This patch is only a first step. I'm working now on a major rework of
> the VE control infrastructure, and I do have drivers/clk/vexpress (can
> be versatile, I don't really mind) directory in my local repo. This will
> happen in time for the next merge window.
>

I'd rather not take any more patches this close to the 3.6 merge
window.  How do you feel about holding onto this patch and
implementing some of the longer term changes mentioned by Linus
towards 3.7?

Regards,
Mike

> Cheers!
>
> Pawel
>
>

[PATCH 4/9] ARM: vexpress: Initial common clock support

[Pawel Moll]

On Mon, 2012-07-16 at 21:15 +0100, Turquette, Mike wrote:
> > This patch is only a first step. I'm working now on a major rework of
> > the VE control infrastructure, and I do have drivers/clk/vexpress (can
> > be versatile, I don't really mind) directory in my local repo. This will
> > happen in time for the next merge window.
> 
> I'd rather not take any more patches this close to the 3.6 merge
> window.  How do you feel about holding onto this patch and
> implementing some of the longer term changes mentioned by Linus
> towards 3.7?

Sorry, I wasn't precise enough... What I meant:

1. The "micro-changes" (contained to arch/arm/mach-vexpress) are going
to 3.6 via arm-soc (already pulled by Arnd).

2. The "big changes" are waiting till 3.7 merge window, and the
drivers/clk/*/clk-vexpress.c will go through your tree.

Hope it makes sense,

Pawe?