[U-Boot] [NEXT PATCH v1 0/7] In this patchset, a new i.MX35 board is added implementing

[U-Boot] [NEXT PATCH v1 0/7] In this patchset, a new i.MX35 board is added implementing

[Stefano Babic]

the internal boot mode and using the general SPL Framework.

For this reason, this patchset depends on:

Tom Rini's SPL generic framework:
	http://lists.denx.de/pipermail/u-boot/2012-August/132813.html

To fix that relocation should not happen in SPL, the following patch
is also required:

	http://patchwork.ozlabs.org/patch/181166/

The woodburn board boots from SD Card. However, the presented way
introducing SPL is general, and can applied to other devices.



Stefano Babic (7):
  ARM: Fix start.S when used with SPL in arm1136
  NAND: added NAND type to nand_ids
  MX35: add LOW_LEVEL_SRAM_STACK to use SPL_FRAMEWORK
  MX35: Add soc_boot_mode and soc_boot_device to MX35
  SPL: Added MLO for mx35 SOC to SPL Makefile
  ARM: Add MLO target to arm1136
  MX35: add support for woodburn board

 MAINTAINERS                                   |    1 +
 arch/arm/cpu/arm1136/config.mk                |    3 +
 arch/arm/cpu/arm1136/mx35/generic.c           |   80 ++++++
 arch/arm/cpu/arm1136/start.S                  |   31 ++-
 arch/arm/cpu/arm1136/u-boot-spl.lds           |   62 +++++
 arch/arm/include/asm/arch-mx35/imx-regs.h     |    2 +
 arch/arm/include/asm/arch-mx35/mmc_host_def.h |   31 +++
 arch/arm/include/asm/arch-mx35/spl.h          |   38 +++
 arch/arm/include/asm/arch-mx35/sys_proto.h    |    2 +
 board/woodburn/Makefile                       |   43 ++++
 board/woodburn/imximage.cfg                   |    4 +
 board/woodburn/lowlevel_init.S                |   93 +++++++
 board/woodburn/mx35_sdram.c                   |  137 +++++++++++
 board/woodburn/woodburn.c                     |  240 ++++++++++++++++++
 boards.cfg                                    |    2 +
 drivers/mtd/nand/nand_ids.c                   |    2 +
 include/configs/woodburn.h                    |   33 +++
 include/configs/woodburn_common.h             |  322 +++++++++++++++++++++++++
 include/configs/woodburn_sd.h                 |   65 +++++
 spl/Makefile                                  |    6 +
 20 files changed, 1186 insertions(+), 11 deletions(-)
 create mode 100644 arch/arm/cpu/arm1136/u-boot-spl.lds
 create mode 100644 arch/arm/include/asm/arch-mx35/mmc_host_def.h
 create mode 100644 arch/arm/include/asm/arch-mx35/spl.h
 create mode 100644 board/woodburn/Makefile
 create mode 100644 board/woodburn/imximage.cfg
 create mode 100644 board/woodburn/lowlevel_init.S
 create mode 100644 board/woodburn/mx35_sdram.c
 create mode 100644 board/woodburn/woodburn.c
 create mode 100644 include/configs/woodburn.h
 create mode 100644 include/configs/woodburn_common.h
 create mode 100644 include/configs/woodburn_sd.h

-- 
1.7.9.5

[U-Boot] [NEXT PATCH v1 1/7] ARM: Fix start.S when used with SPL in arm1136

[Stefano Babic]

This patch modifies start.S for the arm1136 to make it
conform to start.S  in armv7 architecture, to make it
usable if the SPL framework is used.

Signed-off-by: Stefano Babic <sbabic@denx.de>
---
 arch/arm/cpu/arm1136/start.S |   31 ++++++++++++++++++++-----------
 1 file changed, 20 insertions(+), 11 deletions(-)

diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S
index 3752af9..5d3b4c2 100644
--- a/arch/arm/cpu/arm1136/start.S
+++ b/arch/arm/cpu/arm1136/start.S
@@ -100,6 +100,10 @@ _TEXT_BASE:
 _bss_start_ofs:
 	.word __bss_start - _start
 
+.global	_image_copy_end_ofs
+_image_copy_end_ofs:
+	.word 	__image_copy_end - _start
+
 .globl _bss_end_ofs
 _bss_end_ofs:
 	.word __bss_end__ - _start
@@ -193,7 +197,7 @@ stack_setup:
 	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
 	beq	clear_bss		/* skip relocation */
 	mov	r1, r6			/* r1 <- scratch for copy_loop */
-	ldr	r3, _bss_start_ofs
+	ldr	r3, _image_copy_end_ofs
 	add	r2, r0, r3		/* r2 <- source end address	    */
 
 copy_loop:
@@ -241,15 +245,28 @@ fixnext:
 	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
 	cmp	r2, r3
 	blo	fixloop
+	b	clear_bss
+
+_rel_dyn_start_ofs:
+	.word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+	.word __rel_dyn_end - _start
+_dynsym_start_ofs:
+	.word __dynsym_start - _start
 #endif
 
 clear_bss:
-#ifndef CONFIG_SPL_BUILD
+#ifdef CONFIG_SPL_BUILD
+	/* No relocation for SPL */
+	ldr	r0, =__bss_start
+	ldr	r1, =__bss_end__
+#else
 	ldr	r0, _bss_start_ofs
 	ldr	r1, _bss_end_ofs
 	mov	r4, r6			/* reloc addr */
 	add	r0, r0, r4
 	add	r1, r1, r4
+#endif
 	mov	r2, #0x00000000		/* clear			    */
 
 clbss_l:cmp	r0, r1			/* clear loop... */
@@ -258,7 +275,6 @@ clbss_l:cmp	r0, r1			/* clear loop... */
 	add	r0, r0, #4
 	b	clbss_l
 clbss_e:
-#endif	/* #ifndef CONFIG_SPL_BUILD */
 
 /*
  * We are done. Do not return, instead branch to second part of board
@@ -273,7 +289,7 @@ _nand_boot_ofs:
 #else
 jump_2_ram:
 	ldr	r0, _board_init_r_ofs
-	ldr     r1, _TEXT_BASE
+	adr	r1, _start
 	add	lr, r0, r1
 	add	lr, lr, r9
 	/* setup parameters for board_init_r */
@@ -286,13 +302,6 @@ _board_init_r_ofs:
 	.word board_init_r - _start
 #endif
 
-_rel_dyn_start_ofs:
-	.word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-	.word __rel_dyn_end - _start
-_dynsym_start_ofs:
-	.word __dynsym_start - _start
-
 /*
  *************************************************************************
  *
-- 
1.7.9.5

[U-Boot] [NEXT PATCH v1 2/7] NAND: added NAND type to nand_ids

[Stefano Babic]

Signed-off-by: Stefano Babic <sbabic@denx.de>
---
 drivers/mtd/nand/nand_ids.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
index 3953549..fe75686 100644
--- a/drivers/mtd/nand/nand_ids.c
+++ b/drivers/mtd/nand/nand_ids.c
@@ -131,6 +131,8 @@ const struct nand_flash_dev nand_flash_ids[] = {
 	/* 128 Gigabit */
 	{"NAND 16GiB 1,8V 8-bit",	0x1A, 0, 16384, 0, LP_OPTIONS},
 	{"NAND 16GiB 3,3V 8-bit",	0x3A, 0, 16384, 0, LP_OPTIONS},
+	{"NAND 16GiB 3,3V 8-bit",	0x48, 4096, 16384, 0x100000,
+		LP_OPTIONS},
 	{"NAND 16GiB 1,8V 16-bit",	0x2A, 0, 16384, 0, LP_OPTIONS16},
 	{"NAND 16GiB 3,3V 16-bit",	0x4A, 0, 16384, 0, LP_OPTIONS16},
 
-- 
1.7.9.5

[U-Boot] [NEXT PATCH v1 3/7] MX35: add LOW_LEVEL_SRAM_STACK to use SPL_FRAMEWORK

[Stefano Babic]

Signed-off-by: Stefano Babic <sbabic@denx.de>
---
 arch/arm/include/asm/arch-mx35/imx-regs.h |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h
index 3146006..6cd6460 100644
--- a/arch/arm/include/asm/arch-mx35/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx35/imx-regs.h
@@ -31,6 +31,8 @@
 #define IRAM_BASE_ADDR		0x10000000	/* internal ram */
 #define IRAM_SIZE		0x00020000	/* 128 KB */
 
+#define LOW_LEVEL_SRAM_STACK	0x1001E000
+
 /*
  * AIPS 1
  */
-- 
1.7.9.5

[U-Boot] [NEXT PATCH v1 4/7] MX35: Add soc_boot_mode and soc_boot_device to MX35

[Stefano Babic]

The functions are required to use the generic
SPL Framework.

Signed-off-by: Stefano Babic <sbabic@denx.de>
---
 arch/arm/cpu/arm1136/mx35/generic.c           |   80 +++++++++++++++++++++++++
 arch/arm/cpu/arm1136/u-boot-spl.lds           |   62 +++++++++++++++++++
 arch/arm/include/asm/arch-mx35/mmc_host_def.h |   31 ++++++++++
 arch/arm/include/asm/arch-mx35/spl.h          |   38 ++++++++++++
 4 files changed, 211 insertions(+)
 create mode 100644 arch/arm/cpu/arm1136/u-boot-spl.lds
 create mode 100644 arch/arm/include/asm/arch-mx35/mmc_host_def.h
 create mode 100644 arch/arm/include/asm/arch-mx35/spl.h

diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c
index 986b1f9..8fbe09b 100644
--- a/arch/arm/cpu/arm1136/mx35/generic.c
+++ b/arch/arm/cpu/arm1136/mx35/generic.c
@@ -31,6 +31,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 #include <netdev.h>
+#include <spl.h>
 
 #define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel))
 #define CLK_CODE_ARM(c)		(((c) >> 16) & 0xFF)
@@ -488,3 +489,82 @@ void reset_cpu(ulong addr)
 	struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
 	writew(4, &wdog->wcr);
 }
+
+#define RCSR_MEM_CTL_WEIM	0
+#define RCSR_MEM_CTL_NAND	1
+#define RCSR_MEM_CTL_SD		2
+#define RCSR_MEM_TYPE_NOR	0
+#define RCSR_MEM_TYPE_ONENAND	2
+#define RCSR_MEM_TYPE_SD	0
+#define RCSR_MEM_TYPE_I2C	2
+#define RCSR_MEM_TYPE_SPI	3
+
+u32 spl_boot_device(void)
+{
+	puts("spl_boot_device\n");
+	struct ccm_regs *ccm =
+		(struct ccm_regs *)IMX_CCM_BASE;
+
+#if 1
+	return BOOT_DEVICE_MMC1;
+#endif
+
+	u32 rcsr = readl(&ccm->rcsr);
+	u32 mem_type, mem_ctl;
+
+	/* In external mode, no boot device is returned */
+	if ((rcsr >> 10) & 0x03)
+		return BOOT_DEVICE_NONE;
+
+	mem_ctl = (rcsr >> 25) & 0x03;
+	mem_type = (rcsr >> 23) & 0x03;
+
+	switch (mem_ctl) {
+	case RCSR_MEM_CTL_WEIM:
+		switch (mem_type) {
+		case RCSR_MEM_TYPE_NOR:
+			return BOOT_DEVICE_NOR;
+		case RCSR_MEM_TYPE_ONENAND:
+			return BOOT_DEVICE_ONE_NAND;
+		default:
+			return BOOT_DEVICE_NONE;
+		}
+	case RCSR_MEM_CTL_NAND:
+		return BOOT_DEVICE_NAND;
+	case RCSR_MEM_CTL_SD:
+		switch (mem_type) {
+		case RCSR_MEM_TYPE_SD:
+			return BOOT_DEVICE_MMC1;
+		case RCSR_MEM_TYPE_I2C:
+			return BOOT_DEVICE_I2C;
+		case RCSR_MEM_TYPE_SPI:
+			return BOOT_DEVICE_SPI;
+		default:
+			return BOOT_DEVICE_NONE;
+		}
+	}
+
+	return BOOT_DEVICE_NONE;
+}
+
+#ifdef CONFIG_SPL_BUILD
+u32 spl_boot_mode(void)
+{
+	puts("spl_boot_mode\n");
+	switch (spl_boot_device()) {
+	case BOOT_DEVICE_MMC1:
+#ifdef CONFIG_SPL_FAT_SUPPORT
+		return MMCSD_MODE_FAT;
+#else
+		return MMCSD_MODE_RAW;
+#endif
+		break;
+	case BOOT_DEVICE_NAND:
+		return 0;
+		break;
+	default:
+		puts("spl: ERROR:  unsupported device\n");
+		hang();
+	}
+}
+#endif
diff --git a/arch/arm/cpu/arm1136/u-boot-spl.lds b/arch/arm/cpu/arm1136/u-boot-spl.lds
new file mode 100644
index 0000000..a0462ab
--- /dev/null
+++ b/arch/arm/cpu/arm1136/u-boot-spl.lds
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *	Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+		LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+		LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	.text      :
+	{
+	__start = .;
+	  arch/arm/cpu/arm1136/start.o	(.text)
+	  *(.text*)
+	} >.sram
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+	. = ALIGN(4);
+	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+	. = ALIGN(4);
+	__image_copy_end = .;
+	_end = .;
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} >.sdram
+}
diff --git a/arch/arm/include/asm/arch-mx35/mmc_host_def.h b/arch/arm/include/asm/arch-mx35/mmc_host_def.h
new file mode 100644
index 0000000..775b955
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx35/mmc_host_def.h
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation's version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef MMC_HOST_DEF_H
+#define MMC_HOST_DEF_H
+
+/* Driver definitions */
+#define MMCSD_SECTOR_SIZE		512
+
+#endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-mx35/spl.h b/arch/arm/include/asm/arch-mx35/spl.h
new file mode 100644
index 0000000..91d11ae
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx35/spl.h
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_SPL_H_
+
+#define BOOT_DEVICE_NONE	0
+#define BOOT_DEVICE_XIP		1
+#define BOOT_DEVICE_XIPWAIT	2
+#define BOOT_DEVICE_NAND	3
+#define BOOT_DEVICE_ONE_NAND	4
+#define BOOT_DEVICE_MMC1	5
+#define BOOT_DEVICE_MMC2	6
+#define BOOT_DEVICE_MMC2_2	7
+#define BOOT_DEVICE_NOR		8
+#define BOOT_DEVICE_I2C		9
+#define BOOT_DEVICE_SPI		10
+
+#endif
-- 
1.7.9.5

[U-Boot] [NEXT PATCH v1 5/7] SPL: Added MLO for mx35 SOC to SPL Makefile

[Stefano Babic]

Signed-off-by: Stefano Babic <sbabic@denx.de>
---
 spl/Makefile |    6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/spl/Makefile b/spl/Makefile
index f96c08e..77fc405 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -109,6 +109,12 @@ $(OBJTREE)/MLO:	$(obj)u-boot-spl.bin
 		-a $(CONFIG_SPL_TEXT_BASE) -d $< $@
 endif
 
+ifneq ($(CONFIG_IMX_CONFIG),)
+$(OBJTREE)/MLO:	$(obj)u-boot-spl.bin
+	$(OBJTREE)/tools/mkimage -n  $(SRCTREE)/$(CONFIG_IMX_CONFIG) -T imximage \
+		-e $(CONFIG_SPL_TEXT_BASE) -d $< $@
+endif
+
 ALL-y	+= $(obj)u-boot-spl.bin
 
 ifdef CONFIG_SAMSUNG
-- 
1.7.9.5

[U-Boot] [NEXT PATCH v1 6/7] ARM: Add MLO target to arm1136

[Stefano Babic]

Signed-off-by: Stefano Babic <sbabic@denx.de>
---
 arch/arm/cpu/arm1136/config.mk |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/cpu/arm1136/config.mk b/arch/arm/cpu/arm1136/config.mk
index efee0d1..a6c1178 100644
--- a/arch/arm/cpu/arm1136/config.mk
+++ b/arch/arm/cpu/arm1136/config.mk
@@ -31,3 +31,6 @@ PLATFORM_CPPFLAGS += -march=armv5
 # =========================================================================
 PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
 PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
+ifdef CONFIG_SPL_BUILD
+ALL-y	+= $(OBJTREE)/MLO
+endif
-- 
1.7.9.5

[U-Boot] [NEXT PATCH v1 7/7] MX35: add support for woodburn board

[Stefano Babic]

The woodburn board is based on the MX35 SOC.
Support for both external (NOR) and internal
(SD Card) boot mode are added. It uses the
generic SPL framework to implement the internal boot
mode.

The following peripherals are supported:
	- Ethernet (FEC)
	- SD Card
	- NAND (16 Gb)
	- NOR Flash

In the internal boot mode, a simple imximage header
file is generated to set the address in internal RAM
where the SOC must copy the SPL code. The initial setup
is then demanded to the SPL itself.

Signed-off-by: Stefano Babic <sbabic@denx.de>
---
 MAINTAINERS                                |    1 +
 arch/arm/include/asm/arch-mx35/sys_proto.h |    2 +
 board/woodburn/Makefile                    |   43 ++++
 board/woodburn/imximage.cfg                |    4 +
 board/woodburn/lowlevel_init.S             |   93 ++++++++
 board/woodburn/mx35_sdram.c                |  137 ++++++++++++
 board/woodburn/woodburn.c                  |  240 +++++++++++++++++++++
 boards.cfg                                 |    2 +
 include/configs/woodburn.h                 |   33 +++
 include/configs/woodburn_common.h          |  322 ++++++++++++++++++++++++++++
 include/configs/woodburn_sd.h              |   65 ++++++
 11 files changed, 942 insertions(+)
 create mode 100644 board/woodburn/Makefile
 create mode 100644 board/woodburn/imximage.cfg
 create mode 100644 board/woodburn/lowlevel_init.S
 create mode 100644 board/woodburn/mx35_sdram.c
 create mode 100644 board/woodburn/woodburn.c
 create mode 100644 include/configs/woodburn.h
 create mode 100644 include/configs/woodburn_common.h
 create mode 100644 include/configs/woodburn_sd.h

diff --git a/MAINTAINERS b/MAINTAINERS
index c5a6f2f..f6ee8d1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -585,6 +585,7 @@ Stefano Babic <sbabic@denx.de>
 	trizepsiv	xscale/pxa
 	twister		omap3
  	vision2		i.MX51
+	woodburn	i.MX35
 
 Jason Liu <r64343@freescale.com>
 
diff --git a/arch/arm/include/asm/arch-mx35/sys_proto.h b/arch/arm/include/asm/arch-mx35/sys_proto.h
index 422eb52..887f74b 100644
--- a/arch/arm/include/asm/arch-mx35/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx35/sys_proto.h
@@ -25,6 +25,8 @@
 #define _SYS_PROTO_H_
 
 u32 get_cpu_rev(void);
+void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config,
+	u32 row, u32 col, u32 dsize, u32 refresh);
 #define is_soc_rev(rev)	((get_cpu_rev() & 0xFF) - rev)
 void sdelay(unsigned long);
 
diff --git a/board/woodburn/Makefile b/board/woodburn/Makefile
new file mode 100644
index 0000000..09caf63
--- /dev/null
+++ b/board/woodburn/Makefile
@@ -0,0 +1,43 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= woodburn.o mx35_sdram.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/woodburn/imximage.cfg b/board/woodburn/imximage.cfg
new file mode 100644
index 0000000..b4cc8ec
--- /dev/null
+++ b/board/woodburn/imximage.cfg
@@ -0,0 +1,4 @@
+BOOT_FROM      sd
+
+# DDR2 init
+DATA 4 0xB8001010 0x00000304
diff --git a/board/woodburn/lowlevel_init.S b/board/woodburn/lowlevel_init.S
new file mode 100644
index 0000000..e8f2dd3
--- /dev/null
+++ b/board/woodburn/lowlevel_init.S
@@ -0,0 +1,93 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm-offsets.h>
+#include <asm/arch/imx-regs.h>
+#include <generated/asm-offsets.h>
+
+/*
+ * Configuration for the flea3 board.
+ * These defines are used by the included macros and must
+ * be defined first
+ */
+#define AIPS_MPR_CONFIG		0x77777777
+#define AIPS_OPACR_CONFIG	0x00000000
+
+/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+#define MAX_MPR_CONFIG		0x00302154
+
+/* SGPCR - always park on last master */
+#define MAX_SGPCR_CONFIG	0x00000010
+
+/* MGPCR - restore default values */
+#define MAX_MGPCR_CONFIG	0x00000000
+
+/*
+ * M3IF Control Register (M3IFCTL)
+ * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
+ * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[2] = MBX not on priority list (0 << 0)   = 0x00000000
+ * MRRP[3] = MAX1 not on priority list (0 << 0)  = 0x00000000
+ * MRRP[4] = SDMA not on priority list (0 << 0)  = 0x00000000
+ * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
+ * MRRP[6] = IPU1 on priority list (1 << 6)      = 0x00000040
+ * MRRP[7] = IPU2 not on priority list (0 << 0)  = 0x00000000
+ *                                               ------------
+ *                                                 0x00000040
+ */
+#define M3IF_CONFIG		0x00000040
+
+#define CCM_PDR0_CONFIG		0x00801000
+
+/*
+ * includes MX35 utility macros
+ */
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/arch/lowlevel_macro.S>
+
+ENTRY(lowlevel_init)
+
+	/*
+	 * Setup a temporary stack
+	 */
+	ldr	sp, =LOW_LEVEL_SRAM_STACK
+
+	/*
+	 * Save the old lr(passed in ip) and the current lr to stack
+	 */
+	push	{ip, lr}
+
+	core_init
+
+	init_aips
+
+	init_max
+
+	init_m3if
+
+	bl board_early
+
+	pop	{ip, pc}
+ENDPROC(lowlevel_init)
diff --git a/board/woodburn/mx35_sdram.c b/board/woodburn/mx35_sdram.c
new file mode 100644
index 0000000..f7e682c
--- /dev/null
+++ b/board/woodburn/mx35_sdram.c
@@ -0,0 +1,137 @@
+/*
+ * Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <linux/types.h>
+#include <asm/arch/sys_proto.h>
+
+#define ESDCTL_DDR2_EMR2	0x04000000
+#define ESDCTL_DDR2_EMR3	0x06000000
+#define ESDCTL_PRECHARGE	0x00000400
+#define ESDCTL_DDR2_EN_DLL	0x02000400
+#define ESDCTL_DDR2_RESET_DLL	0x00000333
+#define ESDCTL_DDR2_MR		0x00000233
+#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
+
+enum {
+	SMODE_NORMAL =	0,
+	SMODE_PRECHARGE,
+	SMODE_AUTO_REFRESH,
+	SMODE_LOAD_REG,
+	SMODE_MANUAL_REFRESH
+};
+
+#define set_mode(x, en, m)	(x | (en << 31) | (m << 28))
+
+static inline void dram_wait(unsigned int count)
+{
+	volatile unsigned int wait = count;
+
+	while (wait--)
+		;
+
+}
+
+void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config,
+	u32 row, u32 col, u32 dsize, u32 refresh)
+{
+	struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
+	u32 *cfg_reg, *ctl_reg;
+	u32 val;
+	u32 ctlval;
+
+	switch (start_address) {
+	case CSD0_BASE_ADDR:
+		cfg_reg = &esdc->esdcfg0;
+		ctl_reg = &esdc->esdctl0;
+		break;
+	case CSD1_BASE_ADDR:
+		cfg_reg = &esdc->esdcfg1;
+		ctl_reg = &esdc->esdctl1;
+		break;
+	default:
+		return;
+	}
+
+	/* The MX35 supports 11 up to 14 rows */
+	if (row < 11 || row > 14 || col < 8 || col > 10)
+		return;
+	ctlval = (row - 11) << 24 | (col - 8) << 20 | (dsize << 16);
+
+	/* Initialize MISC register for DDR2 */
+	val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
+		ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
+	writel(val, &esdc->esdmisc);
+	val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
+	writel(val, &esdc->esdmisc);
+
+	/*
+	 * according to DDR2 specs, wait a while before
+	 * the PRECHARGE_ALL command
+	 */
+	dram_wait(0x20000);
+
+	/* Load DDR2 config and timing */
+	writel(ddr2_config, cfg_reg);
+
+	/* Precharge ALL */
+	writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
+		ctl_reg);
+	writel(0xda, start_address + ESDCTL_PRECHARGE);
+
+	/* Load mode */
+	writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
+		ctl_reg);
+	writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
+	writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
+	writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
+	writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
+
+	/* Precharge ALL */
+	writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
+		ctl_reg);
+	writel(0xda, start_address + ESDCTL_PRECHARGE);
+
+	/* Set mode auto refresh : at least two refresh are required */
+	writel(set_mode(ctlval, 1, SMODE_AUTO_REFRESH),
+		ctl_reg);
+	writel(0xda, start_address);
+	writel(0xda, start_address);
+
+	writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
+		ctl_reg);
+	writeb(0xda, start_address + ESDCTL_DDR2_MR);
+	writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
+
+	/* OCD mode exit */
+	writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
+
+	/* Set normal mode */
+	writel(set_mode(ctlval, 1, SMODE_NORMAL) | refresh,
+		ctl_reg);
+
+	dram_wait(0x20000);
+
+	/* Do not set delay lines, only for MDDR */
+}
diff --git a/board/woodburn/woodburn.c b/board/woodburn/woodburn.c
new file mode 100644
index 0000000..8068406
--- /dev/null
+++ b/board/woodburn/woodburn.c
@@ -0,0 +1,240 @@
+/*
+ * Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
+ *
+ * Based on flea3.c and mx35pdk.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx35_pins.h>
+#include <asm/arch/iomux.h>
+#include <i2c.h>
+#include <pmic.h>
+#include <fsl_pmic.h>
+#include <mc13892.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <linux/types.h>
+#include <asm/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <netdev.h>
+#include <spl.h>
+
+#define CCM_CCMR_CONFIG		0x003F4208
+
+#define ESDCTL_DDR2_CONFIG	0x007FFC3F
+
+/* For MMC */
+#define GPIO_MMC_CD	7
+#define GPIO_MMC_WP	8
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
+		PHYS_SDRAM_1_SIZE);
+
+	return 0;
+}
+
+#if defined(CONFIG_BOOT_INTERNAL) && \
+	!defined(CONFIG_SPL_BUILD)
+int board_early(void)
+{
+	return 0;
+}
+#else
+
+static void board_setup_sdram(void)
+{
+	struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
+
+	/* Initialize with default values both CSD0/1 */
+	writel(0x2000, &esdc->esdctl0);
+	writel(0x2000, &esdc->esdctl1);
+
+	mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG,
+		 13, 10, 2, 0x8080);
+}
+
+static void setup_iomux_fec(void)
+{
+	/* setup pins for FEC */
+	mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
+}
+
+int board_early(void)
+{
+	struct ccm_regs *ccm =
+		(struct ccm_regs *)IMX_CCM_BASE;
+
+	/* initialize PLL and clock configuration */
+	writel(CCM_CCMR_CONFIG, &ccm->ccmr);
+
+	/* Set-up RAM */
+	board_setup_sdram();
+
+	/* enable clocks */
+	writel(readl(&ccm->cgr0) |
+		MXC_CCM_CGR0_EMI_MASK |
+		MXC_CCM_CGR0_EDI0_MASK |
+		MXC_CCM_CGR0_EPIT1_MASK,
+		&ccm->cgr0);
+
+	writel(readl(&ccm->cgr1) |
+		MXC_CCM_CGR1_FEC_MASK |
+		MXC_CCM_CGR1_GPIO1_MASK |
+		MXC_CCM_CGR1_GPIO2_MASK |
+		MXC_CCM_CGR1_GPIO3_MASK |
+		MXC_CCM_CGR1_I2C1_MASK |
+		MXC_CCM_CGR1_I2C2_MASK |
+		MXC_CCM_CGR1_I2C3_MASK,
+		&ccm->cgr1);
+
+	/* Set-up NAND */
+	__raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
+
+	/* Set pinmux for the required peripherals */
+	setup_iomux_fec();
+
+#ifdef CONFIG_SPL_BUILD
+	preloader_console_init();
+	timer_init();
+#endif
+	/* setup GPIO1_4 FEC_ENABLE signal */
+	mxc_request_iomux(MX35_PIN_SCKR, MUX_CONFIG_ALT5);
+	gpio_direction_output(4, 1);
+	mxc_request_iomux(MX35_PIN_HCKT, MUX_CONFIG_ALT5);
+	gpio_direction_output(9, 0);
+	gpio_set_value(9, 1);
+
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	struct pmic *p;
+	u32 val;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	pmic_init();
+	p = get_pmic();
+
+	/*
+	 * Set switchers in Auto in NORMAL mode & STANDBY mode
+	 * Setup the switcher mode for SW1 & SW2
+	 */
+	pmic_reg_read(p, REG_SW_4, &val);
+	val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
+		(SWMODE_MASK << SWMODE2_SHIFT)));
+	val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
+		(SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
+	/* Set SWILIMB */
+	val |= (1 << 22);
+	pmic_reg_write(p, REG_SW_4, val);
+
+	/* Setup the switcher mode for SW3 & SW4 */
+	pmic_reg_read(p, REG_SW_5, &val);
+	val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
+		(SWMODE_MASK << SWMODE3_SHIFT));
+	val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
+		(SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
+	pmic_reg_write(p, REG_SW_5, val);
+
+	/* Set VGEN1 to 3.15V */
+	pmic_reg_read(p, REG_SETTING_0, &val);
+	val &= ~(VGEN1_MASK);
+	val |= VGEN1_3_15;
+	pmic_reg_write(p, REG_SETTING_0, val);
+
+	pmic_reg_read(p, REG_MODE_0, &val);
+	val |= VGEN1EN;
+	pmic_reg_write(p, REG_MODE_0, val);
+	udelay(2000);
+
+	return 0;
+}
+
+#if defined(CONFIG_FSL_ESDHC)
+struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR, 1};
+
+int board_mmc_init(bd_t *bis)
+{
+	/* configure pins for SDHC1 only */
+	mxc_request_iomux(MX35_PIN_SD1_CMD, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_SD1_CLK, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_SD1_DATA0, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_SD1_DATA1, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_SD1_DATA2, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_SD1_DATA3, MUX_CONFIG_FUNC);
+
+	/* MMC Card Detect on GPIO1_7 */
+	mxc_request_iomux(MX35_PIN_SCKT, MUX_CONFIG_ALT5);
+	mxc_iomux_set_input(MUX_IN_GPIO1_IN_7, 0x1);
+	gpio_direction_input(GPIO_MMC_CD);
+
+	mxc_request_iomux(MX35_PIN_FST, MUX_CONFIG_ALT5);
+	mxc_iomux_set_input(MUX_IN_GPIO1_IN_8, 0x1);
+	gpio_direction_output(GPIO_MMC_WP, 0);
+
+	return fsl_esdhc_initialize(bis, &esdhc_cfg);
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	return !gpio_get_value(GPIO_MMC_CD);
+}
+#endif
+
+void spl_board_init(void)
+{
+}
+
+u32 get_board_rev(void)
+{
+	int rev = 0;
+
+	return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
diff --git a/boards.cfg b/boards.cfg
index fdb84ad..a38d6d0 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -50,6 +50,8 @@ tt01                         arm         arm1136     -                   hale
 imx31_litekit                arm         arm1136     -                   logicpd        mx31
 flea3                        arm         arm1136     -                   CarMediaLab    mx35
 mx35pdk                      arm         arm1136     -                   freescale      mx35
+woodburn                     arm         arm1136     -                   -              mx35
+woodburn_sd                  arm         arm1136     woodburn            -              mx35        woodburn_sd:IMX_CONFIG=board/woodburn/imximage.cfg
 apollon			     arm	 arm1136     apollon		 -	        omap24xx
 omap2420h4                   arm         arm1136     -                   ti             omap24xx
 tnetv107x_evm                arm         arm1176     tnetv107xevm        ti             tnetv107x
diff --git a/include/configs/woodburn.h b/include/configs/woodburn.h
new file mode 100644
index 0000000..434c462
--- /dev/null
+++ b/include/configs/woodburn.h
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration for the woodburn board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include "woodburn_common.h"
+
+/* Set TEXT at the beginning of the NOR flash */
+#define CONFIG_SYS_TEXT_BASE	0xA0000000
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h
new file mode 100644
index 0000000..48688d7
--- /dev/null
+++ b/include/configs/woodburn_common.h
@@ -0,0 +1,322 @@
+/*
+ * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration for the woodburn board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __WOODBURN_COMMON_CONFIG_H
+#define __WOODBURN_COMMON_CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136	/* This is an arm1136 CPU core */
+#define CONFIG_MX35
+#define CONFIG_MX35_HCLK_FREQ	24000000
+
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
+#define CONFIG_DISPLAY_CPUINFO
+
+/* Only in case the value is not present in mach-types.h */
+#ifndef MACH_TYPE_FLEA3
+#define MACH_TYPE_FLEA3                3668
+#endif
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_FLEA3
+
+/* This is required to setup the ESDC controller */
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_BASE		I2C1_BASE_ADDR
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_MXC_SPI
+#define CONFIG_MXC_GPIO
+
+/* PMIC Controller */
+#define CONFIG_PMIC
+#define CONFIG_PMIC_I2C
+#define CONFIG_MC13892_PMIC
+#define CONFIG_PMIC_FSL
+#define CONFIG_SYS_FSL_PMIC_I2C_ADDR	0x8
+#define CONFIG_RTC_MC13XXX
+
+
+/* mmc driver */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_NUM	1
+
+/*
+ * UART (console)
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART1_BASE
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		115200
+
+/*
+ * Command definition
+ */
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_CACHE
+
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+
+#define CONFIG_CMD_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+
+#define CONFIG_CMD_GPIO
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_NET_RETRY_COUNT	100
+
+#define CONFIG_BOOTDELAY	3
+
+#define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */
+
+
+/*
+ * Ethernet on SOC (FEC)
+ */
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE	FEC_BASE_ADDR
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_FEC_MXC_PHYADDR	0x1
+
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+
+#define CONFIG_ARP_TIMEOUT	200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP	/* undef to save memory */
+#define CONFIG_SYS_PROMPT	"woodburn U-Boot > "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER	/* Use the HUSH parser */
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START	0	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x10000
+
+#undef	CONFIG_SYS_CLKS_IN_HZ	/* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ				1000
+
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 * 1024)	/* regular stack */
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM_1		CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE	(256 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		CSD0_BASE_ADDR
+#if 0
+#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR + 0x10000)
+#define CONFIG_SYS_INIT_RAM_SIZE		(IRAM_SIZE / 2)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					CONFIG_SYS_GBL_DATA_OFFSET)
+#else
+#define CONFIG_SYS_GBL_DATA_OFFSET	(LOW_LEVEL_SRAM_STACK - \
+						IRAM_BASE_ADDR - \
+						GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR		(IRAM_BASE_ADDR + \
+					CONFIG_SYS_GBL_DATA_OFFSET)
+#endif
+
+
+/*
+ * MTD Command for mtdparts
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT		"nand0=mxc_nand,nor0=physmap-flash.0"
+#define MTDPARTS_DEFAULT	"mtdparts=mxc_nand:50m(root1)," \
+				"32m(rootfb)," \
+				"64m(pcache)," \
+				"64m(app1)," \
+				"10m(app2),-(spool);" \
+				"physmap-flash.0:512k(u-boot),64k(env1)," \
+				"64k(env2),3776k(kernel1),3776k(kernel2)"
+
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_BASE		CS0_BASE_ADDR
+#define CONFIG_SYS_MAX_FLASH_BANKS 1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512	/* max number of sectors on one chip */
+/* Monitor at beginning of flash */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+
+#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
+				CONFIG_SYS_MONITOR_LEN)
+
+#define CONFIG_ENV_IS_IN_FLASH
+
+/*
+ * CFI FLASH driver setup
+ */
+#define CONFIG_SYS_FLASH_CFI		/* Flash memory is CFI compliant */
+#define CONFIG_FLASH_CFI_DRIVER
+
+/* A non-standard buffered write algorithm */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* faster */
+#define CONFIG_SYS_FLASH_PROTECTION	/* Use hardware sector protection */
+
+/*
+ * NAND FLASH driver setup
+ */
+#define CONFIG_NAND_MXC
+#define CONFIG_NAND_MXC_V1_1
+#define CONFIG_MXC_NAND_REGS_BASE	(NFC_BASE_ADDR)
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		(NFC_BASE_ADDR)
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_LARGEPAGE
+
+#if 0
+#define CONFIG_MTD_DEBUG
+#define CONFIG_MTD_DEBUG_VERBOSE	7
+#endif
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/*
+ * Default environment and default scripts
+ * to update uboot and load kernel
+ */
+#define xstr(s)	str(s)
+#define str(s)	#s
+
+#define CONFIG_HOSTNAME woodburn
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip_sta=setenv bootargs ${bootargs} "			\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
+	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
+		"else run addip_sta;fi\0"	\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"addtty=setenv bootargs ${bootargs}"				\
+		" console=ttymxc0,${baudrate}\0"			\
+	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
+	"loadaddr=80800000\0"						\
+	"kernel_addr_r=80800000\0"					\
+	"hostname=" xstr(CONFIG_HOSTNAME) "\0"				\
+	"bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0"			\
+	"ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0"		\
+	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr}\0"				\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
+		"run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr_r}\0"				\
+	"net_self_load=tftp ${kernel_addr_r} ${bootfile};"		\
+		"tftp ${ramdisk_addr_r} ${ramdisk_file};\0"		\
+	"net_self=if run net_self_load;then "				\
+		"run ramargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr_r} ${ramdisk_addr_r};"		\
+		"else echo Images not loades;fi\0"			\
+	"u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0"			\
+	"load=tftp ${loadaddr} ${u-boot}\0"				\
+	"uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0"		\
+	"update=protect off ${uboot_addr} +80000;"			\
+		"erase ${uboot_addr} +80000;"				\
+		"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0"		\
+	"upd=if run load;then echo Updating u-boot;if run update;"	\
+		"then echo U-Boot updated;"				\
+			"else echo Error updating u-boot !;"		\
+			"echo Board without bootloader !!;"		\
+		"fi;"							\
+		"else echo U-Boot not downloaded..exiting;fi\0"		\
+	"bootcmd=run net_nfs\0"
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/woodburn_sd.h b/include/configs/woodburn_sd.h
new file mode 100644
index 0000000..7b7c259
--- /dev/null
+++ b/include/configs/woodburn_sd.h
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration for the woodburn board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include "woodburn_common.h"
+
+/* Set TEXT in RAM */
+#define CONFIG_SYS_TEXT_BASE	0x82000000
+
+#define CONFIG_BOOT_INTERNAL
+
+/*
+ * SPL
+ */
+#define	CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define	CONFIG_SPL_LDSCRIPT	"arch/arm/cpu/arm1136/u-boot-spl.lds"
+#define	CONFIG_SPL_LIBCOMMON_SUPPORT
+#define	CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x100 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x400 /* 512 KB */
+#define	CONFIG_SPL_GPIO_SUPPORT
+#if 0
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME        "u-boot.bin"
+#endif
+
+#define CONFIG_SPL_TEXT_BASE		0x10002300
+#define CONFIG_SPL_MAX_SIZE		(64 * 1024)	/* 8 KB for stack */
+#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SYS_SPL_MALLOC_START	0x8f000000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
+#define CONFIG_SPL_BSS_START_ADDR	0x8f080000 /* end of RAM */
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+
+#endif				/* __CONFIG_H */
-- 
1.7.9.5

[U-Boot] [NEXT PATCH v1 5/7] SPL: Added MLO for mx35 SOC to SPL Makefile

[Tom Rini]

On 09/06/2012 01:04 AM, Stefano Babic wrote:
> Signed-off-by: Stefano Babic <sbabic@denx.de>
> ---
>  spl/Makefile |    6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/spl/Makefile b/spl/Makefile
> index f96c08e..77fc405 100644
> --- a/spl/Makefile
> +++ b/spl/Makefile
> @@ -109,6 +109,12 @@ $(OBJTREE)/MLO:	$(obj)u-boot-spl.bin
>  		-a $(CONFIG_SPL_TEXT_BASE) -d $< $@
>  endif
>  
> +ifneq ($(CONFIG_IMX_CONFIG),)
> +$(OBJTREE)/MLO:	$(obj)u-boot-spl.bin
> +	$(OBJTREE)/tools/mkimage -n  $(SRCTREE)/$(CONFIG_IMX_CONFIG) -T imximage \
> +		-e $(CONFIG_SPL_TEXT_BASE) -d $< $@
> +endif
> +
>  ALL-y	+= $(obj)u-boot-spl.bin
>  
>  ifdef CONFIG_SAMSUNG

Is that really the name you want?  MLO comes from some part or another
(I've read it, just can't recall off-hand) of the IT ROM docs saying it
will read a file named MLO.  Is mx35 in the same boat?  Or just looking
for a common name?  Thanks!

-- 
Tom

[U-Boot] [NEXT PATCH v1 5/7] SPL: Added MLO for mx35 SOC to SPL Makefile

[Stefano Babic]

On 06/09/2012 19:49, Tom Rini wrote:
> On 09/06/2012 01:04 AM, Stefano Babic wrote:
>> Signed-off-by: Stefano Babic <sbabic@denx.de>
>> ---
>>  spl/Makefile |    6 ++++++
>>  1 file changed, 6 insertions(+)
>>
>> diff --git a/spl/Makefile b/spl/Makefile
>> index f96c08e..77fc405 100644
>> --- a/spl/Makefile
>> +++ b/spl/Makefile
>> @@ -109,6 +109,12 @@ $(OBJTREE)/MLO:	$(obj)u-boot-spl.bin
>>  		-a $(CONFIG_SPL_TEXT_BASE) -d $< $@
>>  endif
>>  
>> +ifneq ($(CONFIG_IMX_CONFIG),)
>> +$(OBJTREE)/MLO:	$(obj)u-boot-spl.bin
>> +	$(OBJTREE)/tools/mkimage -n  $(SRCTREE)/$(CONFIG_IMX_CONFIG) -T imximage \
>> +		-e $(CONFIG_SPL_TEXT_BASE) -d $< $@
>> +endif
>> +
>>  ALL-y	+= $(obj)u-boot-spl.bin
>>  
>>  ifdef CONFIG_SAMSUNG
> 
> Is that really the name you want?  MLO comes from some part or another
> (I've read it, just can't recall off-hand) of the IT ROM docs saying it
> will read a file named MLO.

I know...

>  Is mx35 in the same boat?
>  Or just looking
> for a common name?  

Right. It makes no sense that the binary for Freescale's SOCs has a
name, for TI another one, for...we can generates less confusion if we
uses the same name.

Stefano

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [NEXT PATCH v1 5/7] SPL: Added MLO for mx35 SOC to SPL Makefile

[Tom Rini]

On 09/06/2012 12:59 PM, Stefano Babic wrote:
> On 06/09/2012 19:49, Tom Rini wrote:
>> On 09/06/2012 01:04 AM, Stefano Babic wrote:
>>> Signed-off-by: Stefano Babic <sbabic@denx.de>
>>> ---
>>>  spl/Makefile |    6 ++++++
>>>  1 file changed, 6 insertions(+)
>>>
>>> diff --git a/spl/Makefile b/spl/Makefile
>>> index f96c08e..77fc405 100644
>>> --- a/spl/Makefile
>>> +++ b/spl/Makefile
>>> @@ -109,6 +109,12 @@ $(OBJTREE)/MLO:	$(obj)u-boot-spl.bin
>>>  		-a $(CONFIG_SPL_TEXT_BASE) -d $< $@
>>>  endif
>>>  
>>> +ifneq ($(CONFIG_IMX_CONFIG),)
>>> +$(OBJTREE)/MLO:	$(obj)u-boot-spl.bin
>>> +	$(OBJTREE)/tools/mkimage -n  $(SRCTREE)/$(CONFIG_IMX_CONFIG) -T imximage \
>>> +		-e $(CONFIG_SPL_TEXT_BASE) -d $< $@
>>> +endif
>>> +
>>>  ALL-y	+= $(obj)u-boot-spl.bin
>>>  
>>>  ifdef CONFIG_SAMSUNG
>>
>> Is that really the name you want?  MLO comes from some part or another
>> (I've read it, just can't recall off-hand) of the IT ROM docs saying it
>> will read a file named MLO.
> 
> I know...
> 
>>  Is mx35 in the same boat?
>>  Or just looking
>> for a common name?  
> 
> Right. It makes no sense that the binary for Freescale's SOCs has a
> name, for TI another one, for...we can generates less confusion if we
> uses the same name.

Agreed.  I guess what I'm asking is, in the TI case the ROM reads FAT
and must find 'MLO'.  Does mx35 do the same or is the post-build step
"dd if=MLO of=/dev/... ..." and the filename doesn't matter?  I'm fine
with the change now, just looking for the full details.  Thanks!

-- 
Tom

[U-Boot] [NEXT PATCH v1 5/7] SPL: Added MLO for mx35 SOC to SPL Makefile

[stefano babic]

Am 06/09/2012 22:48, schrieb Tom Rini:
> On 09/06/2012 12:59 PM, Stefano Babic wrote:
>> On 06/09/2012 19:49, Tom Rini wrote:
>>> On 09/06/2012 01:04 AM, Stefano Babic wrote:
>>>> Signed-off-by: Stefano Babic <sbabic@denx.de>
>>>> ---
>>>>  spl/Makefile |    6 ++++++
>>>>  1 file changed, 6 insertions(+)
>>>>
>>>> diff --git a/spl/Makefile b/spl/Makefile
>>>> index f96c08e..77fc405 100644
>>>> --- a/spl/Makefile
>>>> +++ b/spl/Makefile
>>>> @@ -109,6 +109,12 @@ $(OBJTREE)/MLO:	$(obj)u-boot-spl.bin
>>>>  		-a $(CONFIG_SPL_TEXT_BASE) -d $< $@
>>>>  endif
>>>>  
>>>> +ifneq ($(CONFIG_IMX_CONFIG),)
>>>> +$(OBJTREE)/MLO:	$(obj)u-boot-spl.bin
>>>> +	$(OBJTREE)/tools/mkimage -n  $(SRCTREE)/$(CONFIG_IMX_CONFIG) -T imximage \
>>>> +		-e $(CONFIG_SPL_TEXT_BASE) -d $< $@
>>>> +endif
>>>> +
>>>>  ALL-y	+= $(obj)u-boot-spl.bin
>>>>  
>>>>  ifdef CONFIG_SAMSUNG
>>>
>>> Is that really the name you want?  MLO comes from some part or another
>>> (I've read it, just can3't recall off-hand) of the IT ROM docs saying it
>>> will read a file named MLO.
>>
>> I know...
>>
>>>  Is mx35 in the same boat?
>>>  Or just looking
>>> for a common name?  
>>
>> Right. It makes no sense that the binary for Freescale's SOCs has a
>> name, for TI another one, for...we can generates less confusion if we
>> uses the same name.
> 
> Agreed.  I guess what I'm asking is, in the TI case the ROM reads FAT
> and must find 'MLO'.  Does mx35 do the same or

No. And not only the MX35, but also the MX5/MX6.

> is the post-build step
> "dd if=MLO of=/dev/... ..." and the filename doesn't matter?

Exactly. The ROM does not understand a filesystem, and the SPL must be
stored at a fixed address in the SD card. The filename does not matter,
and the SPL is not seen as file, but as a raw image.

>  I'm fine
> with the change now, just looking for the full details.  Thanks!

As for Freescale the filename does not matter while for TI does, we can
use for both MLO ;-)

Stefano

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [NEXT PATCH v1 2/7] NAND: added NAND type to nand_ids

[Scott Wood]

On 09/06/2012 03:04 AM, Stefano Babic wrote:
> Signed-off-by: Stefano Babic <sbabic@denx.de>
> ---
>  drivers/mtd/nand/nand_ids.c |    2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
> index 3953549..fe75686 100644
> --- a/drivers/mtd/nand/nand_ids.c
> +++ b/drivers/mtd/nand/nand_ids.c
> @@ -131,6 +131,8 @@ const struct nand_flash_dev nand_flash_ids[] = {
>  	/* 128 Gigabit */
>  	{"NAND 16GiB 1,8V 8-bit",	0x1A, 0, 16384, 0, LP_OPTIONS},
>  	{"NAND 16GiB 3,3V 8-bit",	0x3A, 0, 16384, 0, LP_OPTIONS},
> +	{"NAND 16GiB 3,3V 8-bit",	0x48, 4096, 16384, 0x100000,
> +		LP_OPTIONS},
>  	{"NAND 16GiB 1,8V 16-bit",	0x2A, 0, 16384, 0, LP_OPTIONS16},
>  	{"NAND 16GiB 3,3V 16-bit",	0x4A, 0, 16384, 0, LP_OPTIONS16},
>  
> 

Why does this NAND chip need things specified that are zeroes for other
chips?

-Scott

[U-Boot] [NEXT PATCH v1 2/7] NAND: added NAND type to nand_ids

[Stefano Babic]

On 07/09/2012 01:19, Scott Wood wrote:
> On 09/06/2012 03:04 AM, Stefano Babic wrote:
>> Signed-off-by: Stefano Babic <sbabic@denx.de>
>> ---

Hi Scott,

>>  drivers/mtd/nand/nand_ids.c |    2 ++
>>  1 file changed, 2 insertions(+)
>>
>> diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
>> index 3953549..fe75686 100644
>> --- a/drivers/mtd/nand/nand_ids.c
>> +++ b/drivers/mtd/nand/nand_ids.c
>> @@ -131,6 +131,8 @@ const struct nand_flash_dev nand_flash_ids[] = {
>>  	/* 128 Gigabit */
>>  	{"NAND 16GiB 1,8V 8-bit",	0x1A, 0, 16384, 0, LP_OPTIONS},
>>  	{"NAND 16GiB 3,3V 8-bit",	0x3A, 0, 16384, 0, LP_OPTIONS},
>> +	{"NAND 16GiB 3,3V 8-bit",	0x48, 4096, 16384, 0x100000,
>> +		LP_OPTIONS},
>>  	{"NAND 16GiB 1,8V 16-bit",	0x2A, 0, 16384, 0, LP_OPTIONS16},
>>  	{"NAND 16GiB 3,3V 16-bit",	0x4A, 0, 16384, 0, LP_OPTIONS16},
>>  
>>
> 
> Why does this NAND chip need things specified that are zeroes for other
> chips?

At least on this board with MX35, the chip cannot be recognized.
Manufacturer ID and device ID are read flawlessly, but then u-boot fails
to get the correct geometry. Setting explicitely the values, I can then
read / write into the NAND without any problem. It can be more a problem
related to the specific MXC NAND driver (mxc_nand.c).

Regards,
Stefano


-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [NEXT PATCH v1 2/7] NAND: added NAND type to nand_ids

[Stefano Babic]

On 07/09/2012 11:12, Stefano Babic wrote:
> On 07/09/2012 01:19, Scott Wood wrote:
>> On 09/06/2012 03:04 AM, Stefano Babic wrote:
>>> Signed-off-by: Stefano Babic <sbabic@denx.de>
>>> ---
> 
> Hi Scott,
> 
>>>  drivers/mtd/nand/nand_ids.c |    2 ++
>>>  1 file changed, 2 insertions(+)
>>>
>>> diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
>>> index 3953549..fe75686 100644
>>> --- a/drivers/mtd/nand/nand_ids.c
>>> +++ b/drivers/mtd/nand/nand_ids.c
>>> @@ -131,6 +131,8 @@ const struct nand_flash_dev nand_flash_ids[] = {
>>>  	/* 128 Gigabit */
>>>  	{"NAND 16GiB 1,8V 8-bit",	0x1A, 0, 16384, 0, LP_OPTIONS},
>>>  	{"NAND 16GiB 3,3V 8-bit",	0x3A, 0, 16384, 0, LP_OPTIONS},
>>> +	{"NAND 16GiB 3,3V 8-bit",	0x48, 4096, 16384, 0x100000,
>>> +		LP_OPTIONS},
>>>  	{"NAND 16GiB 1,8V 16-bit",	0x2A, 0, 16384, 0, LP_OPTIONS16},
>>>  	{"NAND 16GiB 3,3V 16-bit",	0x4A, 0, 16384, 0, LP_OPTIONS16},
>>>  
>>>
>>
>> Why does this NAND chip need things specified that are zeroes for other
>> chips?
> 
> At least on this board with MX35, the chip cannot be recognized.
> Manufacturer ID and device ID are read flawlessly, but then u-boot fails
> to get the correct geometry. Setting explicitely the values, I can then
> read / write into the NAND without any problem. It can be more a problem
> related to the specific MXC NAND driver (mxc_nand.c).

It seems to me that the values returned by this flash cannot be
interpreted in nand_get_flash_type().

The values returned from a READ-ID command with address 0x00 are:

	0x2C 0x48 0x04 0x4A 0xA5,

I can really get these values from the flash, so the MXC controller gets
the correct data.

However, the code in nand_base.c (lines from 2718, so not-Samsung case)
parses the answer setting the NAND as a 16-bit device, but this is
really a 8bit device. I do not know the meaning of the answer, it is not
described in the datasheet.

Cheers,
Stefano

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [NEXT PATCH v1 2/7] NAND: added NAND type to nand_ids

[Scott Wood]

On 09/07/2012 10:23 AM, Stefano Babic wrote:
> On 07/09/2012 11:12, Stefano Babic wrote:
>> On 07/09/2012 01:19, Scott Wood wrote:
>>> On 09/06/2012 03:04 AM, Stefano Babic wrote:
>>>> Signed-off-by: Stefano Babic <sbabic@denx.de>
>>>> ---
>>
>> Hi Scott,
>>
>>>>  drivers/mtd/nand/nand_ids.c |    2 ++
>>>>  1 file changed, 2 insertions(+)
>>>>
>>>> diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
>>>> index 3953549..fe75686 100644
>>>> --- a/drivers/mtd/nand/nand_ids.c
>>>> +++ b/drivers/mtd/nand/nand_ids.c
>>>> @@ -131,6 +131,8 @@ const struct nand_flash_dev nand_flash_ids[] = {
>>>>  	/* 128 Gigabit */
>>>>  	{"NAND 16GiB 1,8V 8-bit",	0x1A, 0, 16384, 0, LP_OPTIONS},
>>>>  	{"NAND 16GiB 3,3V 8-bit",	0x3A, 0, 16384, 0, LP_OPTIONS},
>>>> +	{"NAND 16GiB 3,3V 8-bit",	0x48, 4096, 16384, 0x100000,
>>>> +		LP_OPTIONS},
>>>>  	{"NAND 16GiB 1,8V 16-bit",	0x2A, 0, 16384, 0, LP_OPTIONS16},
>>>>  	{"NAND 16GiB 3,3V 16-bit",	0x4A, 0, 16384, 0, LP_OPTIONS16},
>>>>  
>>>>
>>>
>>> Why does this NAND chip need things specified that are zeroes for other
>>> chips?
>>
>> At least on this board with MX35, the chip cannot be recognized.
>> Manufacturer ID and device ID are read flawlessly, but then u-boot fails
>> to get the correct geometry. Setting explicitely the values, I can then
>> read / write into the NAND without any problem. It can be more a problem
>> related to the specific MXC NAND driver (mxc_nand.c).
> 
> It seems to me that the values returned by this flash cannot be
> interpreted in nand_get_flash_type().
> 
> The values returned from a READ-ID command with address 0x00 are:
> 
> 	0x2C 0x48 0x04 0x4A 0xA5,
> 
> I can really get these values from the flash, so the MXC controller gets
> the correct data.
>
> However, the code in nand_base.c (lines from 2718, so not-Samsung case)
> parses the answer setting the NAND as a 16-bit device, but this is
> really a 8bit device. I do not know the meaning of the answer, it is not
> described in the datasheet.

Does the datasheet say anything about what the ID data is supposed to
look like and how to interpret it?  I tried to download it and Micron
shoved an NDA in my face.

What kind of chip is this?  Is the datasheet publicly available?

These threads seem relevant:
http://patchwork.ozlabs.org/patch/60042/
http://old.nabble.com/-U-Boot--Add-new-NAND-flash-td29858370.html

Does the chip support ONFI?

-Scott

[U-Boot] [NEXT PATCH v1 2/7] NAND: added NAND type to nand_ids

[Stefano Babic]

On 07/09/2012 20:56, Scott Wood wrote:

Hi Scott,

>>>
>>>>>  drivers/mtd/nand/nand_ids.c |    2 ++
>>>>>  1 file changed, 2 insertions(+)
>>>>>
>>>>> diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
>>>>> index 3953549..fe75686 100644
>>>>> --- a/drivers/mtd/nand/nand_ids.c
>>>>> +++ b/drivers/mtd/nand/nand_ids.c
>>>>> @@ -131,6 +131,8 @@ const struct nand_flash_dev nand_flash_ids[] = {
>>>>>  	/* 128 Gigabit */
>>>>>  	{"NAND 16GiB 1,8V 8-bit",	0x1A, 0, 16384, 0, LP_OPTIONS},
>>>>>  	{"NAND 16GiB 3,3V 8-bit",	0x3A, 0, 16384, 0, LP_OPTIONS},
>>>>> +	{"NAND 16GiB 3,3V 8-bit",	0x48, 4096, 16384, 0x100000,
>>>>> +		LP_OPTIONS},
>>>>>  	{"NAND 16GiB 1,8V 16-bit",	0x2A, 0, 16384, 0, LP_OPTIONS16},
>>>>>  	{"NAND 16GiB 3,3V 16-bit",	0x4A, 0, 16384, 0, LP_OPTIONS16},
>>>>>  
>>>>>
>>>>
>>>> Why does this NAND chip need things specified that are zeroes for other
>>>> chips?
>>>
>>> At least on this board with MX35, the chip cannot be recognized.
>>> Manufacturer ID and device ID are read flawlessly, but then u-boot fails
>>> to get the correct geometry. Setting explicitely the values, I can then
>>> read / write into the NAND without any problem. It can be more a problem
>>> related to the specific MXC NAND driver (mxc_nand.c).
>>
>> It seems to me that the values returned by this flash cannot be
>> interpreted in nand_get_flash_type().
>>
>> The values returned from a READ-ID command with address 0x00 are:
>>
>> 	0x2C 0x48 0x04 0x4A 0xA5,
>>
>> I can really get these values from the flash, so the MXC controller gets
>> the correct data.
>>
>> However, the code in nand_base.c (lines from 2718, so not-Samsung case)
>> parses the answer setting the NAND as a 16-bit device, but this is
>> really a 8bit device. I do not know the meaning of the answer, it is not
>> described in the datasheet.
> 
> Does the datasheet say anything about what the ID data is supposed to
> look like and how to interpret it?  I tried to download it and Micron
> shoved an NDA in my face.

I find no description in the datasheet.

> 
> What kind of chip is this?  Is the datasheet publicly available?
> 
> These threads seem relevant:
> http://patchwork.ozlabs.org/patch/60042/
> http://old.nabble.com/-U-Boot--Add-new-NAND-flash-td29858370.html

It is the same case,  as I can see, with the same chip.

> 
> Does the chip support ONFI?

The chip supports ONFI, but it seems the i.MX driver does not. Quite as
described in http://patchwork.ozlabs.org/patch/60042/. READ-ID is always
sent with address 0, I do not know if we can convince the driver to send
the address.

Regards,
Stefano

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [NEXT PATCH v1 5/7] SPL: Added MLO for mx35 SOC to SPL Makefile

[Thomas Petazzoni]

Hello,

Le Thu, 06 Sep 2012 23:57:08 +0200,
stefano babic <sbabic@denx.de> a ?crit :

> > Agreed.  I guess what I'm asking is, in the TI case the ROM reads FAT
> > and must find 'MLO'.  Does mx35 do the same or
> 
> No. And not only the MX35, but also the MX5/MX6.
> 
> > is the post-build step
> > "dd if=MLO of=/dev/... ..." and the filename doesn't matter?
> 
> Exactly. The ROM does not understand a filesystem, and the SPL must be
> stored at a fixed address in the SD card. The filename does not matter,
> and the SPL is not seen as file, but as a raw image.
> 
> >  I'm fine
> > with the change now, just looking for the full details.  Thanks!
> 
> As for Freescale the filename does not matter while for TI does, we can
> use for both MLO ;-)

Then in that case I would precisely *not* use the same filename, in
order to make it clear that Freescale SPL cannot be used in the same
way as the TI SPL. Naming it MLO will certainly confuse users having
previous experience with TI stuff: it will lead them to believe that
creating a FAT filesystem and putting the MLO file in it will be the
necessary steps to get this SPL loaded by the ROM code.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[U-Boot] [NEXT PATCH v1 5/7] SPL: Added MLO for mx35 SOC to SPL Makefile

[Stefano Babic]

On 10/09/2012 14:27, Thomas Petazzoni wrote:
> Hello,
> 

Hi Thomas,

>> Exactly. The ROM does not understand a filesystem, and the SPL must be
>> stored at a fixed address in the SD card. The filename does not matter,
>> and the SPL is not seen as file, but as a raw image.
>>
>>>  I'm fine
>>> with the change now, just looking for the full details.  Thanks!
>>
>> As for Freescale the filename does not matter while for TI does, we can
>> use for both MLO ;-)
> 
> Then in that case I would precisely *not* use the same filename, in
> order to make it clear that Freescale SPL cannot be used in the same
> way as the TI SPL. Naming it MLO will certainly confuse users having
> previous experience with TI stuff: it will lead them to believe that
> creating a FAT filesystem and putting the MLO file in it will be the
> necessary steps to get this SPL loaded by the ROM code.

Of couse, setting a common name is not a reason enough for the users to
not read the manual ;-). The way TI and Freescale have chosen to boot
their SOCs are and remain quite differently.

The reason to have a common name is to avoid to document for each SOC
which is the binary result. Maybe a more neutral name as "SPL" instead
of "MLO" ? This is the first attempt to set SPL for a not-TI SOC, but
hopefully other SOCs will follow, and it is better to set already some
simple rules,

In any case, the resulting binary is a different thing as how to put the
binary into the target: SPL can be copied as MLO on the SD-Card. Tom,
what do you think ?

Best regards,
Stefano

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [NEXT PATCH v1 5/7] SPL: Added MLO for mx35 SOC to SPL Makefile

[Tom Rini]

On Mon, Sep 10, 2012 at 5:44 AM, Stefano Babic <sbabic@denx.de> wrote:
> On 10/09/2012 14:27, Thomas Petazzoni wrote:
>> Hello,
>>
>
> Hi Thomas,
>
>>> Exactly. The ROM does not understand a filesystem, and the SPL must be
>>> stored at a fixed address in the SD card. The filename does not matter,
>>> and the SPL is not seen as file, but as a raw image.
>>>
>>>>  I'm fine
>>>> with the change now, just looking for the full details.  Thanks!
>>>
>>> As for Freescale the filename does not matter while for TI does, we can
>>> use for both MLO ;-)
>>
>> Then in that case I would precisely *not* use the same filename, in
>> order to make it clear that Freescale SPL cannot be used in the same
>> way as the TI SPL. Naming it MLO will certainly confuse users having
>> previous experience with TI stuff: it will lead them to believe that
>> creating a FAT filesystem and putting the MLO file in it will be the
>> necessary steps to get this SPL loaded by the ROM code.
>
> Of couse, setting a common name is not a reason enough for the users to
> not read the manual ;-). The way TI and Freescale have chosen to boot
> their SOCs are and remain quite differently.
>
> The reason to have a common name is to avoid to document for each SOC
> which is the binary result. Maybe a more neutral name as "SPL" instead
> of "MLO" ? This is the first attempt to set SPL for a not-TI SOC, but
> hopefully other SOCs will follow, and it is better to set already some
> simple rules,
>
> In any case, the resulting binary is a different thing as how to put the
> binary into the target: SPL can be copied as MLO on the SD-Card. Tom,
> what do you think ?

I think Thomas raises a good point.  The important thing is that 'make
fooboard' produces everything to boot the board (when possible).  But
at the end of the day, it comes down to the user needs to understand
how to boot their board.  The TI MLO file can be dd'ed to an SD card
and booted too, for example.

-- 
Tom

[U-Boot] [NEXT PATCH v1 2/7] NAND: added NAND type to nand_ids

[Scott Wood]

On 09/10/2012 07:09 AM, Stefano Babic wrote:
> On 07/09/2012 20:56, Scott Wood wrote:
>> What kind of chip is this?  Is the datasheet publicly available?
>>
>> These threads seem relevant:
>> http://patchwork.ozlabs.org/patch/60042/
>> http://old.nabble.com/-U-Boot--Add-new-NAND-flash-td29858370.html
> 
> It is the same case,  as I can see, with the same chip.
> 
>>
>> Does the chip support ONFI?
> 
> The chip supports ONFI, but it seems the i.MX driver does not. Quite as
> described in http://patchwork.ozlabs.org/patch/60042/. READ-ID is always
> sent with address 0, I do not know if we can convince the driver to send
> the address.

How did Linux end up resolving this?  I think it'd be better to have the
Micron decoding logic from that patch, than to introduce a special
addition to the ID table for this one chip, which might not be correct
for all chips with that ID byte.

Or, we could treat it as information to be supplied by platform code (or
the device tree).

-Scott

[U-Boot] [NEXT PATCH v1 2/7] NAND: added NAND type to nand_ids

[Eric Bénard]

Hi Stefano,

Le Mon, 10 Sep 2012 14:09:21 +0200,
Stefano Babic <sbabic@denx.de> a ?crit :
> The chip supports ONFI, but it seems the i.MX driver does not. Quite as
> described in http://patchwork.ozlabs.org/patch/60042/. READ-ID is always
> sent with address 0, I do not know if we can convince the driver to send
> the address.

to add ONFI support to i.MX's driver, you can check this patch (in
barebox, a similar patch for Linux is cooking, actually tested on
i.MX53 and i.MX25) :
http://git.pengutronix.de/?p=barebox.git;a=commit;h=632c45795065e6a7471ab82be38e808eb6204341

Eric

[U-Boot] [NEXT PATCH v1 4/7] MX35: Add soc_boot_mode and soc_boot_device to MX35

[Eric Bénard]

Hi Stefano,

Le Thu,  6 Sep 2012 10:04:57 +0200,
Stefano Babic <sbabic@denx.de> a ?crit :
> +#define RCSR_MEM_CTL_WEIM	0
> +#define RCSR_MEM_CTL_NAND	1
> +#define RCSR_MEM_CTL_SD		2
> +#define RCSR_MEM_TYPE_NOR	0
> +#define RCSR_MEM_TYPE_ONENAND	2
> +#define RCSR_MEM_TYPE_SD	0
> +#define RCSR_MEM_TYPE_I2C	2
> +#define RCSR_MEM_TYPE_SPI	3
> +
> +u32 spl_boot_device(void)
> +{
> +	puts("spl_boot_device\n");
> +	struct ccm_regs *ccm =
> +		(struct ccm_regs *)IMX_CCM_BASE;
> +
> +#if 1
> +	return BOOT_DEVICE_MMC1;
> +#endif

thisseems not clean and seems caused by the fact that the define
RCSR_MEM_CTL_SD should be 3 and not 2 so in your tests the function
spl_boot_device was not detecting the right boot mode. Also IMHO this
define should be named RCSR_MEM_CTL_EXPANSION as in the app note AN3996
at end of page 3 (there is a typo in the reference manual which seems
to be a copy'n paste from i.MX25 as it doesn't take in acount the ATA
HDD case) :
http://cache.freescale.com/files/dsp/doc/app_note/AN3996.pdf

> +
> +	u32 rcsr = readl(&ccm->rcsr);
> +	u32 mem_type, mem_ctl;
> +
> +	/* In external mode, no boot device is returned */
> +	if ((rcsr >> 10) & 0x03)
> +		return BOOT_DEVICE_NONE;
> +
> +	mem_ctl = (rcsr >> 25) & 0x03;
> +	mem_type = (rcsr >> 23) & 0x03;
> +
> +	switch (mem_ctl) {
> +	case RCSR_MEM_CTL_WEIM:
> +		switch (mem_type) {
> +		case RCSR_MEM_TYPE_NOR:
> +			return BOOT_DEVICE_NOR;
> +		case RCSR_MEM_TYPE_ONENAND:
> +			return BOOT_DEVICE_ONE_NAND;
> +		default:
> +			return BOOT_DEVICE_NONE;
> +		}
> +	case RCSR_MEM_CTL_NAND:
> +		return BOOT_DEVICE_NAND;
> +	case RCSR_MEM_CTL_SD:
> +		switch (mem_type) {
> +		case RCSR_MEM_TYPE_SD:
> +			return BOOT_DEVICE_MMC1;
> +		case RCSR_MEM_TYPE_I2C:
> +			return BOOT_DEVICE_I2C;
> +		case RCSR_MEM_TYPE_SPI:
> +			return BOOT_DEVICE_SPI;
> +		default:
> +			return BOOT_DEVICE_NONE;
> +		}
> +	}
> +
> +	return BOOT_DEVICE_NONE;
> +}
> +

Eric

[U-Boot] [NEXT PATCH v1 2/7] NAND: added NAND type to nand_ids

[Stefano Babic]

On 23/09/2012 21:01, Eric B?nard wrote:
> Hi Stefano,
> 
> Le Mon, 10 Sep 2012 14:09:21 +0200,
> Stefano Babic <sbabic@denx.de> a ?crit :
>> The chip supports ONFI, but it seems the i.MX driver does not. Quite as
>> described in http://patchwork.ozlabs.org/patch/60042/. READ-ID is always
>> sent with address 0, I do not know if we can convince the driver to send
>> the address.
> 
> to add ONFI support to i.MX's driver, you can check this patch (in
> barebox, a similar patch for Linux is cooking, actually tested on
> i.MX53 and i.MX25) :
> http://git.pengutronix.de/?p=barebox.git;a=commit;h=632c45795065e6a7471ab82be38e808eb6204341

Thanks Eric, I look at it

Regards,
Stefano

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [NEXT PATCH v1 4/7] MX35: Add soc_boot_mode and soc_boot_device to MX35

[Stefano Babic]

On 23/09/2012 21:25, Eric B?nard wrote:
> Hi Stefano,
> 
> Le Thu,  6 Sep 2012 10:04:57 +0200,
> Stefano Babic <sbabic@denx.de> a ?crit :
>> +#define RCSR_MEM_CTL_WEIM	0
>> +#define RCSR_MEM_CTL_NAND	1
>> +#define RCSR_MEM_CTL_SD		2
>> +#define RCSR_MEM_TYPE_NOR	0
>> +#define RCSR_MEM_TYPE_ONENAND	2
>> +#define RCSR_MEM_TYPE_SD	0
>> +#define RCSR_MEM_TYPE_I2C	2
>> +#define RCSR_MEM_TYPE_SPI	3
>> +
>> +u32 spl_boot_device(void)
>> +{
>> +	puts("spl_boot_device\n");
>> +	struct ccm_regs *ccm =
>> +		(struct ccm_regs *)IMX_CCM_BASE;
>> +
>> +#if 1
>> +	return BOOT_DEVICE_MMC1;
>> +#endif
> 
> thisseems not clean and seems caused by the fact that the define
> RCSR_MEM_CTL_SD should be 3 and not 2 so in your tests the function
> spl_boot_device was not detecting the right boot mode. Also IMHO this
> define should be named RCSR_MEM_CTL_EXPANSION as in the app note AN3996
> at end of page 3 (there is a typo in the reference manual which seems
> to be a copy'n paste from i.MX25 as it doesn't take in acount the ATA
> HDD case) :
> http://cache.freescale.com/files/dsp/doc/app_note/AN3996.pdf

You're right, thanks ! I will fix in V2

Regards,
Stefano


-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [NEXT PATCH v1 2/7] NAND: added NAND type to nand_ids

[Stefano Babic]

On 11/09/2012 01:18, Scott Wood wrote:
> On 09/10/2012 07:09 AM, Stefano Babic wrote:
>> On 07/09/2012 20:56, Scott Wood wrote:
>>> What kind of chip is this?  Is the datasheet publicly available?
>>>
>>> These threads seem relevant:
>>> http://patchwork.ozlabs.org/patch/60042/
>>> http://old.nabble.com/-U-Boot--Add-new-NAND-flash-td29858370.html
>>
>> It is the same case,  as I can see, with the same chip.
>>
>>>

Hi Scott,

>>> Does the chip support ONFI?
>>
>> The chip supports ONFI, but it seems the i.MX driver does not. Quite as
>> described in http://patchwork.ozlabs.org/patch/60042/. READ-ID is always
>> sent with address 0, I do not know if we can convince the driver to send
>> the address.
> 
> How did Linux end up resolving this?

I could take a closer look. The issue is not solved on linux, too. In
fact, the MXC driver in current kernel supports ONFI, but it should work
for newer version of the controller - I think with MX5.

On MX35, the NFC controller is V1.1, exactly as on MX25, and I have the
same issue reported by Matthias that you pointed out in the past
threads: ONFI command does not work.

>  I think it'd be better to have the
> Micron decoding logic from that patch, than to introduce a special
> addition to the ID table for this one chip, which might not be correct
> for all chips with that ID byte.

Agree. I am trying to contact Micron to get some information about it. I
have tried to decode the bytes on basis of other Micron's NAND, but then
bit 6 in byte 4 says that the NAND is a 16 bit device, and that is
wrong. Exactly the same wrong value that Matthias found some times ago.

Stefano

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