[RFC 00/13] MIPS: JZ4750D: Add base support for Ingenic JZ4750D SOC

[RFC 00/13] MIPS: JZ4750D: Add base support for Ingenic JZ4750D SOC

[Antony Pavlov]

AFAIK the single known chip in Ingenic JZ4750D line is JZ4755.
It has just the same CPU core as JZ4740, but another set of
peripherals (though the program model for the most
of the peripherals is the same).

+-----------------+--------------+--------------+
|                 |   JZ4755     |    JZ4740    |
+-----------------+--------------+--------------+
| UART            |      3       |       4      |
| MSC (mmc/sd)    |      2       |       1      |
| GPIO            |     5x32     |      4x32    |
| TCU (timers)    | 6x16 + 1x32  |      8x16    |
| USB             |  device 2.0  |   host 1.1   |
|                 |              |  device 2.0  |
+-----------------+--------------+--------------+

The most significant advantage of the JZ4755 chip
is the second MIPS core dedicated for image processing.
Also JZ4755 is made with use of more precise technology
and it can run on the higher clock rate (approx. 433 MHz
for JZ4755 vs 336 MHz for JZ4740).

The JZ4755 is used in some game consoles:
* Ritmix RZX-50;
* Dingoo A320E/A380;
* GameLinBox.

This patch series based on the work of Lars-Peter Clausen.
To tell the truth it is the Lars-Peter Clausen's patches
with some fixes and changes.

As most of the code for JZ4750D is very close to code
for JZ4740 we can incorporate the code for JZ4750D
to the code for JZ4740 to avoid code duplication.

I propose to rename 'jz4740' mach directory to 'xburst'
or 'ingenic'.

The patch series introduces the minimal support for the JZ4755,
no peripherals are enabled save UART1. To test the kernel
I run it with incorporated initrd rootfs made with help
of https://github.com/gcwnow/buildroot.git

[RFC 01/13] MIPS: JZ4750D: Add base support for Ingenic JZ4750D
[RFC 02/13] MIPS: JZ4750D: Add clock API support
[RFC 03/13] MIPS: JZ4750D: Add IRQ handler code
[RFC 04/13] MIPS: JZ4750D: Add timer support
[RFC 05/13] MIPS: JZ4750D: Add clocksource/clockevent support
[RFC 06/13] MIPS: JZ4750D: Add system reset support
[RFC 07/13] MIPS: JZ4750D: Add setup code
[RFC 08/13] MIPS: JZ4750D: Add serial support
[RFC 09/13] MIPS: JZ4750D: Add prom support
[RFC 10/13] MIPS: JZ4750D: Add platform UART devices
[RFC 11/13] MIPS: JZ4750D: Add Kbuild files
[RFC 12/13] MIPS: JZ4750D: Add rzx50 board support
[RFC 13/13] MIPS: rzx50: Add defconfig file

[RFC 01/13] MIPS: JZ4750D: Add base support for Ingenic JZ4750D System-on-a-Chip

[Antony Pavlov]

Adds a new cpu type for the JZ4750D to the Linux MIPS architecture code.
It also adds the iomem addresses for the different components found on
a JZ4750D SoC.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
 arch/mips/include/asm/bootinfo.h          |    1 +
 arch/mips/include/asm/mach-jz4750d/base.h |   12 ++++++++++++
 arch/mips/include/asm/mach-jz4750d/war.h  |   25 +++++++++++++++++++++++++
 3 files changed, 38 insertions(+)
 create mode 100644 arch/mips/include/asm/mach-jz4750d/base.h
 create mode 100644 arch/mips/include/asm/mach-jz4750d/war.h

diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
index 7a51d87..1d7fea3 100644
--- a/arch/mips/include/asm/bootinfo.h
+++ b/arch/mips/include/asm/bootinfo.h
@@ -76,6 +76,7 @@
  */
 #define  MACH_INGENIC_JZ4730	0	/* JZ4730 SOC		*/
 #define  MACH_INGENIC_JZ4740	1	/* JZ4740 SOC		*/
+#define  MACH_INGENIC_JZ4750D	3	/* JZ4750D SOC		*/
 
 extern char *system_type;
 const char *get_system_type(void);
diff --git a/arch/mips/include/asm/mach-jz4750d/base.h b/arch/mips/include/asm/mach-jz4750d/base.h
new file mode 100644
index 0000000..723b1d0
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4750d/base.h
@@ -0,0 +1,12 @@
+#ifndef __ASM_MACH_JZ4750D_BASE_H__
+#define __ASM_MACH_JZ4750D_BASE_H__
+
+#define JZ4750D_CPM_BASE_ADDR	0x10000000
+#define JZ4750D_INTC_BASE_ADDR	0x10001000
+#define JZ4750D_WDT_BASE_ADDR	0x10002000
+#define JZ4750D_TCU_BASE_ADDR	0x10002010
+#define JZ4750D_RTC_BASE_ADDR	0x10003000
+#define JZ4750D_UART0_BASE_ADDR	0x10030000
+#define JZ4750D_UART1_BASE_ADDR	0x10031000
+
+#endif
diff --git a/arch/mips/include/asm/mach-jz4750d/war.h b/arch/mips/include/asm/mach-jz4750d/war.h
new file mode 100644
index 0000000..7bbad65
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4750d/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_JZ4750D_WAR_H
+#define __ASM_MIPS_MACH_JZ4750D_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR	0
+#define R4600_V1_HIT_CACHEOP_WAR	0
+#define R4600_V2_HIT_CACHEOP_WAR	0
+#define R5432_CP0_INTERRUPT_WAR		0
+#define BCM1250_M3_WAR			0
+#define SIBYTE_1956_WAR			0
+#define MIPS4K_ICACHE_REFILL_WAR	0
+#define MIPS_CACHE_SYNC_WAR		0
+#define TX49XX_ICACHE_INDEX_INV_WAR	0
+#define RM9000_CDEX_SMP_WAR		0
+#define ICACHE_REFILLS_WORKAROUND_WAR	0
+#define R10000_LLSC_WAR			0
+#define MIPS34K_MISSED_ITLB_WAR		0
+
+#endif /* __ASM_MIPS_MACH_JZ4750D_WAR_H */
-- 
1.7.10.4

[RFC 02/13] MIPS: JZ4750D: Add clock API support

[Antony Pavlov]

Add support for managing the clocks found on JZ4750D SoC through the
Linux clock API.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
 arch/mips/jz4750d/clock-debugfs.c |  107 ++++++++
 arch/mips/jz4750d/clock.c         |  499 +++++++++++++++++++++++++++++++++++++
 arch/mips/jz4750d/clock.h         |   75 ++++++
 3 files changed, 681 insertions(+)
 create mode 100644 arch/mips/jz4750d/clock-debugfs.c
 create mode 100644 arch/mips/jz4750d/clock.c
 create mode 100644 arch/mips/jz4750d/clock.h

diff --git a/arch/mips/jz4750d/clock-debugfs.c b/arch/mips/jz4750d/clock-debugfs.c
new file mode 100644
index 0000000..0d8a506
--- /dev/null
+++ b/arch/mips/jz4750d/clock-debugfs.c
@@ -0,0 +1,107 @@
+/*
+ *  Copyright (C) 2012, Antony Pavlov <antonynpavlov@gmail.com>
+ *  JZ4750D SoC clock support debugfs entries
+ *
+ *  based on JZ4740 SoC clock support debugfs entries
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation; either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+#include <linux/debugfs.h>
+#include <linux/uaccess.h>
+
+#include "clock.h"
+
+static struct dentry *jz4750d_clock_debugfs;
+
+static int jz4750d_clock_debugfs_show_enabled(void *data, uint64_t *value)
+{
+	struct clk *clk = data;
+	*value = clk_is_enabled(clk);
+
+	return 0;
+}
+
+static int jz4750d_clock_debugfs_set_enabled(void *data, uint64_t value)
+{
+	struct clk *clk = data;
+
+	if (value)
+		return clk_enable(clk);
+	else
+		clk_disable(clk);
+
+	return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(jz4750d_clock_debugfs_ops_enabled,
+	jz4750d_clock_debugfs_show_enabled,
+	jz4750d_clock_debugfs_set_enabled,
+	"%llu\n");
+
+static int jz4750d_clock_debugfs_show_rate(void *data, uint64_t *value)
+{
+	struct clk *clk = data;
+	*value = clk_get_rate(clk);
+
+	return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(jz4750d_clock_debugfs_ops_rate,
+	jz4750d_clock_debugfs_show_rate,
+	NULL,
+	"%llu\n");
+
+void jz4750d_clock_debugfs_add_clk(struct clk *clk)
+{
+	if (!jz4750d_clock_debugfs)
+		return;
+
+	clk->debugfs_entry = debugfs_create_dir(clk->name, jz4750d_clock_debugfs);
+	debugfs_create_file("rate", S_IWUGO | S_IRUGO, clk->debugfs_entry, clk,
+				&jz4750d_clock_debugfs_ops_rate);
+	debugfs_create_file("enabled", S_IRUGO, clk->debugfs_entry, clk,
+				&jz4750d_clock_debugfs_ops_enabled);
+
+	if (clk->parent) {
+		char parent_path[100];
+		snprintf(parent_path, 100, "../%s", clk->parent->name);
+		clk->debugfs_parent_entry = debugfs_create_symlink("parent",
+						clk->debugfs_entry,
+						parent_path);
+	}
+}
+
+/* TODO: Locking */
+void jz4750d_clock_debugfs_update_parent(struct clk *clk)
+{
+	if (clk->debugfs_parent_entry)
+		debugfs_remove(clk->debugfs_parent_entry);
+
+	if (clk->parent) {
+		char parent_path[100];
+		snprintf(parent_path, 100, "../%s", clk->parent->name);
+		clk->debugfs_parent_entry = debugfs_create_symlink("parent",
+						clk->debugfs_entry,
+						parent_path);
+	} else {
+		clk->debugfs_parent_entry = NULL;
+	}
+}
+
+void jz4750d_clock_debugfs_init(void)
+{
+	jz4750d_clock_debugfs = debugfs_create_dir("jz4750d-clock", NULL);
+	if (IS_ERR(jz4750d_clock_debugfs))
+		jz4750d_clock_debugfs = NULL;
+}
diff --git a/arch/mips/jz4750d/clock.c b/arch/mips/jz4750d/clock.c
new file mode 100644
index 0000000..a542fd5
--- /dev/null
+++ b/arch/mips/jz4750d/clock.c
@@ -0,0 +1,499 @@
+/*
+ *  Copyright (C) 2012, Antony Pavlov <antonynpavlov@gmail.com>
+ *  JZ4750D SoC clock support
+ *
+ *  based on JZ4740 SoC clock support
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation; either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/list.h>
+#include <linux/err.h>
+
+#include <asm/mach-jz4750d/base.h>
+
+#include "clock.h"
+
+#define JZ_REG_CLOCK_CTRL	0x00
+#define JZ_REG_CLOCK_PLL	0x10
+#define JZ_REG_CLOCK_GATE	0x20
+
+#define JZ_CLOCK_CTRL_KO_ENABLE		BIT(30)
+#define JZ_CLOCK_CTRL_UDC_SRC_PLL	BIT(29)
+#define JZ_CLOCK_CTRL_UDIV_MASK		0x1f800000
+#define JZ_CLOCK_CTRL_CHANGE_ENABLE	BIT(22)
+#define JZ_CLOCK_CTRL_PLL_HALF		BIT(21)
+#define JZ_CLOCK_CTRL_MDIV_OFFSET	12
+#define JZ_CLOCK_CTRL_PDIV_OFFSET	 8
+#define JZ_CLOCK_CTRL_HDIV_OFFSET	 4
+#define JZ_CLOCK_CTRL_CDIV_OFFSET	 0
+
+#define JZ_CLOCK_GATE_UART0	BIT(0)
+#define JZ_CLOCK_GATE_RTC	BIT(2)
+#define JZ_CLOCK_GATE_UART1	BIT(14)
+
+#define JZ_CLOCK_PLL_BYPASS	BIT(9)
+
+static void __iomem *jz_clock_base;
+static spinlock_t jz_clock_lock;
+static LIST_HEAD(jz_clocks);
+
+struct main_clk {
+	struct clk clk;
+	uint32_t div_offset;
+};
+
+struct divided_clk {
+	struct clk clk;
+	uint32_t reg;
+	uint32_t mask;
+};
+
+struct static_clk {
+	struct clk clk;
+	unsigned long rate;
+};
+
+static uint32_t jz_clk_reg_read(int reg)
+{
+	return readl(jz_clock_base + reg);
+}
+
+static void jz_clk_reg_write_mask(int reg, uint32_t val, uint32_t mask)
+{
+	uint32_t val2;
+
+	spin_lock(&jz_clock_lock);
+	val2 = readl(jz_clock_base + reg);
+	val2 &= ~mask;
+	val2 |= val;
+	writel(val2, jz_clock_base + reg);
+	spin_unlock(&jz_clock_lock);
+}
+
+static void jz_clk_reg_set_bits(int reg, uint32_t mask)
+{
+	uint32_t val;
+
+	spin_lock(&jz_clock_lock);
+	val = readl(jz_clock_base + reg);
+	val |= mask;
+	writel(val, jz_clock_base + reg);
+	spin_unlock(&jz_clock_lock);
+}
+
+static void jz_clk_reg_clear_bits(int reg, uint32_t mask)
+{
+	uint32_t val;
+
+	spin_lock(&jz_clock_lock);
+	val = readl(jz_clock_base + reg);
+	val &= ~mask;
+	writel(val, jz_clock_base + reg);
+	spin_unlock(&jz_clock_lock);
+}
+
+static int jz_clk_enable_gating(struct clk *clk)
+{
+	if (clk->gate_bit == JZ4750D_CLK_NOT_GATED)
+		return -EINVAL;
+
+	jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, clk->gate_bit);
+	return 0;
+}
+
+static int jz_clk_disable_gating(struct clk *clk)
+{
+	if (clk->gate_bit == JZ4750D_CLK_NOT_GATED)
+		return -EINVAL;
+
+	jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, clk->gate_bit);
+	return 0;
+}
+
+static int jz_clk_is_enabled_gating(struct clk *clk)
+{
+	if (clk->gate_bit == JZ4750D_CLK_NOT_GATED)
+		return 1;
+
+	return !(jz_clk_reg_read(JZ_REG_CLOCK_GATE) & clk->gate_bit);
+}
+
+static unsigned long jz_clk_static_get_rate(struct clk *clk)
+{
+	return ((struct static_clk *)clk)->rate;
+}
+
+static int jz_clk_ko_enable(struct clk *clk)
+{
+	jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_KO_ENABLE);
+	return 0;
+}
+
+static int jz_clk_ko_disable(struct clk *clk)
+{
+	jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_KO_ENABLE);
+	return 0;
+}
+
+static int jz_clk_ko_is_enabled(struct clk *clk)
+{
+	return !!(jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_KO_ENABLE);
+}
+
+static const int pllno[] = {1, 2, 2, 4};
+
+static unsigned long jz_clk_pll_get_rate(struct clk *clk)
+{
+	uint32_t val;
+	int m;
+	int n;
+	int od;
+
+	val = jz_clk_reg_read(JZ_REG_CLOCK_PLL);
+
+	if (val & JZ_CLOCK_PLL_BYPASS)
+		return clk_get_rate(clk->parent);
+
+	m = ((val >> 23) & 0x1ff) + 2;
+	n = ((val >> 18) & 0x1f) + 2;
+	od = (val >> 16) & 0x3;
+
+	return ((clk_get_rate(clk->parent) / n) * m) / pllno[od];
+}
+
+static unsigned long jz_clk_pll_half_get_rate(struct clk *clk)
+{
+	uint32_t reg;
+
+	reg = jz_clk_reg_read(JZ_REG_CLOCK_CTRL);
+	if (reg & JZ_CLOCK_CTRL_PLL_HALF)
+		return jz_clk_pll_get_rate(clk->parent);
+	return jz_clk_pll_get_rate(clk->parent) >> 1;
+}
+
+static const int jz_clk_main_divs[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
+
+static unsigned long jz_clk_main_round_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned long parent_rate = jz_clk_pll_get_rate(clk->parent);
+	int div;
+
+	div = parent_rate / rate;
+	if (div > 32)
+		return parent_rate / 32;
+	else if (div < 1)
+		return parent_rate;
+
+	div &= (0x3 << (ffs(div) - 1));
+
+	return parent_rate / div;
+}
+
+static unsigned long jz_clk_main_get_rate(struct clk *clk)
+{
+	struct main_clk *mclk = (struct main_clk *)clk;
+	uint32_t div;
+
+	div = jz_clk_reg_read(JZ_REG_CLOCK_CTRL);
+
+	div >>= mclk->div_offset;
+	div &= 0xf;
+
+	if (div >= ARRAY_SIZE(jz_clk_main_divs))
+		div = ARRAY_SIZE(jz_clk_main_divs) - 1;
+
+	return jz_clk_pll_get_rate(clk->parent) / jz_clk_main_divs[div];
+}
+
+static int jz_clk_main_set_rate(struct clk *clk, unsigned long rate)
+{
+	struct main_clk *mclk = (struct main_clk *)clk;
+	int i;
+	int div;
+	unsigned long parent_rate = jz_clk_pll_get_rate(clk->parent);
+
+	rate = jz_clk_main_round_rate(clk, rate);
+
+	div = parent_rate / rate;
+
+	i = (ffs(div) - 1) << 1;
+	if (i > 0 && !(div & BIT(i-1)))
+		i -= 1;
+
+	jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, i << mclk->div_offset,
+				0xf << mclk->div_offset);
+
+	return 0;
+}
+
+static struct clk_ops jz_clk_static_ops = {
+	.get_rate = jz_clk_static_get_rate,
+	.enable = jz_clk_enable_gating,
+	.disable = jz_clk_disable_gating,
+	.is_enabled = jz_clk_is_enabled_gating,
+};
+
+static struct static_clk jz_clk_ext = {
+	.clk = {
+		.name = "ext",
+		.gate_bit = JZ4750D_CLK_NOT_GATED,
+		.ops = &jz_clk_static_ops,
+	},
+};
+
+static struct clk_ops jz_clk_pll_ops = {
+	.get_rate = jz_clk_pll_get_rate,
+};
+
+static struct clk jz_clk_pll = {
+	.name = "pll",
+	.parent = &jz_clk_ext.clk,
+	.ops = &jz_clk_pll_ops,
+};
+
+static struct clk_ops jz_clk_pll_half_ops = {
+	.get_rate = jz_clk_pll_half_get_rate,
+};
+
+static struct clk jz_clk_pll_half = {
+	.name = "pll half",
+	.parent = &jz_clk_pll,
+	.ops = &jz_clk_pll_half_ops,
+};
+
+static const struct clk_ops jz_clk_main_ops = {
+	.get_rate = jz_clk_main_get_rate,
+	.set_rate = jz_clk_main_set_rate,
+	.round_rate = jz_clk_main_round_rate,
+};
+
+static struct main_clk jz_clk_cpu = {
+	.clk = {
+		.name = "cclk",
+		.parent = &jz_clk_pll,
+		.ops = &jz_clk_main_ops,
+	},
+	.div_offset = JZ_CLOCK_CTRL_CDIV_OFFSET,
+};
+
+static struct main_clk jz_clk_memory = {
+	.clk = {
+		.name = "mclk",
+		.parent = &jz_clk_pll,
+		.ops = &jz_clk_main_ops,
+	},
+	.div_offset = JZ_CLOCK_CTRL_MDIV_OFFSET,
+};
+
+static struct main_clk jz_clk_high_speed_peripheral = {
+	.clk = {
+		.name = "hclk",
+		.parent = &jz_clk_pll,
+		.ops = &jz_clk_main_ops,
+	},
+	.div_offset = JZ_CLOCK_CTRL_HDIV_OFFSET,
+};
+
+static struct main_clk jz_clk_low_speed_peripheral = {
+	.clk = {
+		.name = "pclk",
+		.parent = &jz_clk_pll,
+		.ops = &jz_clk_main_ops,
+	},
+	.div_offset = JZ_CLOCK_CTRL_PDIV_OFFSET,
+};
+
+static const struct clk_ops jz_clk_ko_ops = {
+	.enable = jz_clk_ko_enable,
+	.disable = jz_clk_ko_disable,
+	.is_enabled = jz_clk_ko_is_enabled,
+};
+
+static struct clk jz_clk_ko = {
+	.name = "cko",
+	.parent = &jz_clk_memory.clk,
+	.ops = &jz_clk_ko_ops,
+};
+
+static const struct clk_ops jz_clk_simple_ops = {
+	.enable = jz_clk_enable_gating,
+	.disable = jz_clk_disable_gating,
+	.is_enabled = jz_clk_is_enabled_gating,
+};
+
+static struct clk jz4750d_clock_simple_clks[] = {
+	[0] = {
+		.name = "uart0",
+		.parent = &jz_clk_ext.clk,
+		.gate_bit = JZ_CLOCK_GATE_UART0,
+		.ops = &jz_clk_simple_ops,
+	},
+	[1] = {
+		.name = "uart1",
+		.parent = &jz_clk_ext.clk,
+		.gate_bit = JZ_CLOCK_GATE_UART1,
+		.ops = &jz_clk_simple_ops,
+	},
+};
+
+static struct static_clk jz_clk_rtc = {
+	.clk = {
+		.name = "rtc",
+		.gate_bit = JZ_CLOCK_GATE_RTC,
+		.ops = &jz_clk_static_ops,
+	},
+	.rate = 32768,
+};
+
+int clk_enable(struct clk *clk)
+{
+	if (!clk->ops->enable)
+		return -EINVAL;
+
+	return clk->ops->enable(clk);
+}
+EXPORT_SYMBOL_GPL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+	if (clk->ops->disable)
+		clk->ops->disable(clk);
+}
+EXPORT_SYMBOL_GPL(clk_disable);
+
+int clk_is_enabled(struct clk *clk)
+{
+	if (clk->ops->is_enabled)
+		return clk->ops->is_enabled(clk);
+
+	return 1;
+}
+EXPORT_SYMBOL_GPL(clk_is_enabled);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+	if (clk->ops->get_rate)
+		return clk->ops->get_rate(clk);
+	if (clk->parent)
+		return clk_get_rate(clk->parent);
+
+	return -EINVAL;
+}
+EXPORT_SYMBOL_GPL(clk_get_rate);
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	if (!clk->ops->set_rate)
+		return -EINVAL;
+	return clk->ops->set_rate(clk, rate);
+}
+EXPORT_SYMBOL_GPL(clk_set_rate);
+
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+	if (clk->ops->round_rate)
+		return clk->ops->round_rate(clk, rate);
+
+	return -EINVAL;
+}
+EXPORT_SYMBOL_GPL(clk_round_rate);
+
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	int ret;
+	int enabled;
+
+	if (!clk->ops->set_parent)
+		return -EINVAL;
+
+	enabled = clk_is_enabled(clk);
+	if (enabled)
+		clk_disable(clk);
+	ret = clk->ops->set_parent(clk, parent);
+	if (enabled)
+		clk_enable(clk);
+
+	jz4750d_clock_debugfs_update_parent(clk);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(clk_set_parent);
+
+struct clk *clk_get(struct device *dev, const char *name)
+{
+	struct clk *clk;
+
+	list_for_each_entry(clk, &jz_clocks, list) {
+		if (strcmp(clk->name, name) == 0)
+			return clk;
+	}
+	return ERR_PTR(-ENXIO);
+}
+EXPORT_SYMBOL_GPL(clk_get);
+
+void clk_put(struct clk *clk)
+{
+}
+EXPORT_SYMBOL_GPL(clk_put);
+
+static inline void clk_add(struct clk *clk)
+{
+	list_add_tail(&clk->list, &jz_clocks);
+
+	jz4750d_clock_debugfs_add_clk(clk);
+}
+
+static void clk_register_clks(void)
+{
+	size_t i;
+
+	clk_add(&jz_clk_ext.clk);
+	clk_add(&jz_clk_pll);
+	clk_add(&jz_clk_pll_half);
+	clk_add(&jz_clk_cpu.clk);
+	clk_add(&jz_clk_high_speed_peripheral.clk);
+	clk_add(&jz_clk_low_speed_peripheral.clk);
+	clk_add(&jz_clk_ko);
+	clk_add(&jz_clk_rtc.clk);
+
+	for (i = 0; i < ARRAY_SIZE(jz4750d_clock_simple_clks); ++i)
+		clk_add(&jz4750d_clock_simple_clks[i]);
+}
+
+static int jz4750d_clock_init(void)
+{
+	uint32_t val;
+
+	jz_clock_base = ioremap(JZ4750D_CPM_BASE_ADDR, 0x100);
+	if (!jz_clock_base)
+		return -EBUSY;
+
+	spin_lock_init(&jz_clock_lock);
+
+	jz_clk_ext.rate = jz4750d_clock_bdata.ext_rate;
+	jz_clk_rtc.rate = jz4750d_clock_bdata.rtc_rate;
+
+	val = jz_clk_reg_read(JZ_REG_CLOCK_CTRL);
+
+	if (val & JZ_CLOCK_CTRL_UDC_SRC_PLL)
+		jz4750d_clock_simple_clks[0].parent = &jz_clk_pll_half;
+
+	jz4750d_clock_debugfs_init();
+
+	clk_register_clks();
+
+	return 0;
+}
+arch_initcall(jz4750d_clock_init);
diff --git a/arch/mips/jz4750d/clock.h b/arch/mips/jz4750d/clock.h
new file mode 100644
index 0000000..f809b51
--- /dev/null
+++ b/arch/mips/jz4750d/clock.h
@@ -0,0 +1,75 @@
+/*
+ *  Copyright (C) 2012, Antony Pavlov <antonynpavlov@gmail.com>
+ *  JZ4750D SoC clock support
+ *
+ *  based on JZ4740 SoC clock support
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation; either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#ifndef __MIPS_JZ4750D_CLOCK_H__
+#define __MIPS_JZ4750D_CLOCK_H__
+
+#include <linux/list.h>
+
+struct jz4750d_clock_board_data {
+	unsigned long ext_rate;
+	unsigned long rtc_rate;
+};
+
+extern struct jz4750d_clock_board_data jz4750d_clock_bdata;
+
+void jz4750d_clock_suspend(void);
+void jz4750d_clock_resume(void);
+
+struct clk;
+
+struct clk_ops {
+	unsigned long (*get_rate)(struct clk *clk);
+	unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
+	int (*set_rate)(struct clk *clk, unsigned long rate);
+	int (*enable)(struct clk *clk);
+	int (*disable)(struct clk *clk);
+	int (*is_enabled)(struct clk *clk);
+
+	int (*set_parent)(struct clk *clk, struct clk *parent);
+
+};
+
+struct clk {
+	const char *name;
+	struct clk *parent;
+
+	uint32_t gate_bit;
+
+	const struct clk_ops *ops;
+
+	struct list_head list;
+
+#ifdef CONFIG_DEBUG_FS
+	struct dentry *debugfs_entry;
+	struct dentry *debugfs_parent_entry;
+#endif
+
+};
+
+#define JZ4750D_CLK_NOT_GATED ((uint32_t)-1)
+
+int clk_is_enabled(struct clk *clk);
+
+#ifdef CONFIG_DEBUG_FS
+void jz4750d_clock_debugfs_init(void);
+void jz4750d_clock_debugfs_add_clk(struct clk *clk);
+void jz4750d_clock_debugfs_update_parent(struct clk *clk);
+#else
+static inline void jz4750d_clock_debugfs_init(void) {};
+static inline void jz4750d_clock_debugfs_add_clk(struct clk *clk) {};
+static inline void jz4750d_clock_debugfs_update_parent(struct clk *clk) {};
+#endif
+
+#endif
-- 
1.7.10.4

[RFC 03/13] MIPS: JZ4750D: Add IRQ handler code

[Antony Pavlov]

Add support for IRQ handling on a JZ4750D SoC.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
 arch/mips/include/asm/mach-jz4750d/irq.h |   29 ++++++
 arch/mips/jz4750d/irq.c                  |  158 ++++++++++++++++++++++++++++++
 2 files changed, 187 insertions(+)
 create mode 100644 arch/mips/include/asm/mach-jz4750d/irq.h
 create mode 100644 arch/mips/jz4750d/irq.c

diff --git a/arch/mips/include/asm/mach-jz4750d/irq.h b/arch/mips/include/asm/mach-jz4750d/irq.h
new file mode 100644
index 0000000..3b157d0
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4750d/irq.h
@@ -0,0 +1,29 @@
+/*
+ *  Copyright (C) 2012, Antony Pavlov <antonynpavlov@gmail.com>
+ *  JZ4750D IRQ definitions
+ *
+ *  based on JZ4740 IRQ definitions
+ *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation; either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#ifndef __ASM_MACH_JZ4750D_IRQ_H__
+#define __ASM_MACH_JZ4750D_IRQ_H__
+
+#define MIPS_CPU_IRQ_BASE 0
+#define JZ4750D_IRQ_BASE 8
+
+#define JZ4750D_IRQ(x)		(JZ4750D_IRQ_BASE + (x))
+
+#define JZ4750D_IRQ_UART1	JZ4750D_IRQ(8)
+#define JZ4750D_IRQ_UART0	JZ4750D_IRQ(9)
+#define JZ4750D_IRQ_TCU1	JZ4750D_IRQ(22)
+
+#define NR_IRQS (256)
+
+#endif
diff --git a/arch/mips/jz4750d/irq.c b/arch/mips/jz4750d/irq.c
new file mode 100644
index 0000000..dcd1153
--- /dev/null
+++ b/arch/mips/jz4750d/irq.c
@@ -0,0 +1,158 @@
+/*
+ *  Copyright (C) 2012, Antony Pavlov <antonynpavlov@gmail.com>
+ *  JZ4750D platform IRQ support
+ *
+ *  based on JZ4740 platform IRQ support
+ *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation; either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/timex.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+
+#include <asm/io.h>
+#include <asm/mipsregs.h>
+#include <asm/irq_cpu.h>
+
+#include <asm/mach-jz4750d/base.h>
+
+static void __iomem *jz_intc_base;
+static uint32_t jz_intc_wakeup;
+
+#define JZ_REG_INTC_STATUS	0x00
+#define JZ_REG_INTC_MASK	0x04
+#define JZ_REG_INTC_SET_MASK	0x08
+#define JZ_REG_INTC_CLEAR_MASK	0x0c
+#define JZ_REG_INTC_PENDING	0x10
+
+#define IRQ_BIT(x) BIT((x) - JZ4750D_IRQ_BASE)
+
+static inline unsigned long intc_irq_bit(struct irq_data *data)
+{
+	return (unsigned long)irq_data_get_irq_chip_data(data);
+}
+
+static void intc_irq_unmask(struct irq_data *d)
+{
+	writel(intc_irq_bit(d), jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
+}
+
+static void intc_irq_mask(struct irq_data *d)
+{
+	writel(intc_irq_bit(d), jz_intc_base + JZ_REG_INTC_SET_MASK);
+}
+
+static int intc_irq_set_wake(struct irq_data *d, unsigned int on)
+{
+	if (on)
+		jz_intc_wakeup |= intc_irq_bit(d);
+	else
+		jz_intc_wakeup &= ~intc_irq_bit(d);
+
+	return 0;
+}
+
+static struct irq_chip intc_irq_type = {
+	.name =		"INTC",
+	.irq_mask =	intc_irq_mask,
+	.irq_mask_ack =	intc_irq_mask,
+	.irq_unmask =	intc_irq_unmask,
+	.irq_set_wake =	intc_irq_set_wake,
+};
+
+static irqreturn_t jz4750d_cascade(int irq, void *data)
+{
+	uint32_t irq_reg;
+
+	irq_reg = readl(jz_intc_base + JZ_REG_INTC_PENDING);
+
+	if (irq_reg)
+		generic_handle_irq(__fls(irq_reg) + JZ4750D_IRQ_BASE);
+
+	return IRQ_HANDLED;
+}
+
+static struct irqaction jz4750d_cascade_action = {
+	.handler = jz4750d_cascade,
+	.name = "JZ4750D cascade interrupt",
+};
+
+void __init arch_init_irq(void)
+{
+	int i;
+
+	mips_cpu_irq_init();
+
+	jz_intc_base = ioremap(JZ4750D_INTC_BASE_ADDR, 0x14);
+
+	for (i = JZ4750D_IRQ_BASE; i < JZ4750D_IRQ_BASE + 32; i++) {
+		irq_set_chip_data(i, (void *)IRQ_BIT(i));
+		irq_set_chip_and_handler(i, &intc_irq_type, handle_level_irq);
+	}
+
+	setup_irq(2, &jz4750d_cascade_action);
+}
+
+asmlinkage void plat_irq_dispatch(void)
+{
+	unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
+	if (pending & STATUSF_IP2)
+		do_IRQ(2);
+	else if (pending & STATUSF_IP3)
+		do_IRQ(3);
+	else
+		spurious_interrupt();
+}
+
+#ifdef CONFIG_DEBUG_FS
+
+static inline void intc_seq_reg(struct seq_file *s, const char *name,
+	unsigned int reg)
+{
+	seq_printf(s, "%s:\t\t%08x\n", name, readl(jz_intc_base + reg));
+}
+
+static int intc_regs_show(struct seq_file *s, void *unused)
+{
+	intc_seq_reg(s, "Status", JZ_REG_INTC_STATUS);
+	intc_seq_reg(s, "Mask", JZ_REG_INTC_MASK);
+	intc_seq_reg(s, "Pending", JZ_REG_INTC_PENDING);
+
+	return 0;
+}
+
+static int intc_regs_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, intc_regs_show, NULL);
+}
+
+static const struct file_operations intc_regs_operations = {
+	.open		= intc_regs_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static int __init intc_debugfs_init(void)
+{
+	(void) debugfs_create_file("jz_regs_intc", S_IFREG | S_IRUGO,
+				NULL, NULL, &intc_regs_operations);
+	return 0;
+}
+subsys_initcall(intc_debugfs_init);
+
+#endif
-- 
1.7.10.4

[RFC 04/13] MIPS: JZ4750D: Add timer support

[Antony Pavlov]

Add support for the timer/counter unit on a JZ4750D SoC. This code is used
as a common base for the JZ4750D clocksource/clockevent implementation and
PWM support.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
 arch/mips/include/asm/mach-jz4750d/timer.h |   21 ++++
 arch/mips/jz4750d/timer.c                  |   49 ++++++++
 arch/mips/jz4750d/timer.h                  |  182 ++++++++++++++++++++++++++++
 3 files changed, 252 insertions(+)
 create mode 100644 arch/mips/include/asm/mach-jz4750d/timer.h
 create mode 100644 arch/mips/jz4750d/timer.c
 create mode 100644 arch/mips/jz4750d/timer.h

diff --git a/arch/mips/include/asm/mach-jz4750d/timer.h b/arch/mips/include/asm/mach-jz4750d/timer.h
new file mode 100644
index 0000000..7a1ba46
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4750d/timer.h
@@ -0,0 +1,21 @@
+/*
+ *  Copyright (C) 2012, Antony Pavlov <antonynpavlov@gmail.com>
+ *  JZ4750D platform timer support
+ *
+ *  based on JZ4740 platform timer support
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation; either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#ifndef __ASM_MACH_JZ4750D_TIMER
+#define __ASM_MACH_JZ4750D_TIMER
+
+void jz4750d_timer_enable_watchdog(void);
+void jz4750d_timer_disable_watchdog(void);
+
+#endif
diff --git a/arch/mips/jz4750d/timer.c b/arch/mips/jz4750d/timer.c
new file mode 100644
index 0000000..85682b1
--- /dev/null
+++ b/arch/mips/jz4750d/timer.c
@@ -0,0 +1,49 @@
+/*
+ *  Copyright (C) 2012, Antony Pavlov <antonynpavlov@gmail.com>
+ *  JZ4750D platform timer support
+ *
+ *  based on JZ4740 platform timer support
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation; either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include "timer.h"
+
+#include <asm/mach-jz4750d/base.h>
+
+void __iomem *jz4750d_timer_base;
+
+void jz4750d_timer_enable_watchdog(void)
+{
+	writel(BIT(16), jz4750d_timer_base + JZ_REG_TIMER_STOP_CLEAR);
+}
+EXPORT_SYMBOL_GPL(jz4750d_timer_enable_watchdog);
+
+void jz4750d_timer_disable_watchdog(void)
+{
+	writel(BIT(16), jz4750d_timer_base + JZ_REG_TIMER_STOP_SET);
+}
+EXPORT_SYMBOL_GPL(jz4750d_timer_disable_watchdog);
+
+void __init jz4750d_timer_init(void)
+{
+	jz4750d_timer_base = ioremap(JZ4750D_TCU_BASE_ADDR, 0x100);
+
+	if (!jz4750d_timer_base)
+		panic("Failed to ioremap timer registers");
+
+	/* Disable __ALL__ timer clocks */
+	writel(0x000180ff, jz4750d_timer_base + JZ_REG_TIMER_STOP_SET);
+
+	/* Timer irqs are unmasked by default, mask them __ALL__ */
+	writel(0x003f803f, jz4750d_timer_base + JZ_REG_TIMER_MASK_SET);
+}
diff --git a/arch/mips/jz4750d/timer.h b/arch/mips/jz4750d/timer.h
new file mode 100644
index 0000000..05e4752
--- /dev/null
+++ b/arch/mips/jz4750d/timer.h
@@ -0,0 +1,182 @@
+/*
+ *  Copyright (C) 2012, Antony Pavlov <antonynpavlov@gmail.com>
+ *  JZ4750D platform timer support
+ *
+ *  based on JZ4740 platform timer support
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation; either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#ifndef __MIPS_JZ4750D_TIMER_H__
+#define __MIPS_JZ4750D_TIMER_H__
+
+#include <linux/module.h>
+#include <linux/io.h>
+
+#define JZ_REG_TIMER_ENABLE		0x00
+#define JZ_REG_TIMER_ENABLE_SET		0x04
+#define JZ_REG_TIMER_ENABLE_CLEAR	0x08
+#define JZ_REG_TIMER_FLAG		0x10
+#define JZ_REG_TIMER_FLAG_SET		0x14
+#define JZ_REG_TIMER_FLAG_CLEAR		0x18
+#define JZ_REG_TIMER_STOP		0x0C
+#define JZ_REG_TIMER_STOP_SET		0x1C
+#define JZ_REG_TIMER_STOP_CLEAR		0x2C
+#define JZ_REG_TIMER_MASK		0x20
+#define JZ_REG_TIMER_MASK_SET		0x24
+#define JZ_REG_TIMER_MASK_CLEAR		0x28
+
+#define JZ_REG_TIMER_DFR(x) (((x) * 0x10) + 0x30)
+#define JZ_REG_TIMER_DHR(x) (((x) * 0x10) + 0x34)
+#define JZ_REG_TIMER_CNT(x) (((x) * 0x10) + 0x38)
+#define JZ_REG_TIMER_CTRL(x) (((x) * 0x10) + 0x3C)
+
+#define JZ_TIMER_IRQ_HALF(x) BIT((x) + 0x10)
+#define JZ_TIMER_IRQ_FULL(x) BIT(x)
+
+#define JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN	BIT(9)
+#define JZ_TIMER_CTRL_PWM_ACTIVE_LOW		BIT(8)
+#define JZ_TIMER_CTRL_PWM_ENABLE		BIT(7)
+#define JZ_TIMER_CTRL_PRESCALE_MASK		0x1c
+#define JZ_TIMER_CTRL_PRESCALE_OFFSET		0x3
+#define JZ_TIMER_CTRL_PRESCALE_1		(0 << 3)
+#define JZ_TIMER_CTRL_PRESCALE_4		(1 << 3)
+#define JZ_TIMER_CTRL_PRESCALE_16		(2 << 3)
+#define JZ_TIMER_CTRL_PRESCALE_64		(3 << 3)
+#define JZ_TIMER_CTRL_PRESCALE_256		(4 << 3)
+#define JZ_TIMER_CTRL_PRESCALE_1024		(5 << 3)
+
+#define JZ_TIMER_CTRL_PRESCALER(x) ((x) << JZ_TIMER_CTRL_PRESCALE_OFFSET)
+
+#define JZ_TIMER_CTRL_SRC_EXT		BIT(2)
+#define JZ_TIMER_CTRL_SRC_RTC		BIT(1)
+#define JZ_TIMER_CTRL_SRC_PCLK		BIT(0)
+
+extern void __iomem *jz4750d_timer_base;
+void __init jz4750d_timer_init(void);
+
+static inline void jz4750d_timer_stop(unsigned int timer)
+{
+	writel(BIT(timer), jz4750d_timer_base + JZ_REG_TIMER_STOP_SET);
+}
+
+static inline void jz4750d_timer_start(unsigned int timer)
+{
+	writel(BIT(timer), jz4750d_timer_base + JZ_REG_TIMER_STOP_CLEAR);
+}
+
+static inline bool jz4750d_timer_is_enabled(unsigned int timer)
+{
+	return readb(jz4750d_timer_base + JZ_REG_TIMER_ENABLE) & BIT(timer);
+}
+
+static inline void jz4750d_timer_enable(unsigned int timer)
+{
+	writeb(BIT(timer), jz4750d_timer_base + JZ_REG_TIMER_ENABLE_SET);
+}
+
+static inline void jz4750d_timer_disable(unsigned int timer)
+{
+	writeb(BIT(timer), jz4750d_timer_base + JZ_REG_TIMER_ENABLE_CLEAR);
+}
+
+static inline void jz4750d_timer_set_period(unsigned int timer, u16 period)
+{
+	writew(period, jz4750d_timer_base + JZ_REG_TIMER_DFR(timer));
+}
+
+static inline void jz4750d_timer_set_duty(unsigned int timer, u16 duty)
+{
+	writew(duty, jz4750d_timer_base + JZ_REG_TIMER_DHR(timer));
+}
+
+static inline void jz4750d_timer_set_count(unsigned int timer, u16 count)
+{
+	writew(count, jz4750d_timer_base + JZ_REG_TIMER_CNT(timer));
+}
+
+static inline u16 jz4750d_timer_get_count(unsigned int timer)
+{
+	return readw(jz4750d_timer_base + JZ_REG_TIMER_CNT(timer));
+}
+
+static inline void jz4750d_timer_ack_full(unsigned int timer)
+{
+	writel(JZ_TIMER_IRQ_FULL(timer),
+		jz4750d_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
+}
+
+static inline void jz4750d_timer_irq_full_enable(unsigned int timer)
+{
+	writel(JZ_TIMER_IRQ_FULL(timer),
+		jz4750d_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
+	writel(JZ_TIMER_IRQ_FULL(timer),
+		jz4750d_timer_base + JZ_REG_TIMER_MASK_CLEAR);
+}
+
+static inline void jz4750d_timer_irq_full_disable(unsigned int timer)
+{
+	writel(JZ_TIMER_IRQ_FULL(timer),
+		jz4750d_timer_base + JZ_REG_TIMER_MASK_SET);
+}
+
+static inline void jz4750d_timer_set_ctrl(unsigned int timer, u16 ctrl)
+{
+	writew(ctrl, jz4750d_timer_base + JZ_REG_TIMER_CTRL(timer));
+}
+
+static inline u16 jz4750d_timer_get_ctrl(unsigned int timer)
+{
+	return readw(jz4750d_timer_base + JZ_REG_TIMER_CTRL(timer));
+}
+
+#define JZ_REG_OSTIMER_DR		0xD0
+#define JZ_REG_OSTIMER_CNT		0xD8
+#define JZ_REG_OSTIMER_CTRL		0xDC
+
+#define JZ_OSTIMER_CTRL_PRESCALE_1		(0 << 3)
+#define JZ_OSTIMER_CTRL_PRESCALE_4		(1 << 3)
+#define JZ_OSTIMER_CTRL_PRESCALE_16		(2 << 3)
+#define JZ_OSTIMER_CTRL_PRESCALE_64		(3 << 3)
+#define JZ_OSTIMER_CTRL_PRESCALE_256		(4 << 3)
+#define JZ_OSTIMER_CTRL_PRESCALE_1024		(5 << 3)
+
+#define JZ_OSTIMER_CTRL_SRC_EXT		BIT(2)
+#define JZ_OSTIMER_CTRL_SRC_RTC		BIT(1)
+#define JZ_OSTIMER_CTRL_SRC_PCLK	BIT(0)
+
+#define JZ_TIMER_SCR_OSTSC		BIT(15)
+#define JZ_TIMER_ESR_OSTST		BIT(15)
+
+static inline void jz4750d_ostimer_set_ctrl(u16 ctrl)
+{
+	writew(ctrl, jz4750d_timer_base + JZ_REG_OSTIMER_CTRL);
+}
+
+static inline uint32_t jz4750d_ostimer_get_count(void)
+{
+	return readl(jz4750d_timer_base + JZ_REG_OSTIMER_CNT);
+}
+
+static inline void jz4750d_ostimer_start(void)
+{
+	writel(JZ_TIMER_SCR_OSTSC,
+		jz4750d_timer_base + JZ_REG_TIMER_STOP_CLEAR);
+}
+
+static inline void jz4750d_ostimer_enable(void)
+{
+	writel(JZ_TIMER_ESR_OSTST,
+		jz4750d_timer_base + JZ_REG_TIMER_ENABLE_SET);
+}
+
+static inline void jz4750d_ostimer_set_period(u32 period)
+{
+	writel(period, jz4750d_timer_base + JZ_REG_OSTIMER_DR);
+}
+#endif
-- 
1.7.10.4

[RFC 05/13] MIPS: JZ4750D: Add clocksource/clockevent support

[Antony Pavlov]

Add clocksource and clockevent support for the timer/counter unit on
JZ4750D SoCs.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
 arch/mips/jz4750d/time.c |  145 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 145 insertions(+)
 create mode 100644 arch/mips/jz4750d/time.c

diff --git a/arch/mips/jz4750d/time.c b/arch/mips/jz4750d/time.c
new file mode 100644
index 0000000..5df91e0
--- /dev/null
+++ b/arch/mips/jz4750d/time.c
@@ -0,0 +1,145 @@
+/*
+ *  Copyright (C) 2012, Antony Pavlov <antonynpavlov@gmail.com>
+ *  JZ4750D platform time support
+ *
+ *  based on JZ4740 platform time support
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation; either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/time.h>
+
+#include <linux/clockchips.h>
+
+#include <asm/time.h>
+
+#include "clock.h"
+#include "timer.h"
+
+#define TIMER_CLOCKEVENT 5
+
+static uint16_t jz4750d_jiffies_per_tick;
+
+static cycle_t jz4750d_clocksource_read(struct clocksource *cs)
+{
+	return (cycle_t)jz4750d_ostimer_get_count();
+}
+
+static struct clocksource jz4750d_clocksource = {
+	.name = "jz4750d-timer",
+	.rating = 200,
+	.read = jz4750d_clocksource_read,
+	.mask = CLOCKSOURCE_MASK(32),
+	.flags = CLOCK_SOURCE_WATCHDOG,
+};
+
+static irqreturn_t jz4750d_clockevent_irq(int irq, void *devid)
+{
+	struct clock_event_device *cd = devid;
+
+	jz4750d_timer_ack_full(TIMER_CLOCKEVENT);
+
+	if (cd->mode != CLOCK_EVT_MODE_PERIODIC)
+		jz4750d_timer_disable(TIMER_CLOCKEVENT);
+
+	cd->event_handler(cd);
+
+	return IRQ_HANDLED;
+}
+
+static void jz4750d_clockevent_set_mode(enum clock_event_mode mode,
+	struct clock_event_device *cd)
+{
+	switch (mode) {
+	case CLOCK_EVT_MODE_PERIODIC:
+		jz4750d_timer_set_count(TIMER_CLOCKEVENT, 0);
+		jz4750d_timer_set_period(TIMER_CLOCKEVENT, jz4750d_jiffies_per_tick);
+	case CLOCK_EVT_MODE_RESUME:
+		jz4750d_timer_irq_full_enable(TIMER_CLOCKEVENT);
+		jz4750d_timer_enable(TIMER_CLOCKEVENT);
+		break;
+	case CLOCK_EVT_MODE_ONESHOT:
+	case CLOCK_EVT_MODE_SHUTDOWN:
+		jz4750d_timer_disable(TIMER_CLOCKEVENT);
+		break;
+	default:
+		break;
+	}
+}
+
+static int jz4750d_clockevent_set_next(unsigned long evt,
+	struct clock_event_device *cd)
+{
+	jz4750d_timer_set_count(TIMER_CLOCKEVENT, 0);
+	jz4750d_timer_set_period(TIMER_CLOCKEVENT, evt);
+	jz4750d_timer_enable(TIMER_CLOCKEVENT);
+
+	return 0;
+}
+
+static struct clock_event_device jz4750d_clockevent = {
+	.name = "jz4750d-timer",
+	.features = CLOCK_EVT_FEAT_PERIODIC,
+	.set_next_event = jz4750d_clockevent_set_next,
+	.set_mode = jz4750d_clockevent_set_mode,
+	.rating = 200,
+	.irq = JZ4750D_IRQ_TCU1,
+};
+
+static struct irqaction timer_irqaction = {
+	.handler = jz4750d_clockevent_irq,
+	.flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER,
+	.name = "jz4750d-timerirq",
+	.dev_id = &jz4750d_clockevent,
+};
+
+void __init plat_time_init(void)
+{
+	int ret;
+	uint32_t clk_rate;
+
+	jz4750d_timer_init();
+
+	clk_rate = jz4750d_clock_bdata.ext_rate >> 4;
+	jz4750d_jiffies_per_tick = DIV_ROUND_CLOSEST(clk_rate, HZ);
+
+	clockevent_set_clock(&jz4750d_clockevent, clk_rate);
+	jz4750d_clockevent.min_delta_ns =
+		clockevent_delta2ns(100, &jz4750d_clockevent);
+	jz4750d_clockevent.max_delta_ns =
+		clockevent_delta2ns(0xffff, &jz4750d_clockevent);
+	jz4750d_clockevent.cpumask = cpumask_of(0);
+
+	jz4750d_timer_irq_full_disable(TIMER_CLOCKEVENT);
+
+	clockevents_register_device(&jz4750d_clockevent);
+
+	ret = clocksource_register_hz(&jz4750d_clocksource, clk_rate);
+
+	if (ret)
+		printk(KERN_ERR "Failed to register clocksource: %d\n", ret);
+
+	setup_irq(JZ4750D_IRQ_TCU1, &timer_irqaction);
+
+	jz4750d_timer_set_ctrl(TIMER_CLOCKEVENT, JZ_TIMER_CTRL_PRESCALE_16
+		| JZ_TIMER_CTRL_SRC_EXT);
+	jz4750d_ostimer_set_ctrl(JZ_OSTIMER_CTRL_PRESCALE_16
+		| JZ_OSTIMER_CTRL_SRC_EXT);
+
+	jz4750d_timer_set_period(TIMER_CLOCKEVENT, jz4750d_jiffies_per_tick);
+	jz4750d_timer_irq_full_enable(TIMER_CLOCKEVENT);
+
+	jz4750d_ostimer_set_period(0xffffffff);
+
+	jz4750d_timer_enable(TIMER_CLOCKEVENT);
+	jz4750d_timer_start(TIMER_CLOCKEVENT);
+	jz4750d_ostimer_enable();
+	jz4750d_ostimer_start();
+}
-- 
1.7.10.4

[RFC 06/13] MIPS: JZ4750D: Add system reset support

[Antony Pavlov]

Add support for poweroff/reboot on a JZ4750D SoC.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
 arch/mips/jz4750d/reset.c |   79 +++++++++++++++++++++++++++++++++++++++++++++
 arch/mips/jz4750d/reset.h |    6 ++++
 2 files changed, 85 insertions(+)
 create mode 100644 arch/mips/jz4750d/reset.c
 create mode 100644 arch/mips/jz4750d/reset.h

diff --git a/arch/mips/jz4750d/reset.c b/arch/mips/jz4750d/reset.c
new file mode 100644
index 0000000..eb8441c
--- /dev/null
+++ b/arch/mips/jz4750d/reset.c
@@ -0,0 +1,79 @@
+/*
+ *  Copyright (C) 2012, Antony Pavlov <antonynpavlov@gmail.com>
+ *  JZ4750D reset routines
+ *
+ *  based on JZ4740 reset routines
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation; either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/pm.h>
+
+#include <asm/reboot.h>
+
+#include <asm/mach-jz4750d/base.h>
+#include <asm/mach-jz4750d/timer.h>
+
+static void jz4750d_halt(void)
+{
+	while (1) {
+		__asm__(".set push;\n"
+			".set mips3;\n"
+			"wait;\n"
+			".set pop;\n"
+		);
+	}
+}
+
+#define JZ_REG_WDT_DATA 0x00
+#define JZ_REG_WDT_COUNTER_ENABLE 0x04
+#define JZ_REG_WDT_COUNTER 0x08
+#define JZ_REG_WDT_CTRL 0x0c
+
+static void jz4750d_restart(char *command)
+{
+	void __iomem *wdt_base = ioremap(JZ4750D_WDT_BASE_ADDR, 0x0f);
+
+	jz4750d_timer_enable_watchdog();
+
+	writeb(0, wdt_base + JZ_REG_WDT_COUNTER_ENABLE);
+
+	writew(0, wdt_base + JZ_REG_WDT_COUNTER);
+	writew(0, wdt_base + JZ_REG_WDT_DATA);
+	writew(BIT(2), wdt_base + JZ_REG_WDT_CTRL);
+
+	writeb(1, wdt_base + JZ_REG_WDT_COUNTER_ENABLE);
+	jz4750d_halt();
+}
+
+#define JZ_REG_RTC_CTRL		0x00
+#define JZ_REG_RTC_HIBERNATE	0x20
+
+#define JZ_RTC_CTRL_WRDY	BIT(7)
+
+static void jz4750d_power_off(void)
+{
+	void __iomem *rtc_base = ioremap(JZ4750D_RTC_BASE_ADDR, 0x24);
+	uint32_t ctrl;
+
+	do {
+		ctrl = readl(rtc_base + JZ_REG_RTC_CTRL);
+	} while (!(ctrl & JZ_RTC_CTRL_WRDY));
+
+	writel(1, rtc_base + JZ_REG_RTC_HIBERNATE);
+	jz4750d_halt();
+}
+
+void jz4750d_reset_init(void)
+{
+	_machine_restart = jz4750d_restart;
+	_machine_halt = jz4750d_halt;
+	pm_power_off = jz4750d_power_off;
+}
diff --git a/arch/mips/jz4750d/reset.h b/arch/mips/jz4750d/reset.h
new file mode 100644
index 0000000..e00d1e1
--- /dev/null
+++ b/arch/mips/jz4750d/reset.h
@@ -0,0 +1,6 @@
+#ifndef __MIPS_JZ4750D_RESET_H__
+#define __MIPS_JZ4750D_RESET_H__
+
+extern void jz4750d_reset_init(void);
+
+#endif
-- 
1.7.10.4

[RFC 07/13] MIPS: JZ4750D: Add setup code

[Antony Pavlov]

Add get_system_type for JZ4750D SoCs. Fix memory size to 64M.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
 arch/mips/jz4750d/setup.c |   35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 arch/mips/jz4750d/setup.c

diff --git a/arch/mips/jz4750d/setup.c b/arch/mips/jz4750d/setup.c
new file mode 100644
index 0000000..e36ed0a
--- /dev/null
+++ b/arch/mips/jz4750d/setup.c
@@ -0,0 +1,35 @@
+/*
+ *  Copyright (C) 2012, Antony Pavlov <antonynpavlov@gmail.com>
+ *  JZ4750D setup code
+ *
+ *  based on JZ4740 setup code
+ *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  Copyright (C) 2011, Maarten ter Huurne <maarten@treewalker.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation; either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+
+#include <asm/bootinfo.h>
+
+#include "reset.h"
+
+void __init plat_mem_setup(void)
+{
+	jz4750d_reset_init();
+
+	/* FIXME: the detection of the memory size is skipped */
+	add_memory_region(0, 0x04000000 /* 64 M */, BOOT_MEM_RAM);
+}
+
+const char *get_system_type(void)
+{
+	return "JZ4750D";
+}
-- 
1.7.10.4

[RFC 08/13] MIPS: JZ4750D: Add serial support

[Antony Pavlov]

The JZ4750D UART interface is almost 16550 compatible.
The UART module needs to be enabled by setting a bit in the FCR register
and it has support for receive timeout interrupts. Instead of adding yet
another machine specific quirk to the 8250 serial driver we provide a
serial_out implementation which sets the required additional flags.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
 arch/mips/jz4750d/serial.c |   32 ++++++++++++++++++++++++++++++++
 arch/mips/jz4750d/serial.h |   22 ++++++++++++++++++++++
 2 files changed, 54 insertions(+)
 create mode 100644 arch/mips/jz4750d/serial.c
 create mode 100644 arch/mips/jz4750d/serial.h

diff --git a/arch/mips/jz4750d/serial.c b/arch/mips/jz4750d/serial.c
new file mode 100644
index 0000000..e152e64
--- /dev/null
+++ b/arch/mips/jz4750d/serial.c
@@ -0,0 +1,32 @@
+/*
+ *  Copyright (C) 2012, Antony Pavlov <antonynpavlov@gmail.com>
+ *  JZ4750D serial support
+ *
+ *  based on JZ4740 serial support
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation; either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/io.h>
+#include <linux/serial_core.h>
+#include <linux/serial_reg.h>
+
+void jz4750d_serial_out(struct uart_port *p, int offset, int value)
+{
+	switch (offset) {
+	case UART_FCR:
+		value |= 0x10; /* Enable uart module */
+		break;
+	case UART_IER:
+		value |= (value & 0x4) << 2;
+		break;
+	default:
+		break;
+	}
+	writeb(value, p->membase + (offset << p->regshift));
+}
diff --git a/arch/mips/jz4750d/serial.h b/arch/mips/jz4750d/serial.h
new file mode 100644
index 0000000..d381572
--- /dev/null
+++ b/arch/mips/jz4750d/serial.h
@@ -0,0 +1,22 @@
+/*
+ *  Copyright (C) 2012, Antony Pavlov <antonynpavlov@gmail.com>
+ *  JZ4750D serial support
+ *
+ *  based on JZ4740 serial support
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation; either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#ifndef __MIPS_JZ4750D_SERIAL_H__
+#define __MIPS_JZ4750D_SERIAL_H__
+
+struct uart_port;
+
+void jz4750d_serial_out(struct uart_port *p, int offset, int value);
+
+#endif
-- 
1.7.10.4

[RFC 09/13] MIPS: JZ4750D: Add prom support

[Antony Pavlov]

Add support for initializing arcs_cmdline on JZ4750D based machines and
provides a prom_putchar implementation.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
 arch/mips/jz4750d/prom.c |   67 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 67 insertions(+)
 create mode 100644 arch/mips/jz4750d/prom.c

diff --git a/arch/mips/jz4750d/prom.c b/arch/mips/jz4750d/prom.c
new file mode 100644
index 0000000..60cd1fc
--- /dev/null
+++ b/arch/mips/jz4750d/prom.c
@@ -0,0 +1,67 @@
+/*
+ *  Copyright (C) 2012, Antony Pavlov <antonynpavlov@gmail.com>
+ *  JZ4750D SoC prom code
+ *
+ *  based on JZ4740 SoC prom code
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation; either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/string.h>
+
+#include <linux/serial_reg.h>
+
+#include <asm/bootinfo.h>
+#include <asm/mach-jz4750d/base.h>
+
+static __init void jz4750d_init_cmdline(int argc, char *argv[])
+{
+	unsigned int count = COMMAND_LINE_SIZE - 1;
+	int i;
+	char *dst = &(arcs_cmdline[0]);
+	char *src;
+
+	for (i = 1; i < argc && count; ++i) {
+		src = argv[i];
+		while (*src && count) {
+			*dst++ = *src++;
+			--count;
+		}
+		*dst++ = ' ';
+	}
+	if (i > 1)
+		--dst;
+
+	*dst = 0;
+}
+
+void __init prom_init(void)
+{
+	jz4750d_init_cmdline((int)fw_arg0, (char **)fw_arg1);
+	mips_machtype = MACH_INGENIC_JZ4750D;
+}
+
+void __init prom_free_prom_memory(void)
+{
+}
+
+#define UART_REG(_reg) ((void __iomem *)CKSEG1ADDR(JZ4750D_UART1_BASE_ADDR + (_reg << 2)))
+
+void prom_putchar(char c)
+{
+	uint8_t lsr;
+
+	do {
+		lsr = readb(UART_REG(UART_LSR));
+	} while ((lsr & UART_LSR_TEMT) == 0);
+
+	writeb(c, UART_REG(UART_TX));
+}
-- 
1.7.10.4

[RFC 10/13] MIPS: JZ4750D: Add platform UART devices

[Antony Pavlov]

Add platform devices for the JZ4750D platform UART drivers.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
 arch/mips/include/asm/mach-jz4750d/platform.h |   22 +++++++
 arch/mips/jz4750d/platform.c                  |   84 +++++++++++++++++++++++++
 2 files changed, 106 insertions(+)
 create mode 100644 arch/mips/include/asm/mach-jz4750d/platform.h
 create mode 100644 arch/mips/jz4750d/platform.c

diff --git a/arch/mips/include/asm/mach-jz4750d/platform.h b/arch/mips/include/asm/mach-jz4750d/platform.h
new file mode 100644
index 0000000..255a165
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4750d/platform.h
@@ -0,0 +1,22 @@
+/*
+ *  Copyright (C) 2012, Antony Pavlov <antonynpavlov@gmail.com>
+ *  JZ4750D platform device definitions
+ *
+ *  based on JZ4740 platform device definitions
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation; either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#ifndef __JZ4750D_PLATFORM_H__
+#define __JZ4750D_PLATFORM_H__
+
+#include <linux/platform_device.h>
+
+void jz4750d_serial_device_register(void);
+
+#endif /* __JZ4750D_PLATFORM_H__ */
diff --git a/arch/mips/jz4750d/platform.c b/arch/mips/jz4750d/platform.c
new file mode 100644
index 0000000..5ac083d
--- /dev/null
+++ b/arch/mips/jz4750d/platform.c
@@ -0,0 +1,84 @@
+/*
+ *  Copyright (C) 2012, Antony Pavlov <antonynpavlov@gmail.com>
+ *  JZ4750D platform devices
+ *
+ *  based on JZ4740 platform devices
+ *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation; either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/resource.h>
+
+#include <linux/dma-mapping.h>
+
+#include <asm/mach-jz4750d/platform.h>
+#include <asm/mach-jz4750d/base.h>
+#include <asm/mach-jz4750d/irq.h>
+
+#include <linux/serial_core.h>
+#include <linux/serial_8250.h>
+
+#include "serial.h"
+#include "clock.h"
+
+/* Serial */
+#define JZ4750D_UART_DATA(_id) \
+	{ \
+		.flags = UPF_SKIP_TEST | UPF_IOREMAP | UPF_FIXED_TYPE, \
+		.iotype = UPIO_MEM, \
+		.regshift = 2, \
+		.serial_out = jz4750d_serial_out, \
+		.type = PORT_16550, \
+		.mapbase = JZ4750D_UART ## _id ## _BASE_ADDR, \
+		.irq = JZ4750D_IRQ_UART ## _id, \
+	}
+
+static struct plat_serial8250_port jz4750d_uart_data[] = {
+	JZ4750D_UART_DATA(0),
+	JZ4750D_UART_DATA(1),
+	{},
+};
+
+static struct platform_device jz4750d_uart_device = {
+	.name = "serial8250",
+	.id = 0,
+	.dev = {
+		.platform_data = jz4750d_uart_data,
+	},
+};
+
+#define JZ_REG_CLOCK_CTRL	0x00
+#define JZ_CLOCK_CTRL_KO_ENABLE	BIT(30)
+
+void jz4750d_serial_device_register(void)
+{
+	void __iomem *cpm_base = ioremap(JZ4750D_CPM_BASE_ADDR, 0x100);
+	struct plat_serial8250_port *p;
+	int uart_rate;
+
+	uart_rate = jz4750d_clock_bdata.ext_rate;
+
+	/*
+	 * FIXME
+	 * ECS bit selects the clock source between EXCLK and EXCLK/2 output
+	 * This bit is only used to APB device such as UART I2S I2C SSI SADC UDC_PHY etc.
+	 */
+
+	if (readl(cpm_base + JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_KO_ENABLE) {
+		uart_rate >>= 1;
+	}
+
+	for (p = jz4750d_uart_data; p->flags != 0; ++p)
+		p->uartclk = uart_rate;
+
+	platform_device_register(&jz4750d_uart_device);
+}
-- 
1.7.10.4

[RFC 11/13] MIPS: JZ4750D: Add Kbuild files

[Antony Pavlov]

Add the Kbuild files for the JZ4750D architecture and adds JZ4750D support
to the MIPS Kbuild files.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
 arch/mips/Kbuild.platforms |    1 +
 arch/mips/Kconfig          |   11 +++++++++++
 arch/mips/jz4750d/Kconfig  |    5 +++++
 arch/mips/jz4750d/Makefile |   10 ++++++++++
 arch/mips/jz4750d/Platform |    3 +++
 5 files changed, 30 insertions(+)
 create mode 100644 arch/mips/jz4750d/Kconfig
 create mode 100644 arch/mips/jz4750d/Makefile
 create mode 100644 arch/mips/jz4750d/Platform

diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index d64786d..e7d70fe 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -11,6 +11,7 @@ platforms += dec
 platforms += emma
 platforms += jazz
 platforms += jz4740
+platforms += jz4750d
 platforms += lantiq
 platforms += lasat
 platforms += loongson
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index faf6528..9f35486 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -224,6 +224,16 @@ config MACH_JZ4740
 	select HAVE_CLK
 	select GENERIC_IRQ_CHIP
 
+config MACH_JZ4750D
+	bool "Ingenic JZ4750D based machines"
+	select SYS_HAS_CPU_MIPS32_R1
+	select SYS_SUPPORTS_32BIT_KERNEL
+	select SYS_SUPPORTS_LITTLE_ENDIAN
+	select DMA_NONCOHERENT
+	select IRQ_CPU
+	select SYS_HAS_EARLY_PRINTK
+	select HAVE_CLK
+
 config LANTIQ
 	bool "Lantiq based platforms"
 	select DMA_NONCOHERENT
@@ -843,6 +853,7 @@ source "arch/mips/bcm47xx/Kconfig"
 source "arch/mips/bcm63xx/Kconfig"
 source "arch/mips/jazz/Kconfig"
 source "arch/mips/jz4740/Kconfig"
+source "arch/mips/jz4750d/Kconfig"
 source "arch/mips/lantiq/Kconfig"
 source "arch/mips/lasat/Kconfig"
 source "arch/mips/pmc-sierra/Kconfig"
diff --git a/arch/mips/jz4750d/Kconfig b/arch/mips/jz4750d/Kconfig
new file mode 100644
index 0000000..388eea4
--- /dev/null
+++ b/arch/mips/jz4750d/Kconfig
@@ -0,0 +1,5 @@
+choice
+	prompt "Machine type"
+	depends on MACH_JZ4750D
+
+endchoice
diff --git a/arch/mips/jz4750d/Makefile b/arch/mips/jz4750d/Makefile
new file mode 100644
index 0000000..0ecfbd4
--- /dev/null
+++ b/arch/mips/jz4750d/Makefile
@@ -0,0 +1,10 @@
+#
+# Makefile for the Ingenic JZ4750D.
+#
+
+# Object file lists.
+
+obj-y += prom.o irq.o time.o reset.o setup.o
+obj-y += clock.o platform.o timer.o serial.o
+
+obj-$(CONFIG_DEBUG_FS) += clock-debugfs.o
diff --git a/arch/mips/jz4750d/Platform b/arch/mips/jz4750d/Platform
new file mode 100644
index 0000000..2e4e050
--- /dev/null
+++ b/arch/mips/jz4750d/Platform
@@ -0,0 +1,3 @@
+platform-$(CONFIG_MACH_JZ4750D)	+= jz4750d/
+cflags-$(CONFIG_MACH_JZ4750D)	+= -I$(srctree)/arch/mips/include/asm/mach-jz4750d
+load-$(CONFIG_MACH_JZ4750D)	+= 0xffffffff80010000
-- 
1.7.10.4

[RFC 12/13] MIPS: JZ4750D: Add rzx50 board support

[Antony Pavlov]

Add support for the Ritmix RZX-50 portable game console.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
 arch/mips/jz4750d/Kconfig       |    4 ++++
 arch/mips/jz4750d/Makefile      |    3 +++
 arch/mips/jz4750d/board-rzx50.c |   41 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 48 insertions(+)
 create mode 100644 arch/mips/jz4750d/board-rzx50.c

diff --git a/arch/mips/jz4750d/Kconfig b/arch/mips/jz4750d/Kconfig
index 388eea4..243dfeb 100644
--- a/arch/mips/jz4750d/Kconfig
+++ b/arch/mips/jz4750d/Kconfig
@@ -1,5 +1,9 @@
 choice
 	prompt "Machine type"
 	depends on MACH_JZ4750D
+	default JZ4750D_RZX50
+
+config JZ4750D_RZX50
+	bool "Ritmix RZX-50"
 
 endchoice
diff --git a/arch/mips/jz4750d/Makefile b/arch/mips/jz4750d/Makefile
index 0ecfbd4..9378802 100644
--- a/arch/mips/jz4750d/Makefile
+++ b/arch/mips/jz4750d/Makefile
@@ -8,3 +8,6 @@ obj-y += prom.o irq.o time.o reset.o setup.o
 obj-y += clock.o platform.o timer.o serial.o
 
 obj-$(CONFIG_DEBUG_FS) += clock-debugfs.o
+
+# board specific support
+obj-$(CONFIG_JZ4750D_RZX50)	+= board-rzx50.o
diff --git a/arch/mips/jz4750d/board-rzx50.c b/arch/mips/jz4750d/board-rzx50.c
new file mode 100644
index 0000000..27b9e96
--- /dev/null
+++ b/arch/mips/jz4750d/board-rzx50.c
@@ -0,0 +1,41 @@
+/*
+ *  Copyright (C) 2012, Antony Pavlov <antonynpavlov@gmail.com>
+ *  Ritmix RZX-50 board setup routines.
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation; either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/mach-jz4750d/platform.h>
+
+#include "serial.h"
+#include "clock.h"
+
+struct jz4750d_clock_board_data jz4750d_clock_bdata = {
+	.ext_rate = 24000000,
+	.rtc_rate = 32768,
+};
+
+static int __init rzx50_init_platform_devices(void)
+{
+	jz4750d_serial_device_register();
+
+	return 0;
+}
+
+static int __init rzx50_board_setup(void)
+{
+	printk(KERN_ERR "Ritmix RZX-50 board setup\n");
+
+	if (rzx50_init_platform_devices())
+		panic("Failed to initalize platform devices\n");
+
+	return 0;
+}
+arch_initcall(rzx50_board_setup);
-- 
1.7.10.4

[RFC 13/13] MIPS: rzx50: Add defconfig file

[Antony Pavlov]

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
 arch/mips/configs/ritmix-rzx50_defonfig |   63 +++++++++++++++++++++++++++++++
 1 file changed, 63 insertions(+)
 create mode 100644 arch/mips/configs/ritmix-rzx50_defonfig

diff --git a/arch/mips/configs/ritmix-rzx50_defonfig b/arch/mips/configs/ritmix-rzx50_defonfig
new file mode 100644
index 0000000..fc392f5
--- /dev/null
+++ b/arch/mips/configs/ritmix-rzx50_defonfig
@@ -0,0 +1,63 @@
+CONFIG_MACH_JZ4750D=y
+CONFIG_HZ_100=y
+CONFIG_KEXEC=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE="/home/antony/git/gcwnow-buildroot.git/output/images/rootfs.cpio"
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_EMBEDDED=y
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_NETDEVICES=y
+# CONFIG_ETHERNET is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+CONFIG_LEGACY_PTY_COUNT=2
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=2
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+# CONFIG_MISC_FILESYSTEMS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_FTRACE is not set
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="mem=64M root=/dev/loop0 ro rdinit=/bin/sh console=ttyS1,57600 panic=3"
+CONFIG_CMDLINE_OVERRIDE=y
-- 
1.7.10.4

Re: [RFC 00/13] MIPS: JZ4750D: Add base support for Ingenic JZ4750D SOC

[Lars-Peter Clausen]

On 10/23/2012 07:43 PM, Antony Pavlov wrote:
> AFAIK the single known chip in Ingenic JZ4750D line is JZ4755.
> It has just the same CPU core as JZ4740, but another set of
> peripherals (though the program model for the most
> of the peripherals is the same).
> 
> +-----------------+--------------+--------------+
> |                 |   JZ4755     |    JZ4740    |
> +-----------------+--------------+--------------+
> | UART            |      3       |       4      |
> | MSC (mmc/sd)    |      2       |       1      |
> | GPIO            |     5x32     |      4x32    |
> | TCU (timers)    | 6x16 + 1x32  |      8x16    |
> | USB             |  device 2.0  |   host 1.1   |
> |                 |              |  device 2.0  |
> +-----------------+--------------+--------------+
> 
> The most significant advantage of the JZ4755 chip
> is the second MIPS core dedicated for image processing.
> Also JZ4755 is made with use of more precise technology
> and it can run on the higher clock rate (approx. 433 MHz
> for JZ4755 vs 336 MHz for JZ4740).
> 
> The JZ4755 is used in some game consoles:
> * Ritmix RZX-50;
> * Dingoo A320E/A380;
> * GameLinBox.
> 
> This patch series based on the work of Lars-Peter Clausen.
> To tell the truth it is the Lars-Peter Clausen's patches
> with some fixes and changes.
> 
> As most of the code for JZ4750D is very close to code
> for JZ4740 we can incorporate the code for JZ4750D
> to the code for JZ4740 to avoid code duplication.

Yes, definitely agreed. Most of the peripherals are similar enough that they
can be supported by a shared driver. I actually started working on this some
time ago, but never finished it, because other things took priority.
The code can be found here:
http://projects.qi-hardware.com/index.php/p/qi-kernel/source/tree/jz47xx-2.6.38/arch/mips/jz47xx

The code is based on 2.6.38 and is a bit outdated by now, but I think it gets
the idea over quite well. And most of the patches touching jz47xx related code
are still valid as well.

As for the renaming I'm not so sure if it is really necessary. We often stick
we the name for the driver or architecture version which was first supported by
the kernel and add note in Kconfig and comments that the driver also supports
other version/variants of the peripheral or SoC.

- Lars

Re: [RFC 00/13] MIPS: JZ4750D: Add base support for Ingenic JZ4750D SOC

[Steven J. Hill]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

On 10/23/2012 01:15 PM, Lars-Peter Clausen wrote:
> As for the renaming I'm not so sure if it is really necessary. We often
> stick we the name for the driver or architecture version which was first
> supported by the kernel and add note in Kconfig and comments that the
> driver also supports other version/variants of the peripheral or SoC.
> 
We currently have 'jz4740' and 'jz4770' directories. I think putting the
jz4750d code into 'jz4740' is a good idea too. Perhaps someday a 'jz47xx'
directory could be possible, but not sure it is worth the work.

- -Steve
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Comment: Using GnuPG with Mozilla - http://www.enigmail.net/

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Re: [RFC 00/13] MIPS: JZ4750D: Add base support for Ingenic JZ4750D SOC

[Lars-Peter Clausen]

On 10/23/2012 09:57 PM, Steven J. Hill wrote:
> On 10/23/2012 01:15 PM, Lars-Peter Clausen wrote:
>> As for the renaming I'm not so sure if it is really necessary. We often
>> stick we the name for the driver or architecture version which was first
>> supported by the kernel and add note in Kconfig and comments that the
>> driver also supports other version/variants of the peripheral or SoC.
> 
> We currently have 'jz4740' and 'jz4770' directories. I think putting the
> jz4750d code into 'jz4740' is a good idea too. Perhaps someday a 'jz47xx'
> directory could be possible, but not sure it is worth the work.

In my opinion it is more effort to maintain these as separate
subarchitectures. The peripherals are just to similar. Making a change to
one of the jz4740 drivers will likely require the same change to the jz4770
driver.

- Lars

Re: [RFC 11/13] MIPS: JZ4750D: Add Kbuild files

[Maarten ter Huurne]

On Tuesday 23 October 2012 21:43:59 Antony Pavlov wrote:
> Add the Kbuild files for the JZ4750D architecture and adds JZ4750D support
> to the MIPS Kbuild files.
[snip]
> diff --git a/arch/mips/jz4750d/Platform b/arch/mips/jz4750d/Platform
> new file mode 100644
> index 0000000..2e4e050
> --- /dev/null
> +++ b/arch/mips/jz4750d/Platform
> @@ -0,0 +1,3 @@
> +platform-$(CONFIG_MACH_JZ4750D)	+= jz4750d/
> +cflags-$(CONFIG_MACH_JZ4750D)	+=
> -I$(srctree)/arch/mips/include/asm/mach-jz4750d
> +load-$(CONFIG_MACH_JZ4750D)	+= 0xffffffff80010000

What is the purpose of padding the load address to 64 bits?

The reason I'm asking is that we encountered a bug with that when creating a 
u-boot image on a 32-bit host machine: the mkimage tool will only parse the 
first 8 hex digits and then inserts the wrong load address into the uImage.

Bye,
		Maarten

Re: [RFC 11/13] MIPS: JZ4750D: Add Kbuild files

[Ralf Baechle]

On Wed, Oct 24, 2012 at 06:16:35PM +0200, Maarten ter Huurne wrote:

> What is the purpose of padding the load address to 64 bits?
> 
> The reason I'm asking is that we encountered a bug with that when creating a 
> u-boot image on a 32-bit host machine: the mkimage tool will only parse the 
> first 8 hex digits and then inserts the wrong load address into the uImage.

Ld internally uses 64 bit addresses.  Also, for platforms that support
32 bit and 64 bit kernels we'd have to specify two values that only differ
by the sign extension in the upper bits.

  Ralf

Re: [RFC 11/13] MIPS: JZ4750D: Add Kbuild files

[Antony Pavlov]

On 24 October 2012 20:16, Maarten ter Huurne <maarten@treewalker.org> wrote:
> On Tuesday 23 October 2012 21:43:59 Antony Pavlov wrote:
>> Add the Kbuild files for the JZ4750D architecture and adds JZ4750D support
>> to the MIPS Kbuild files.
> [snip]
>> diff --git a/arch/mips/jz4750d/Platform b/arch/mips/jz4750d/Platform
>> new file mode 100644
>> index 0000000..2e4e050
>> --- /dev/null
>> +++ b/arch/mips/jz4750d/Platform
>> @@ -0,0 +1,3 @@
>> +platform-$(CONFIG_MACH_JZ4750D)      += jz4750d/
>> +cflags-$(CONFIG_MACH_JZ4750D)        +=
>> -I$(srctree)/arch/mips/include/asm/mach-jz4750d
>> +load-$(CONFIG_MACH_JZ4750D)  += 0xffffffff80010000
>
> What is the purpose of padding the load address to 64 bits?
>
> The reason I'm asking is that we encountered a bug with that when creating a
> u-boot image on a 32-bit host machine: the mkimage tool will only parse the
> first 8 hex digits and then inserts the wrong load address into the uImage.

I have just copied jz4740/Platform.

I don't use U-Boot, so I have never faced this problem.

-- 
Best regards,
  Antony Pavlov

Re: [RFC 11/13] MIPS: JZ4750D: Add Kbuild files

[Florian Fainelli]

On Wednesday 24 October 2012 18:16:35 Maarten ter Huurne wrote:
> On Tuesday 23 October 2012 21:43:59 Antony Pavlov wrote:
> > Add the Kbuild files for the JZ4750D architecture and adds JZ4750D support
> > to the MIPS Kbuild files.
> [snip]
> > diff --git a/arch/mips/jz4750d/Platform b/arch/mips/jz4750d/Platform
> > new file mode 100644
> > index 0000000..2e4e050
> > --- /dev/null
> > +++ b/arch/mips/jz4750d/Platform
> > @@ -0,0 +1,3 @@
> > +platform-$(CONFIG_MACH_JZ4750D)	+= jz4750d/
> > +cflags-$(CONFIG_MACH_JZ4750D)	+=
> > -I$(srctree)/arch/mips/include/asm/mach-jz4750d
> > +load-$(CONFIG_MACH_JZ4750D)	+= 0xffffffff80010000
> 
> What is the purpose of padding the load address to 64 bits?
> 
> The reason I'm asking is that we encountered a bug with that when creating a 
> u-boot image on a 32-bit host machine: the mkimage tool will only parse the 
> first 8 hex digits and then inserts the wrong load address into the uImage.

AFAIR u-boot's mkimage expects 32-bits quantities as a load address, so I would
not be surprised that using this line as-is as an input parameter to mkimage
does not give yout the expected result.
-- 
Florian

Re: [RFC 11/13] MIPS: JZ4750D: Add Kbuild files

[Maarten ter Huurne]

On Wednesday 24 October 2012 19:43:25 Florian Fainelli wrote:
> On Wednesday 24 October 2012 18:16:35 Maarten ter Huurne wrote:
> > On Tuesday 23 October 2012 21:43:59 Antony Pavlov wrote:
> > > Add the Kbuild files for the JZ4750D architecture and adds JZ4750D
> > > support to the MIPS Kbuild files.
> > 
> > [snip]
> > 
> > > diff --git a/arch/mips/jz4750d/Platform b/arch/mips/jz4750d/Platform
> > > new file mode 100644
> > > index 0000000..2e4e050
> > > --- /dev/null
> > > +++ b/arch/mips/jz4750d/Platform
> > > @@ -0,0 +1,3 @@
> > > +platform-$(CONFIG_MACH_JZ4750D)	+= jz4750d/
> > > +cflags-$(CONFIG_MACH_JZ4750D)	+=
> > > -I$(srctree)/arch/mips/include/asm/mach-jz4750d
> > > +load-$(CONFIG_MACH_JZ4750D)	+= 0xffffffff80010000
> > 
> > What is the purpose of padding the load address to 64 bits?
> > 
> > The reason I'm asking is that we encountered a bug with that when
> > creating a u-boot image on a 32-bit host machine: the mkimage tool will
> > only parse the first 8 hex digits and then inserts the wrong load
> > address into the uImage.
>
> AFAIR u-boot's mkimage expects 32-bits quantities as a load address, so I
> would not be surprised that using this line as-is as an input parameter
> to mkimage does not give yout the expected result.

The actual uImage format supports only 32-bit addresses, but mkimage is 
inconsistent in its handling of 64-bit addresses: if the tool is compiled 
for x86_64 it parses all 16 hex digits and uses the lower 32 bits, but if it 
is compiled for x86 it parses only the first 8 hex digits and the resulting 
image won't boot.

There is no "uImage" target for MIPS in the mainline kernel; we added our 
own and it indeed passes $(VMLINUX_LOAD_ADDRESS) to mkimage as-is on the 
command line. Since Ralf indicated that there are good reasons for sign 
extending the address, I think I'll have to change how it is passed to 
mkimage.

Bye,
		Maarten