From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ian Campbell Subject: Re: [PATCH 4/7] xen/arm: set the SMP bit in the ACTLR register Date: Thu, 25 Oct 2012 10:52:17 +0100 Message-ID: <1351158737.18035.142.camel@zakaz.uk.xensource.com> References: <1351091027-20740-4-git-send-email-stefano.stabellini@eu.citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1351091027-20740-4-git-send-email-stefano.stabellini@eu.citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Stefano Stabellini Cc: "xen-devel@lists.xensource.com" , "Tim (Xen.org)" List-Id: xen-devel@lists.xenproject.org On Wed, 2012-10-24 at 16:03 +0100, Stefano Stabellini wrote: > From the Cortex A15 manual: > > "Enables the processor to receive instruction cache, BTB, and TLB maintenance > operations from other processors" > > ... > > "You must set this bit before enabling the caches and MMU, or > performing any cache and TLB maintenance operations. The only time > you must clear this bit is during a processor power-down sequence" Is it considered a bug that the firmware doesn't do this? > Signed-off-by: Stefano Stabellini > --- > xen/arch/arm/head.S | 6 ++++++ > xen/include/asm-arm/processor.h | 30 ++++++++++++++++++++++++++++++ > 2 files changed, 36 insertions(+), 0 deletions(-) > > diff --git a/xen/arch/arm/head.S b/xen/arch/arm/head.S > index 3d01be0..c784f4d 100644 > --- a/xen/arch/arm/head.S > +++ b/xen/arch/arm/head.S > @@ -148,6 +148,12 @@ skip_bss: > > PRINT("- Setting up control registers -\r\n") > > + /* XXX: Cortex A15 specific */ We probably need some sort of early proc info keyed of the processor id (like Linux) has so we can push this processor specific stuff into the right places. > + /* Set up the SMP bit in ACTLR */ > + mrc CP32(r0, ACTLR) > + orr r0, r0, #(ACTLR_SMP) /* enable SMP bit*/ > + mcr CP32(r0, ACTLR) Linux does this IFF it isn't already set for some reason: #ifdef CONFIG_SMP ALT_SMP(mrc p15, 0, r0, c1, c0, 1) ALT_UP(mov r0, #(1 << 6)) @ fake it for UP tst r0, #(1 << 6) @ SMP/nAMP mode enabled? orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode orreq r0, r0, r10 @ Enable CPU-specific SMP bits mcreq p15, 0, r0, c1, c0, 1 #endif Might just relate to the "fake it up for UP" thing I suppose. > + > /* Set up memory attribute type tables */ > ldr r0, =MAIR0VAL > ldr r1, =MAIR1VAL > diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h > index 3849b23..91a5836 100644 > --- a/xen/include/asm-arm/processor.h > +++ b/xen/include/asm-arm/processor.h > @@ -34,6 +34,36 @@ > #define SCTLR_A (1<<1) > #define SCTLR_M (1<<0) > > +/* ACTLR Auxiliary Control Register */ > +#define ACTLR_SNOOP_DELAYED (1<<31) If these are CortexA15 specific then I think they ought to be ACTLR_CA15_FOO or something. And possibly in a new processor-ca15.h header instead. > +#define ACTLR_MAIN_CLOCK (1<<30) > +#define ACTLR_NEON_CLOCK (1<<29) > +#define ACTLR_NONCACHE (1<<24) > +#define ACTLR_INORDER_REQ (1<<23) > +#define ACTLR_INORDER_LOAD (1<<22) > +#define ACTLR_L2_TLB_PREFETCH (1<<21) > +#define ACTLR_L2_IPA_PA_CACHE (1<<20) > +#define ACTLR_L2_CACHE (1<<19) > +#define ACTLR_L2_PA_CACHE (1<<18) > +#define ACTLR_TLB (1<<17) > +#define ACTLR_STRONGY_ORDERED (1<<16) > +#define ACTLR_INORDER (1<<15) > +#define ACTLR_FORCE_LIM (1<<14) > +#define ACTLR_CP_FLUSH (1<<13) > +#define ACTLR_CP_PUSH (1<<12) > +#define ACTLR_LIM (1<<11) > +#define ACTLR_SER (1<<10) > +#define ACTLR_OPT (1<<9) > +#define ACTLR_WFI (1<<8) > +#define ACTLR_WFE (1<<7) > +#define ACTLR_SMP (1<<6) > +#define ACTLR_PLD (1<<5) > +#define ACTLR_IP (1<<4) > +#define ACTLR_MICRO_BTB (1<<3) > +#define ACTLR_LOOP_ONE (1<<2) > +#define ACTLR_LOOP_DISABLE (1<<1) > +#define ACTLR_BTB (1<<0) > + > #define SCTLR_BASE 0x00c50078 > #define HSCTLR_BASE 0x30c51878 >