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From: Andi Kleen <andi@firstfloor.org>
To: linux-kernel@vger.kernel.org
Cc: acme@redhat.com, peterz@infradead.org, jolsa@redhat.com,
	eranian@google.com, mingo@kernel.org, namhyung@kernel.org,
	Andi Kleen <ak@linux.intel.com>
Subject: [PATCH 09/32] perf, x86: Support LBR filtering by INTX/NOTX/ABORT v2
Date: Tue, 30 Oct 2012 17:34:00 -0700	[thread overview]
Message-ID: <1351643663-23828-10-git-send-email-andi@firstfloor.org> (raw)
In-Reply-To: <1351643663-23828-1-git-send-email-andi@firstfloor.org>

From: Andi Kleen <ak@linux.intel.com>

Add LBR filtering for branch in transaction, branch not in transaction
or transaction abort. This is exposed as new sample types.

v2: Rename ABORT to ABORTTX
Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
 arch/x86/kernel/cpu/perf_event_intel_lbr.c |   31 +++++++++++++++++++++++++--
 include/uapi/linux/perf_event.h            |    5 +++-
 2 files changed, 32 insertions(+), 4 deletions(-)

diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
index ad5af13..5455a00 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
@@ -85,9 +85,13 @@ enum {
 	X86_BR_JMP      = 1 << 9, /* jump */
 	X86_BR_IRQ      = 1 << 10,/* hw interrupt or trap or fault */
 	X86_BR_IND_CALL = 1 << 11,/* indirect calls */
+	X86_BR_ABORT    = 1 << 12,/* transaction abort */
+	X86_BR_INTX     = 1 << 13,/* in transaction */
+	X86_BR_NOTX     = 1 << 14,/* not in transaction */
 };
 
 #define X86_BR_PLM (X86_BR_USER | X86_BR_KERNEL)
+#define X86_BR_ANYTX (X86_BR_NOTX | X86_BR_INTX)
 
 #define X86_BR_ANY       \
 	(X86_BR_CALL    |\
@@ -99,6 +103,7 @@ enum {
 	 X86_BR_JCC     |\
 	 X86_BR_JMP	 |\
 	 X86_BR_IRQ	 |\
+	 X86_BR_ABORT	 |\
 	 X86_BR_IND_CALL)
 
 #define X86_BR_ALL (X86_BR_PLM | X86_BR_ANY)
@@ -347,6 +352,16 @@ static void intel_pmu_setup_sw_lbr_filter(struct perf_event *event)
 
 	if (br_type & PERF_SAMPLE_BRANCH_IND_CALL)
 		mask |= X86_BR_IND_CALL;
+
+	if (br_type & PERF_SAMPLE_BRANCH_ABORTTX)
+		mask |= X86_BR_ABORT;
+
+	if (br_type & PERF_SAMPLE_BRANCH_INTX)
+		mask |= X86_BR_INTX;
+
+	if (br_type & PERF_SAMPLE_BRANCH_NOTX)
+		mask |= X86_BR_NOTX;
+
 	/*
 	 * stash actual user request into reg, it may
 	 * be used by fixup code for some CPU
@@ -393,7 +408,8 @@ int intel_pmu_setup_lbr_filter(struct perf_event *event)
 	/*
 	 * no LBR on this PMU
 	 */
-	if (!x86_pmu.lbr_nr || x86_pmu.intel_cap.lbr_format > LBR_FORMAT_MAX_KNOWN)
+	if (!x86_pmu.lbr_nr ||
+	    x86_pmu.intel_cap.lbr_format > LBR_FORMAT_MAX_KNOWN)
 		return -EOPNOTSUPP;
 
 	/*
@@ -421,7 +437,7 @@ int intel_pmu_setup_lbr_filter(struct perf_event *event)
  * decoded (e.g., text page not present), then X86_BR_NONE is
  * returned.
  */
-static int branch_type(unsigned long from, unsigned long to)
+static int branch_type(unsigned long from, unsigned long to, int abort)
 {
 	struct insn insn;
 	void *addr;
@@ -441,6 +457,9 @@ static int branch_type(unsigned long from, unsigned long to)
 	if (from == 0 || to == 0)
 		return X86_BR_NONE;
 
+	if (abort)
+		return X86_BR_ABORT | to_plm;
+
 	if (from_plm == X86_BR_USER) {
 		/*
 		 * can happen if measuring at the user level only
@@ -577,7 +596,13 @@ intel_pmu_lbr_filter(struct cpu_hw_events *cpuc)
 		from = cpuc->lbr_entries[i].from;
 		to = cpuc->lbr_entries[i].to;
 
-		type = branch_type(from, to);
+		type = branch_type(from, to, cpuc->lbr_entries[i].abort);
+		if (type != X86_BR_NONE && (br_sel & X86_BR_ANYTX)) {
+			if (cpuc->lbr_entries[i].intx)
+				type |= X86_BR_INTX;
+			else
+				type |= X86_BR_NOTX;
+		}
 
 		/* if type does not correspond, then discard */
 		if (type == X86_BR_NONE || (br_sel & type) != type) {
diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
index 4f63c05..8e38823 100644
--- a/include/uapi/linux/perf_event.h
+++ b/include/uapi/linux/perf_event.h
@@ -155,8 +155,11 @@ enum perf_branch_sample_type {
 	PERF_SAMPLE_BRANCH_ANY_CALL	= 1U << 4, /* any call branch */
 	PERF_SAMPLE_BRANCH_ANY_RETURN	= 1U << 5, /* any return branch */
 	PERF_SAMPLE_BRANCH_IND_CALL	= 1U << 6, /* indirect calls */
+	PERF_SAMPLE_BRANCH_ABORTTX	= 1U << 7, /* transaction aborts */
+	PERF_SAMPLE_BRANCH_INTX		= 1U << 8, /* in transaction (flag) */
+	PERF_SAMPLE_BRANCH_NOTX		= 1U << 9, /* not in transaction (flag) */
 
-	PERF_SAMPLE_BRANCH_MAX		= 1U << 7, /* non-ABI */
+	PERF_SAMPLE_BRANCH_MAX		= 1U << 10, /* non-ABI */
 };
 
 #define PERF_SAMPLE_BRANCH_PLM_ALL \
-- 
1.7.7.6


  parent reply	other threads:[~2012-10-31  0:42 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-10-31  0:33 perf PMU support for Haswell v5 Andi Kleen
2012-10-31  0:33 ` [PATCH 01/32] perf, x86: Add PEBSv2 record support Andi Kleen
2012-10-31  0:33 ` [PATCH 02/32] perf, x86: Basic Haswell PMU support v2 Andi Kleen
2012-10-31  0:33 ` [PATCH 03/32] perf, x86: Basic Haswell PEBS support v3 Andi Kleen
2012-10-31  0:33 ` [PATCH 04/32] perf, x86: Support the TSX intx/intx_cp qualifiers v2 Andi Kleen
2012-10-31  0:33 ` [PATCH 05/32] perf, kvm: Support the intx/intx_cp modifiers in KVM arch perfmon emulation v3 Andi Kleen
2012-10-31 10:27   ` Gleb Natapov
2012-10-31 10:32     ` Andi Kleen
2012-10-31 10:38       ` Gleb Natapov
2012-10-31 16:43         ` Andi Kleen
2012-11-01 16:50   ` Andi Kleen
2012-10-31  0:33 ` [PATCH 06/32] perf, x86: Support PERF_SAMPLE_ADDR on Haswell Andi Kleen
2012-10-31  0:33 ` [PATCH 07/32] perf, x86: Support Haswell v4 LBR format Andi Kleen
2012-10-31  0:33 ` [PATCH 08/32] perf, x86: Disable LBR recording for unknown LBR_FMT Andi Kleen
2012-10-31  0:34 ` Andi Kleen [this message]
2012-10-31  0:34 ` [PATCH 10/32] perf, tools: Add abort_tx,no_tx,in_tx branch filter options to perf record -j v3 Andi Kleen
2012-10-31  0:34 ` [PATCH 11/32] perf, tools: Support sorting by intx, abort branch flags Andi Kleen
2012-10-31  0:34 ` [PATCH 12/32] perf, x86: Support full width counting Andi Kleen
2012-10-31  0:34 ` [PATCH 13/32] perf, x86: Avoid checkpointed counters causing excessive TSX aborts v3 Andi Kleen
2012-10-31  0:34 ` [PATCH 14/32] perf, core: Add a concept of a weightened sample Andi Kleen
2012-10-31  0:34 ` [PATCH 15/32] perf, x86: Support weight samples for PEBS Andi Kleen
2012-10-31  0:34 ` [PATCH 16/32] perf, tools: Add support for weight v3 Andi Kleen
2012-10-31  0:34 ` [PATCH 17/32] perf, tools: Handle XBEGIN like a jump Andi Kleen
2012-11-14  6:35   ` [tip:perf/core] perf annotate: " tip-bot for Andi Kleen
2012-10-31  0:34 ` [PATCH 18/32] perf, x86: Support for printing PMU state on spurious PMIs v3 Andi Kleen
2012-10-31  0:34 ` [PATCH 19/32] perf, core: Add generic transaction flags v2 Andi Kleen
2012-10-31  0:34 ` [PATCH 20/32] perf, x86: Add Haswell specific transaction flag reporting Andi Kleen
2012-10-31  0:34 ` [PATCH 21/32] perf, tools: Add support for record transaction flags v2 Andi Kleen
2012-10-31  0:34 ` [PATCH 22/32] perf, tools: Point --sort documentation to --help Andi Kleen
2012-10-31  0:34 ` [PATCH 23/32] perf, tools: Add browser support for transaction flags v2 Andi Kleen
2012-10-31  9:02   ` [PATCH] perf, tools: Fix WERROR=1 build with transction flags and fix browser Andi Kleen
2012-10-31  0:34 ` [PATCH 24/32] perf, tools: Add arbitary aliases and support names with - Andi Kleen
2012-10-31  0:34 ` [PATCH 25/32] tools, perf: Add a precise event qualifier Andi Kleen
2012-10-31  0:34 ` [PATCH 26/32] perf, x86: improve sysfs event mapping with event string Andi Kleen
2012-10-31  0:34 ` [PATCH 27/32] perf, x86: Support CPU specific sysfs events Andi Kleen
2012-11-07 14:41   ` Stephane Eranian
2012-10-31  0:34 ` [PATCH 28/32] perf, x86: Add Haswell TSX event aliases v2 Andi Kleen
2012-10-31  0:34 ` [PATCH 29/32] perf, tools: Add perf stat --transaction v2 Andi Kleen
2012-10-31  0:34 ` [PATCH 30/32] perf, x86: Add a Haswell precise instructions event v2 Andi Kleen
2012-10-31  0:34 ` [PATCH 31/32] perf, tools: Default to cpu// for events v3 Andi Kleen
2012-10-31  0:34 ` [PATCH 32/32] perf, tools: List kernel supplied event aliases in perf list v2 Andi Kleen
2012-11-10  1:27 perf PMU support for Haswell v6 Andi Kleen
2012-11-10  1:27 ` [PATCH 09/32] perf, x86: Support LBR filtering by INTX/NOTX/ABORT v2 Andi Kleen

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