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* [PATCH] x86/amd: disable way access filter on affected CPUs
@ 2012-10-24  7:56 Andre Przywara
  2012-10-24 10:46 ` Ingo Molnar
  0 siblings, 1 reply; 6+ messages in thread
From: Andre Przywara @ 2012-10-24  7:56 UTC (permalink / raw)
  To: hpa, tglx, mingo; +Cc: linux-kernel, andreas.herrmann3, Andre Przywara

The WAF may hurt the performance of some workloads, caused by
aliasing issues in the L1 cache.
Disable it on the affected CPUs.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
---
 arch/x86/kernel/cpu/amd.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index f7e98a2..1b7d165 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -631,6 +631,20 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
 		}
 	}
 
+	/*
+	 * The way access filter has a performance penalty on some workloads.
+	 * Disable it on the affected CPUs.
+	 */
+	if ((c->x86 == 0x15) &&
+	    (c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
+		u64 val;
+
+		if (!rdmsrl_safe(0xc0011021, &val) && !(val & 0x1E)) {
+			val |= 0x1E;
+			wrmsrl_safe(0xc0011021, val);
+		}
+	}
+
 	cpu_detect_cache_sizes(c);
 
 	/* Multi core CPU? */
-- 
1.7.12.1



^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH] x86/amd: disable way access filter on affected CPUs
  2012-10-24  7:56 [PATCH] x86/amd: disable way access filter on affected CPUs Andre Przywara
@ 2012-10-24 10:46 ` Ingo Molnar
  2012-10-24 15:35   ` Andre Przywara
  0 siblings, 1 reply; 6+ messages in thread
From: Ingo Molnar @ 2012-10-24 10:46 UTC (permalink / raw)
  To: Andre Przywara; +Cc: hpa, tglx, mingo, linux-kernel, andreas.herrmann3


* Andre Przywara <andre.przywara@amd.com> wrote:

> The WAF may hurt the performance of some workloads, caused by
> aliasing issues in the L1 cache.
> Disable it on the affected CPUs.
> 
> Signed-off-by: Andre Przywara <andre.przywara@amd.com>
> ---
>  arch/x86/kernel/cpu/amd.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
> index f7e98a2..1b7d165 100644
> --- a/arch/x86/kernel/cpu/amd.c
> +++ b/arch/x86/kernel/cpu/amd.c
> @@ -631,6 +631,20 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
>  		}
>  	}
>  
> +	/*
> +	 * The way access filter has a performance penalty on some workloads.
> +	 * Disable it on the affected CPUs.
> +	 */
> +	if ((c->x86 == 0x15) &&
> +	    (c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
> +		u64 val;
> +
> +		if (!rdmsrl_safe(0xc0011021, &val) && !(val & 0x1E)) {
> +			val |= 0x1E;
> +			wrmsrl_safe(0xc0011021, val);
> +		}
> +	}

Would be nice to hear more about the background of this change, 
about the amount of 'penalty' and the nature of the workloads. 
Also, it would be useful to know how the [0x02..0x1f] model 
range was chosen.

Thanks,

	Ingo

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH] x86/amd: disable way access filter on affected CPUs
  2012-10-24 10:46 ` Ingo Molnar
@ 2012-10-24 15:35   ` Andre Przywara
  2012-10-26 14:56     ` Ingo Molnar
  0 siblings, 1 reply; 6+ messages in thread
From: Andre Przywara @ 2012-10-24 15:35 UTC (permalink / raw)
  To: Ingo Molnar; +Cc: hpa, tglx, mingo, linux-kernel, andreas.herrmann3

On 10/24/2012 12:46 PM, Ingo Molnar wrote:
>
> * Andre Przywara <andre.przywara@amd.com> wrote:
>
>> The WAF may hurt the performance of some workloads, caused by
>> aliasing issues in the L1 cache.
>> Disable it on the affected CPUs.
>>
>> Signed-off-by: Andre Przywara <andre.przywara@amd.com>
>> ---
>>   arch/x86/kernel/cpu/amd.c | 14 ++++++++++++++
>>   1 file changed, 14 insertions(+)
>>
>> diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
>> index f7e98a2..1b7d165 100644
>> --- a/arch/x86/kernel/cpu/amd.c
>> +++ b/arch/x86/kernel/cpu/amd.c
>> @@ -631,6 +631,20 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
>>   		}
>>   	}
>>
>> +	/*
>> +	 * The way access filter has a performance penalty on some workloads.
>> +	 * Disable it on the affected CPUs.
>> +	 */
>> +	if ((c->x86 == 0x15) &&
>> +	    (c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
>> +		u64 val;
>> +
>> +		if (!rdmsrl_safe(0xc0011021, &val) && !(val & 0x1E)) {
>> +			val |= 0x1E;
>> +			wrmsrl_safe(0xc0011021, val);
>> +		}
>> +	}
>
> Would be nice to hear more about the background of this change,
> about the amount of 'penalty' and the nature of the workloads.

The issue is similar to that one of last year:
http://lkml.indiana.edu/hypermail/linux/kernel/1107.3/00041.html
That new patch does not replace the old one, we just need another quirk 
for newer CPUs.

The penalty depends on the circumstances, if you need a number, I can 
only tell you the 3% from last year.

The workloads would be those that access code from the same physical 
page under different virtual addresses, so different processes using the 
same libraries with ASLR or multiple instances of PIE-binaries.
The code needs to be accessed simultaneously from both cores of the same 
compute unit.

More details here:
http://developer.amd.com/Assets/SharedL1InstructionCacheonAMD15hCPU.pdf

> Also, it would be useful to know how the [0x02..0x1f] model
> range was chosen.

That is everything that has the core known as Piledriver.
That includes the AMD A-Series (aka Trinity) and the just released new 
CPUs of the FX-Series (aka Vishera).
The model numbering is a bit odd here: FX CPUs have model 2, A-Series 
has model 10h, with possible extensions to 1Fh. Hence the range of model 
ids.
Model 2 CPUs should have the fix in BIOS, but I guess there are quite 
some boxes out there which will not be updated. Better safe than sorry.

Regards,
Andre.

-- 
Andre Przywara
AMD-OSRC (Dresden)
Tel: x29712


^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH] x86/amd: disable way access filter on affected CPUs
  2012-10-24 15:35   ` Andre Przywara
@ 2012-10-26 14:56     ` Ingo Molnar
  2012-10-31 16:20       ` Andre Przywara
  0 siblings, 1 reply; 6+ messages in thread
From: Ingo Molnar @ 2012-10-26 14:56 UTC (permalink / raw)
  To: Andre Przywara; +Cc: hpa, tglx, mingo, linux-kernel, andreas.herrmann3


* Andre Przywara <andre.przywara@amd.com> wrote:

> On 10/24/2012 12:46 PM, Ingo Molnar wrote:
> >
> >* Andre Przywara <andre.przywara@amd.com> wrote:
> >
> >>The WAF may hurt the performance of some workloads, caused by
> >>aliasing issues in the L1 cache.
> >>Disable it on the affected CPUs.
> >>
> >>Signed-off-by: Andre Przywara <andre.przywara@amd.com>
> >>---
> >>  arch/x86/kernel/cpu/amd.c | 14 ++++++++++++++
> >>  1 file changed, 14 insertions(+)
> >>
> >>diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
> >>index f7e98a2..1b7d165 100644
> >>--- a/arch/x86/kernel/cpu/amd.c
> >>+++ b/arch/x86/kernel/cpu/amd.c
> >>@@ -631,6 +631,20 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
> >>  		}
> >>  	}
> >>
> >>+	/*
> >>+	 * The way access filter has a performance penalty on some workloads.
> >>+	 * Disable it on the affected CPUs.
> >>+	 */
> >>+	if ((c->x86 == 0x15) &&
> >>+	    (c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
> >>+		u64 val;
> >>+
> >>+		if (!rdmsrl_safe(0xc0011021, &val) && !(val & 0x1E)) {
> >>+			val |= 0x1E;
> >>+			wrmsrl_safe(0xc0011021, val);
> >>+		}
> >>+	}
> >
> >Would be nice to hear more about the background of this change,
> >about the amount of 'penalty' and the nature of the workloads.
> 
> The issue is similar to that one of last year:
> http://lkml.indiana.edu/hypermail/linux/kernel/1107.3/00041.html
> That new patch does not replace the old one, we just need another
> quirk for newer CPUs.
> 
> The penalty depends on the circumstances, if you need a number, I
> can only tell you the 3% from last year.
> 
> The workloads would be those that access code from the same physical
> page under different virtual addresses, so different processes using
> the same libraries with ASLR or multiple instances of PIE-binaries.
> The code needs to be accessed simultaneously from both cores of the
> same compute unit.
> 
> More details here:
> http://developer.amd.com/Assets/SharedL1InstructionCacheonAMD15hCPU.pdf
> 
> >Also, it would be useful to know how the [0x02..0x1f] model
> >range was chosen.
> 
> That is everything that has the core known as Piledriver.
> That includes the AMD A-Series (aka Trinity) and the just released
> new CPUs of the FX-Series (aka Vishera).
> The model numbering is a bit odd here: FX CPUs have model 2,
> A-Series has model 10h, with possible extensions to 1Fh. Hence the
> range of model ids.
> Model 2 CPUs should have the fix in BIOS, but I guess there are
> quite some boxes out there which will not be updated. Better safe
> than sorry.

Most of this info makes a perfect changelog entry - mind sending 
an updated v2 patch with this information included?

Thanks,

	Ingo

^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH] x86/amd: disable way access filter on affected CPUs
  2012-10-26 14:56     ` Ingo Molnar
@ 2012-10-31 16:20       ` Andre Przywara
  2012-11-01 21:33         ` [tip:x86/urgent] x86, amd: Disable way access filter on Piledriver CPUs tip-bot for Andre Przywara
  0 siblings, 1 reply; 6+ messages in thread
From: Andre Przywara @ 2012-10-31 16:20 UTC (permalink / raw)
  To: Ingo Molnar
  Cc: Thomas Gleixner, H. Peter Anvin, linux-kernel, Andreas Herrmann, osp

From: Andre Przywara <andre.przywara@amd.com>

The Way Access Filter in recent AMD CPUs may hurt the performance of
some workloads, caused by aliasing issues in the L1 cache.
This patch disables it on the affected CPUs.

The issue is similar to that one of last year:
http://lkml.indiana.edu/hypermail/linux/kernel/1107.3/00041.html
This new patch does not replace the old one, we just need another
quirk for newer CPUs.

The performance penalty without the patch depends on the
circumstances, but is a bit less than the last year's 3%.

The workloads affected would be those that access code from the same
physical page under different virtual addresses, so different
processes using the same libraries with ASLR or multiple instances of
PIE-binaries. The code needs to be accessed simultaneously from both
cores of the same compute unit.

More details can be found here:
http://developer.amd.com/Assets/SharedL1InstructionCacheonAMD15hCPU.pdf

CPUs affected are anything with the core known as Piledriver.
That includes the new parts of the AMD A-Series (aka Trinity) and the
just released new CPUs of the FX-Series (aka Vishera).
The model numbering is a bit odd here: FX CPUs have model 2,
A-Series has model 10h, with possible extensions to 1Fh. Hence the
range of model ids.

Signed-off-by: Andre Przywara <osp@andrep.de>
---
 arch/x86/kernel/cpu/amd.c |   14 ++++++++++++++
 1 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index f7e98a2..1b7d165 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -631,6 +631,20 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
 		}
 	}
 
+	/*
+	 * The way access filter has a performance penalty on some workloads.
+	 * Disable it on the affected CPUs.
+	 */
+	if ((c->x86 == 0x15) &&
+	    (c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
+		u64 val;
+
+		if (!rdmsrl_safe(0xc0011021, &val) && !(val & 0x1E)) {
+			val |= 0x1E;
+			wrmsrl_safe(0xc0011021, val);
+		}
+	}
+
 	cpu_detect_cache_sizes(c);
 
 	/* Multi core CPU? */
-- 
1.7.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [tip:x86/urgent] x86, amd: Disable way access filter on Piledriver CPUs
  2012-10-31 16:20       ` Andre Przywara
@ 2012-11-01 21:33         ` tip-bot for Andre Przywara
  0 siblings, 0 replies; 6+ messages in thread
From: tip-bot for Andre Przywara @ 2012-11-01 21:33 UTC (permalink / raw)
  To: linux-tip-commits
  Cc: linux-kernel, osp, hpa, mingo, andre.przywara, tglx, hpa

Commit-ID:  2bbf0a1427c377350f001fbc6260995334739ad7
Gitweb:     http://git.kernel.org/tip/2bbf0a1427c377350f001fbc6260995334739ad7
Author:     Andre Przywara <andre.przywara@amd.com>
AuthorDate: Wed, 31 Oct 2012 17:20:50 +0100
Committer:  H. Peter Anvin <hpa@linux.intel.com>
CommitDate: Wed, 31 Oct 2012 13:06:55 -0700

x86, amd: Disable way access filter on Piledriver CPUs

The Way Access Filter in recent AMD CPUs may hurt the performance of
some workloads, caused by aliasing issues in the L1 cache.
This patch disables it on the affected CPUs.

The issue is similar to that one of last year:
http://lkml.indiana.edu/hypermail/linux/kernel/1107.3/00041.html
This new patch does not replace the old one, we just need another
quirk for newer CPUs.

The performance penalty without the patch depends on the
circumstances, but is a bit less than the last year's 3%.

The workloads affected would be those that access code from the same
physical page under different virtual addresses, so different
processes using the same libraries with ASLR or multiple instances of
PIE-binaries. The code needs to be accessed simultaneously from both
cores of the same compute unit.

More details can be found here:
http://developer.amd.com/Assets/SharedL1InstructionCacheonAMD15hCPU.pdf

CPUs affected are anything with the core known as Piledriver.
That includes the new parts of the AMD A-Series (aka Trinity) and the
just released new CPUs of the FX-Series (aka Vishera).
The model numbering is a bit odd here: FX CPUs have model 2,
A-Series has model 10h, with possible extensions to 1Fh. Hence the
range of model ids.

Signed-off-by: Andre Przywara <osp@andrep.de>
Link: http://lkml.kernel.org/r/1351700450-9277-1-git-send-email-osp@andrep.de
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
---
 arch/x86/kernel/cpu/amd.c |   14 ++++++++++++++
 1 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index f7e98a2..1b7d165 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -631,6 +631,20 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
 		}
 	}
 
+	/*
+	 * The way access filter has a performance penalty on some workloads.
+	 * Disable it on the affected CPUs.
+	 */
+	if ((c->x86 == 0x15) &&
+	    (c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
+		u64 val;
+
+		if (!rdmsrl_safe(0xc0011021, &val) && !(val & 0x1E)) {
+			val |= 0x1E;
+			wrmsrl_safe(0xc0011021, val);
+		}
+	}
+
 	cpu_detect_cache_sizes(c);
 
 	/* Multi core CPU? */

^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2012-11-01 21:33 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2012-10-24  7:56 [PATCH] x86/amd: disable way access filter on affected CPUs Andre Przywara
2012-10-24 10:46 ` Ingo Molnar
2012-10-24 15:35   ` Andre Przywara
2012-10-26 14:56     ` Ingo Molnar
2012-10-31 16:20       ` Andre Przywara
2012-11-01 21:33         ` [tip:x86/urgent] x86, amd: Disable way access filter on Piledriver CPUs tip-bot for Andre Przywara

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