From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rui Guo Subject: [PATCH 2/3] qemu-xen-trad: Correctly expose PCH ISA bridge for IGD passthrough Date: Fri, 8 Feb 2013 00:12:07 +0800 Message-ID: <1360253528-5424-3-git-send-email-firemeteor@users.sourceforge.net> References: <1360253528-5424-1-git-send-email-firemeteor@users.sourceforge.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1360253528-5424-1-git-send-email-firemeteor@users.sourceforge.net> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: xen-devel@lists.xen.org, ian.campbell@citrix.com, stefano.stabellini@citrix.com Cc: Rui Guo List-Id: xen-devel@lists.xenproject.org The i915 driver probes chip version through PCH ISA bridge device / vendor ID. Previously, the PCH ISA bridge is exposed as PCI-PCI bridge in qemu-xen-trad, which breaks the assumption of the driver. This change fixes the issue by correctly exposing the ISA bridge to domU. Signed-off-by: Stefano Stabellini , Rui Guo Tested-by: Rui Guo Xen-devel: http://marc.info/?l=xen-devel&m=135548433715750 --- hw/pci.c | 5 ----- hw/pci.h | 5 +++++ hw/pt-graphics.c | 24 +++++++++++++++++++++--- 3 files changed, 26 insertions(+), 8 deletions(-) diff --git a/hw/pci.c b/hw/pci.c index f051de1..d371bd7 100644 --- a/hw/pci.c +++ b/hw/pci.c @@ -871,11 +871,6 @@ void pci_unplug_netifs(void) } } -typedef struct { - PCIDevice dev; - PCIBus *bus; -} PCIBridge; - void pci_bridge_write_config(PCIDevice *d, uint32_t address, uint32_t val, int len) { diff --git a/hw/pci.h b/hw/pci.h index edc58b6..c2acab9 100644 --- a/hw/pci.h +++ b/hw/pci.h @@ -222,6 +222,11 @@ struct PCIDevice { int irq_state[4]; }; +typedef struct { + PCIDevice dev; + PCIBus *bus; +} PCIBridge; + extern char direct_pci_str[]; extern int direct_pci_msitranslate; extern int direct_pci_power_mgmt; diff --git a/hw/pt-graphics.c b/hw/pt-graphics.c index c6f8869..5d4cf4a 100644 --- a/hw/pt-graphics.c +++ b/hw/pt-graphics.c @@ -3,6 +3,7 @@ */ #include "pass-through.h" +#include "pci.h" #include "pci/header.h" #include "pci/pci.h" @@ -40,9 +41,26 @@ void intel_pch_init(PCIBus *bus) did = pt_pci_host_read(pci_dev_1f, PCI_DEVICE_ID, 2); rid = pt_pci_host_read(pci_dev_1f, PCI_REVISION, 1); - if ( vid == PCI_VENDOR_ID_INTEL ) - pci_bridge_init(bus, PCI_DEVFN(0x1f, 0), vid, did, rid, - pch_map_irq, "intel_bridge_1f"); + if (vid == PCI_VENDOR_ID_INTEL) { + PCIBridge *s = (PCIBridge *)pci_register_device(bus, "intel_bridge_1f", + sizeof(PCIBridge), PCI_DEVFN(0x1f, 0), NULL, pci_bridge_write_config); + + pci_config_set_vendor_id(s->dev.config, vid); + pci_config_set_device_id(s->dev.config, did); + + s->dev.config[PCI_COMMAND] = 0x06; // command = bus master, pci mem + s->dev.config[PCI_COMMAND + 1] = 0x00; + s->dev.config[PCI_STATUS] = 0xa0; // status = fast back-to-back, 66MHz, no error + s->dev.config[PCI_STATUS + 1] = 0x00; // status = fast devsel + s->dev.config[PCI_REVISION] = rid; + s->dev.config[PCI_CLASS_PROG] = 0x00; // programming i/f + pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_ISA); + s->dev.config[PCI_LATENCY_TIMER] = 0x10; + s->dev.config[PCI_HEADER_TYPE] = 0x80; + s->dev.config[PCI_SEC_STATUS] = 0xa0; + + s->bus = pci_register_secondary_bus(&s->dev, pch_map_irq); + } } uint32_t igd_read_opregion(struct pt_dev *pci_dev) -- 1.7.10.4