From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kuo-Jung Su Date: Fri, 29 Mar 2013 15:06:23 +0800 Subject: [U-Boot] [PATCH 06/11] i2c: add FTI2C010 I2C controller support In-Reply-To: <1364540788-13943-1-git-send-email-dantesu@gmail.com> References: <1364540788-13943-1-git-send-email-dantesu@gmail.com> Message-ID: <1364540788-13943-7-git-send-email-dantesu@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Kuo-Jung Su Faraday FTI2C010 is a multi-function I2C controller which supports both master and slave mode. This patch simplily implements the master mode only. Signed-off-by: Kuo-Jung Su --- drivers/i2c/Makefile | 1 + drivers/i2c/fti2c010.c | 360 ++++++++++++++++++++++++++++++++++++++++++++++++ drivers/i2c/fti2c010.h | 68 +++++++++ 3 files changed, 429 insertions(+) create mode 100644 drivers/i2c/fti2c010.c create mode 100644 drivers/i2c/fti2c010.h diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 5dbdbe3..ed2b8c0 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -29,6 +29,7 @@ COBJS-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o COBJS-$(CONFIG_DRIVER_DAVINCI_I2C) += davinci_i2c.o COBJS-$(CONFIG_DW_I2C) += designware_i2c.o COBJS-$(CONFIG_FSL_I2C) += fsl_i2c.o +COBJS-$(CONFIG_FTI2C010) += fti2c010.o COBJS-$(CONFIG_I2C_MVTWSI) += mvtwsi.o COBJS-$(CONFIG_I2C_MV) += mv_i2c.o COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o diff --git a/drivers/i2c/fti2c010.c b/drivers/i2c/fti2c010.c new file mode 100644 index 0000000..be5e02c --- /dev/null +++ b/drivers/i2c/fti2c010.c @@ -0,0 +1,360 @@ +/* + * Faraday I2C Controller + * + * (C) Copyright 2010 Faraday Technology + * Dante Su + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + */ + +#include +#include + +#include "fti2c010.h" + +#define I2C_RD 1 +#define I2C_WR 0 + +struct fti2c010_chip { + uint32_t bus; + uint32_t speed; + uint32_t iobase; +}; + +#if defined(CONFIG_HARD_I2C) + +static struct fti2c010_chip fti2c010_info[] = { +#ifdef CONFIG_I2C_MULTI_BUS +# ifdef CONFIG_FTI2C010_BASE0 + { + .bus = 0, + .speed = 0, + .iobase = CONFIG_FTI2C010_BASE0, + }, +# endif +# ifdef CONFIG_FTI2C010_BASE1 + { + .bus = 1, + .speed = 0, + .iobase = CONFIG_FTI2C010_BASE1, + }, +# endif +# ifdef CONFIG_FTI2C010_BASE2 + { + .bus = 2, + .speed = 0, + .iobase = CONFIG_FTI2C010_BASE2, + }, +# endif +# ifdef CONFIG_FTI2C010_BASE3 + { + .bus = 3, + .speed = 0, + .iobase = CONFIG_FTI2C010_BASE3, + }, +# endif +#else /* #ifdef CONFIG_I2C_MULTI_BUS */ + { + .bus = 0, + .speed = 0, + .iobase = CONFIG_FTI2C010_BASE, + }, +#endif /* #ifdef CONFIG_I2C_MULTI_BUS */ +}; + +static struct fti2c010_chip *priv = fti2c010_info; + +/* Register access macros */ +#define I2C_REG32(priv, off) \ + *(volatile uint32_t *)((priv)->iobase + (off)) + +static int fti2c010_wait(uint32_t mask) +{ + int ret = -1; + uint32_t stat, t; + + for (t = get_timer(0); get_timer(t) < 100; ) { + stat = I2C_REG32(priv, REG_SR); + if ((stat & mask) == mask) { + ret = 0; + break; + } + } + + return ret; +} + +/* + * u-boot I2C API + */ + +/* + * Initialization, must be called once on start up, may be called + * repeatedly to change the speed and slave addresses. + */ +void i2c_init(int speed, int slaveaddr) +{ + if (speed || priv->speed == 0) + i2c_set_bus_speed(speed); +} + +/* + * Probe the given I2C chip address. Returns 0 if a chip responded, + * not 0 on failure. + */ +int i2c_probe(uchar chip) +{ + int rc; + + i2c_init(0, chip); + + /* 1. Select slave device (7bits Address + 1bit R/W) */ + I2C_REG32(priv, REG_DR) = (chip << 1) + I2C_WR; + I2C_REG32(priv, REG_CR) = CR_ENABLE | CR_TBEN | CR_START; + rc = fti2c010_wait(SR_DT); + if (rc) + return rc; + + /* 2. Select device register */ + I2C_REG32(priv, REG_DR) = 0; + I2C_REG32(priv, REG_CR) = CR_ENABLE | CR_TBEN; + rc = fti2c010_wait(SR_DT); + + return rc; +} + +/* + * Read/Write interface: + * chip: I2C chip address, range 0..127 + * addr: Memory (register) address within the chip + * alen: Number of bytes to use for addr (typically 1, 2 for larger + * memories, 0 for register type devices with only one + * register) + * buffer: Where to read/write the data + * len: How many bytes to read/write + * + * Returns: 0 on success, not 0 on failure + */ +int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) +{ + int rc, pos; + uchar paddr[4]; + + i2c_init(0, chip); + + paddr[0] = (addr >> 0) & 0xFF; + paddr[1] = (addr >> 8) & 0xFF; + paddr[2] = (addr >> 16) & 0xFF; + paddr[3] = (addr >> 24) & 0xFF; + + /* + * Phase A. Set register address + */ + + /* A.1 Select slave device (7bits Address + 1bit R/W) */ + I2C_REG32(priv, REG_DR) = (chip << 1) + I2C_WR; + I2C_REG32(priv, REG_CR) = CR_ENABLE | CR_TBEN | CR_START; + rc = fti2c010_wait(SR_DT); + if (rc) + return rc; + + /* A.2 Select device register */ + for (pos = 0; pos < alen; ++pos) { + uint32_t ctrl = CR_ENABLE | CR_TBEN; + I2C_REG32(priv, REG_DR) = paddr[pos]; + I2C_REG32(priv, REG_CR) = ctrl; + rc = fti2c010_wait(SR_DT); + if (rc) + return rc; + } + + /* + * Phase B. Get register data + */ + + /* B.1 Select slave device (7bits Address + 1bit R/W) */ + I2C_REG32(priv, REG_DR) = (chip << 1) + I2C_RD; + I2C_REG32(priv, REG_CR) = CR_ENABLE | CR_TBEN | CR_START; + rc = fti2c010_wait(SR_DT); + if (rc) + return rc; + + /* B.2 Get register data */ + for (pos = 0; pos < len; ++pos) { + uint32_t ctrl = CR_ENABLE | CR_TBEN; + uint32_t stat = SR_DR; + if (pos == len - 1) { + ctrl |= CR_NAK | CR_STOP; + stat |= SR_ACK; + } + I2C_REG32(priv, REG_CR) = ctrl; + rc = fti2c010_wait(stat); + if (rc) + break; + buf[pos] = (uchar)(I2C_REG32(priv, REG_DR) & 0xFF); + } + + return rc; +} + +/* + * Read/Write interface: + * chip: I2C chip address, range 0..127 + * addr: Memory (register) address within the chip + * alen: Number of bytes to use for addr (typically 1, 2 for larger + * memories, 0 for register type devices with only one + * register) + * buffer: Where to read/write the data + * len: How many bytes to read/write + * + * Returns: 0 on success, not 0 on failure + */ +int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) +{ + int rc, pos; + uchar paddr[4]; + + i2c_init(0, chip); + + paddr[0] = (addr >> 0) & 0xFF; + paddr[1] = (addr >> 8) & 0xFF; + paddr[2] = (addr >> 16) & 0xFF; + paddr[3] = (addr >> 24) & 0xFF; + + /* + * Phase A. Set register address + */ + + /* A.1 Select slave device (7bits Address + 1bit R/W) */ + I2C_REG32(priv, REG_DR) = (chip << 1) + I2C_WR; + I2C_REG32(priv, REG_CR) = CR_ENABLE | CR_TBEN | CR_START; + rc = fti2c010_wait(SR_DT); + if (rc) + return rc; + + /* A.2 Select device register */ + for (pos = 0; pos < alen; ++pos) { + uint32_t ctrl = CR_ENABLE | CR_TBEN; + I2C_REG32(priv, REG_DR) = paddr[pos]; + I2C_REG32(priv, REG_CR) = ctrl; + rc = fti2c010_wait(SR_DT); + if (rc) + return rc; + } + + /* + * Phase B. Set register data + */ + + for (pos = 0; pos < len; ++pos) { + uint32_t ctrl = CR_ENABLE | CR_TBEN; + if (pos == len - 1) + ctrl |= CR_STOP; + I2C_REG32(priv, REG_DR) = buf[pos]; + I2C_REG32(priv, REG_CR) = ctrl; + rc = fti2c010_wait(SR_DT); + if (rc) + break; + } + + return rc; +} + +/* + * Functions for setting the current I2C bus and its speed + */ +#ifdef CONFIG_I2C_MULTI_BUS + +/* + * i2c_set_bus_num: + * + * Change the active I2C bus. Subsequent read/write calls will + * go to this one. + * + * bus - bus index, zero based + * + * Returns: 0 on success, not 0 on failure + * + */ +int i2c_set_bus_num(unsigned int bus) +{ + if (bus >= sizeof(fti2c010_info) / sizeof(fti2c010_info[0])) + return -1; + priv = fti2c010_info + bus; + i2c_init(5000, 0); + return 0; +} + +/* + * i2c_get_bus_num: + * + * Returns index of currently active I2C bus. Zero-based. + */ + +unsigned int i2c_get_bus_num(void) +{ + return priv->bus; +} + +#endif /* #ifdef CONFIG_I2C_MULTI_BUS */ + +/* + * i2c_set_bus_speed: + * + * Change the speed of the active I2C bus + * + * speed - bus speed in Hz + * + * Returns: 0 on success, not 0 on failure + * + */ +int i2c_set_bus_speed(unsigned int speed) +{ +#ifdef CONFIG_FTI2C010_SCLK + unsigned long apb = CONFIG_FTI2C010_SCLK; +#else + unsigned long apb = clk_get_rate("I2C"); +#endif + unsigned long div = 0x640; + unsigned long gsr = 0; + unsigned long tsr = 0x20; + unsigned long t; + + I2C_REG32(priv, REG_CR) = 1; + t = get_timer(0); + while (get_timer(t) < 100) { + if (I2C_REG32(priv, REG_CR) & 1) + continue; + break; + } + + /* SCLout = PCLK/(2*(COUNT + 2) + GSR) */ + priv->speed = apb / (2 * (div + 2) + gsr); + + if (speed > 0) { + for (div = 0; div < 0x1000000; ++div) { + priv->speed = apb / (2 * (div + 2) + gsr); + if (priv->speed < speed) + break; + } + } + + I2C_REG32(priv, REG_TGSR) = (gsr << 10) | tsr; + I2C_REG32(priv, REG_CDR) = div; + + return 0; +} + +/* + * i2c_get_bus_speed: + * + * Returns speed of currently active I2C bus in Hz + */ + +unsigned int i2c_get_bus_speed(void) +{ + return priv->speed; +} + +#endif /* CONFIG_HARD_I2C */ diff --git a/drivers/i2c/fti2c010.h b/drivers/i2c/fti2c010.h new file mode 100644 index 0000000..704b3a2 --- /dev/null +++ b/drivers/i2c/fti2c010.h @@ -0,0 +1,68 @@ +/* + * Faraday I2C Controller + * + * (C) Copyright 2010 Faraday Technology + * Dante Su + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + */ + +#ifndef __FTI2C010_H +#define __FTI2C010_H + +/* + * FTI2C010 registers + */ +#define REG_CR 0x00 /* control register */ +#define REG_SR 0x04 /* status register */ +#define REG_CDR 0x08 /* clock division register */ +#define REG_DR 0x0C /* data register */ +#define REG_SAR 0x10 /* slave address register */ +#define REG_TGSR 0x14 /* time & glitch suppression register */ +#define REG_BMR 0x18 /* bus monitor register */ +#define REG_REVR 0x30 /* revision register */ + +/* + * REG_CTRL + */ +#define CR_ALIEN 0x2000 /* Arbitration lose */ +#define CR_SAMIEN 0x1000 /* slave address match */ +#define CR_STOPIEN 0x800 /* stop condition */ +#define CR_BERRIEN 0x400 /* non ACK response */ +#define CR_DRIEN 0x200 /* data receive */ +#define CR_DTIEN 0x100 /* data transmit */ +#define CR_TBEN 0x80 /* transfer byte enable */ +#define CR_NAK 0x40 /* with this bit set, fti2c010 will not drive ACK signal */ +#define CR_STOP 0x20 /* stop */ +#define CR_START 0x10 /* start */ +#define CR_GCEN 0x8 /* general call */ +#define CR_SCLEN 0x4 /* enable clock */ +#define CR_I2CEN 0x2 /* enable I2C */ +#define CR_I2CRST 0x1 /* reset I2C */ +#define CR_ENABLE \ + (CR_ALIEN | CR_SAMIEN | CR_STOPIEN | CR_BERRIEN \ + | CR_DRIEN | CR_DTIEN | CR_SCLEN | CR_I2CEN) + +/* + * REG_STAT + */ +#define SR_CLRAL 0x400 +#define SR_CLRGC 0x200 +#define SR_CLRSAM 0x100 +#define SR_CLRSTOP 0x80 +#define SR_CLRBERR 0x40 +#define SR_DR 0x20 /* DR received one new data byte */ +#define SR_DT 0x10 /* DR trandmitted one new data byte */ +#define SR_BB 0x8 +#define SR_BUSY 0x4 +#define SR_ACK 0x2 +#define SR_RW 0x1 + +/* + * REG_BMR + */ +#define BMR_SCL 0x2 +#define BMR_SDA 0x1 + +#endif /* EOF */ -- 1.7.9.5