From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paulo Zanoni Subject: [PATCH 6/9] drm/i915: make intel_ddi_get_cdclk_freq return values in KHz Date: Fri, 3 May 2013 17:23:42 -0300 Message-ID: <1367612625-4823-7-git-send-email-przanoni@gmail.com> References: <1367612625-4823-1-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-vc0-f175.google.com (mail-vc0-f175.google.com [209.85.220.175]) by gabe.freedesktop.org (Postfix) with ESMTP id 62BC5E5DED for ; Fri, 3 May 2013 13:24:20 -0700 (PDT) Received: by mail-vc0-f175.google.com with SMTP id lf10so1786996vcb.34 for ; Fri, 03 May 2013 13:24:20 -0700 (PDT) In-Reply-To: <1367612625-4823-1-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org From: Paulo Zanoni With this, that 338 can finally become the correct 337500. Due to the change we need to adjust the intel_dp_aux_ch function to set the correct value, so adjust the division and also use DIV_ROUND_CLOSEST instead of the old "round down" behavior because the spec says the value "should be programmed to get as close as possible to the ideal rate of 2MHz". Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_ddi.c | 10 +++++----- drivers/gpu/drm/i915/intel_dp.c | 3 ++- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 21fb852..e5b1b63 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1335,14 +1335,14 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder) int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv) { if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT) - return 450; + return 450000; else if ((I915_READ(LCPLL_CTL) & LCPLL_CLK_FREQ_MASK) == LCPLL_CLK_FREQ_450) - return 450; + return 450000; else if (IS_ULT(dev_priv->dev)) - return 338; + return 337500; else - return 540; + return 540000; } void intel_ddi_pll_init(struct drm_device *dev) @@ -1355,7 +1355,7 @@ void intel_ddi_pll_init(struct drm_device *dev) * Don't even try to turn it on. */ - DRM_DEBUG_KMS("CDCLK running at %dMHz\n", + DRM_DEBUG_KMS("CDCLK running at %dKHz\n", intel_ddi_get_cdclk_freq(dev_priv)); if (val & LCPLL_CD_SOURCE_FCLK) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index a293523..3df1383 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -346,7 +346,8 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, */ if (is_cpu_edp(intel_dp)) { if (HAS_DDI(dev)) - aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1; + aux_clock_divider = DIV_ROUND_CLOSEST( + intel_ddi_get_cdclk_freq(dev_priv), 2000); else if (IS_VALLEYVIEW(dev)) aux_clock_divider = 100; else if (IS_GEN6(dev) || IS_GEN7(dev)) -- 1.7.10.4