From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paulo Zanoni Subject: [PATCH 7/9] drm/i915: set the IPS linetime watermark Date: Fri, 3 May 2013 17:23:43 -0300 Message-ID: <1367612625-4823-8-git-send-email-przanoni@gmail.com> References: <1367612625-4823-1-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ve0-f177.google.com (mail-ve0-f177.google.com [209.85.128.177]) by gabe.freedesktop.org (Postfix) with ESMTP id B48A4E5EA2 for ; Fri, 3 May 2013 13:24:22 -0700 (PDT) Received: by mail-ve0-f177.google.com with SMTP id jw11so1881537veb.36 for ; Fri, 03 May 2013 13:24:22 -0700 (PDT) In-Reply-To: <1367612625-4823-1-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org From: Paulo Zanoni Remove the "placeholder" comment and set the actual value described by the specification. We still don't enable IPS, but it won't hurt to already have the value set here. While at it, fully set the register value instead of just masking the values we're changing. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_pm.c | 22 +++++++--------------- 1 file changed, 7 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 3ca020c..59bac2e 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2022,7 +2022,7 @@ haswell_update_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc) enum pipe pipe = intel_crtc->pipe; struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; int target_clock; - u32 temp; + u32 linetime, ips_linetime; if (!intel_crtc_active(crtc)) { I915_WRITE(PIPE_WM_LINETIME(pipe), 0); @@ -2034,24 +2034,16 @@ haswell_update_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc) else target_clock = intel_crtc->config.adjusted_mode.clock; - temp = I915_READ(PIPE_WM_LINETIME(pipe)); - temp &= ~PIPE_WM_LINETIME_MASK; - /* The WM are computed with base on how long it takes to fill a single * row at the given clock rate, multiplied by 8. * */ - temp |= PIPE_WM_LINETIME_TIME( - DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, target_clock)); - - /* IPS watermarks are only used by pipe A, and are ignored by - * pipes B and C. They are calculated similarly to the common - * linetime values, except that we are using CD clock frequency - * in MHz instead of pixel rate for the division. - * - * This is a placeholder for the IPS watermark calculation code. - */ + linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, target_clock); + ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, + intel_ddi_get_cdclk_freq(dev_priv)); - I915_WRITE(PIPE_WM_LINETIME(pipe), temp); + I915_WRITE(PIPE_WM_LINETIME(pipe), + PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | + PIPE_WM_LINETIME_TIME(linetime)); } static void haswell_update_wm(struct drm_device *dev) -- 1.7.10.4