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From: Jun Nakajima <jun.nakajima@intel.com>
To: kvm@vger.kernel.org
Subject: [PATCH v2 12/13] nEPT: Move is_rsvd_bits_set() to paging_tmpl.h
Date: Mon,  6 May 2013 00:04:31 -0700	[thread overview]
Message-ID: <1367823872-25895-12-git-send-email-jun.nakajima@intel.com> (raw)
In-Reply-To: <1367823872-25895-11-git-send-email-jun.nakajima@intel.com>

Move is_rsvd_bits_set() to paging_tmpl.h so that it can be used to check
reserved bits in EPT page table entries as well.

Signed-off-by: Jun Nakajima <jun.nakajima@intel.com>
Signed-off-by: Xinhao Xu <xinhao.xu@intel.com>
---
 arch/x86/kvm/mmu.c         |  8 --------
 arch/x86/kvm/paging_tmpl.h | 12 ++++++++++--
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
index 99bfc5e..054c68b 100644
--- a/arch/x86/kvm/mmu.c
+++ b/arch/x86/kvm/mmu.c
@@ -2460,14 +2460,6 @@ static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
 	mmu_free_roots(vcpu);
 }
 
-static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
-{
-	int bit7;
-
-	bit7 = (gpte >> 7) & 1;
-	return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0;
-}
-
 static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
 				     bool no_dirty_log)
 {
diff --git a/arch/x86/kvm/paging_tmpl.h b/arch/x86/kvm/paging_tmpl.h
index 51dca23..777d5d7 100644
--- a/arch/x86/kvm/paging_tmpl.h
+++ b/arch/x86/kvm/paging_tmpl.h
@@ -124,11 +124,19 @@ static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
 }
 #endif
 
+static bool FNAME(is_rsvd_bits_set)(struct kvm_mmu *mmu, u64 gpte, int level)
+{
+	int bit7;
+
+	bit7 = (gpte >> 7) & 1;
+	return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0;
+}
+
 static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu,
 				  struct kvm_mmu_page *sp, u64 *spte,
 				  u64 gpte)
 {
-	if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL))
+	if (FNAME(is_rsvd_bits_set)(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL))
 		goto no_present;
 
 	if (!is_present_gpte(gpte))
@@ -279,7 +287,7 @@ retry_walk:
 		if (unlikely(!is_present_gpte(pte)))
 			goto error;
 
-		if (unlikely(is_rsvd_bits_set(&vcpu->arch.mmu, pte,
+		if (unlikely(FNAME(is_rsvd_bits_set)(&vcpu->arch.mmu, pte,
 					      walker->level))) {
 			errcode |= PFERR_RSVD_MASK | PFERR_PRESENT_MASK;
 			goto error;
-- 
1.8.1.2


  reply	other threads:[~2013-05-06  7:05 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-05-06  7:04 [PATCH v2 01/13] nEPT: Support LOAD_IA32_EFER entry/exit controls for L1 Jun Nakajima
2013-05-06  7:04 ` [PATCH v2 02/13] nEPT: Move gpte_access() and prefetch_invalid_gpte() to paging_tmpl.h Jun Nakajima
2013-05-06  7:04   ` [PATCH v2 03/13] nEPT: Add EPT tables support " Jun Nakajima
2013-05-06  7:04     ` [PATCH v2 04/13] nEPT: Define EPT-specific link_shadow_page() Jun Nakajima
2013-05-06  7:04       ` [PATCH v2 05/13] nEPT: MMU context for nested EPT Jun Nakajima
2013-05-06  7:04         ` [PATCH v2 06/13] nEPT: Fix cr3 handling in nested exit and entry Jun Nakajima
2013-05-06  7:04           ` [PATCH v2 07/13] nEPT: Fix wrong test in kvm_set_cr3 Jun Nakajima
2013-05-06  7:04             ` [PATCH v2 08/13] nEPT: Some additional comments Jun Nakajima
2013-05-06  7:04               ` [PATCH v2 09/13] nEPT: Advertise EPT to L1 Jun Nakajima
2013-05-06  7:04                 ` [PATCH v2 10/13] nEPT: Nested INVEPT Jun Nakajima
2013-05-06  7:04                   ` [PATCH v2 11/13] nEPT: Miscelleneous cleanups Jun Nakajima
2013-05-06  7:04                     ` Jun Nakajima [this message]
2013-05-06  7:04                       ` [PATCH v2 13/13] nEPT: Inject EPT violation/misconfigration Jun Nakajima
2013-05-06  7:13 ` [PATCH v2 01/13] nEPT: Support LOAD_IA32_EFER entry/exit controls for L1 Jan Kiszka

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