From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marc Zyngier Subject: [PATCH v4 22/32] arm64: KVM: define 32bit specific registers Date: Tue, 14 May 2013 15:13:50 +0100 Message-ID: <1368540840-26750-23-git-send-email-marc.zyngier@arm.com> References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com> Content-Type: text/plain; charset=WINDOWS-1252 Content-Transfer-Encoding: quoted-printable Cc: catalin.marinas@arm.com, will.deacon@arm.com, pbonzini@redhat.com, gleb@redhat.com, Christopher Covington To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org Return-path: Received: from service87.mimecast.com ([91.220.42.44]:48865 "EHLO service87.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757788Ab3ENOQO (ORCPT ); Tue, 14 May 2013 10:16:14 -0400 In-Reply-To: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com> Sender: kvm-owner@vger.kernel.org List-ID: Define the 32bit specific registers (SPSRs, cp15...). Most CPU registers are directly mapped to a 64bit register (r0->x0...). Only the SPSRs have separate registers. cp15 registers are also mapped into their 64bit counterpart in most cases. Reviewed-by: Christopher Covington Signed-off-by: Marc Zyngier --- arch/arm64/include/asm/kvm_asm.h | 38 +++++++++++++++++++++++++++++++++++= ++- arch/arm64/include/asm/kvm_host.h | 5 ++++- arch/arm64/include/uapi/asm/kvm.h | 7 ++++++- 3 files changed, 47 insertions(+), 3 deletions(-) diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_= asm.h index 591ac21..c92de41 100644 --- a/arch/arm64/include/asm/kvm_asm.h +++ b/arch/arm64/include/asm/kvm_asm.h @@ -42,7 +42,43 @@ #define=09TPIDR_EL1=0918=09/* Thread ID, Privileged */ #define=09AMAIR_EL1=0919=09/* Aux Memory Attribute Indirection Register */ #define=09CNTKCTL_EL1=0920=09/* Timer Control Register (EL1) */ -#define=09NR_SYS_REGS=0921 +/* 32bit specific registers. Keep them at the end of the range */ +#define=09DACR32_EL2=0921=09/* Domain Access Control Register */ +#define=09IFSR32_EL2=0922=09/* Instruction Fault Status Register */ +#define=09FPEXC32_EL2=0923=09/* Floating-Point Exception Control Register = */ +#define=09DBGVCR32_EL2=0924=09/* Debug Vector Catch Register */ +#define=09TEECR32_EL1=0925=09/* ThumbEE Configuration Register */ +#define=09TEEHBR32_EL1=0926=09/* ThumbEE Handler Base Register */ +#define=09NR_SYS_REGS=0927 + +/* 32bit mapping */ +#define c0_MPIDR=09(MPIDR_EL1 * 2)=09/* MultiProcessor ID Register */ +#define c0_CSSELR=09(CSSELR_EL1 * 2)/* Cache Size Selection Register */ +#define c1_SCTLR=09(SCTLR_EL1 * 2)=09/* System Control Register */ +#define c1_ACTLR=09(ACTLR_EL1 * 2)=09/* Auxiliary Control Register */ +#define c1_CPACR=09(CPACR_EL1 * 2)=09/* Coprocessor Access Control */ +#define c2_TTBR0=09(TTBR0_EL1 * 2)=09/* Translation Table Base Register 0 = */ +#define c2_TTBR0_high=09(c2_TTBR0 + 1)=09/* TTBR0 top 32 bits */ +#define c2_TTBR1=09(TTBR1_EL1 * 2)=09/* Translation Table Base Register 1 = */ +#define c2_TTBR1_high=09(c2_TTBR1 + 1)=09/* TTBR1 top 32 bits */ +#define c2_TTBCR=09(TCR_EL1 * 2)=09/* Translation Table Base Control R. */ +#define c3_DACR=09=09(DACR32_EL2 * 2)/* Domain Access Control Register */ +#define c5_DFSR=09=09(ESR_EL1 * 2)=09/* Data Fault Status Register */ +#define c5_IFSR=09=09(IFSR32_EL2 * 2)/* Instruction Fault Status Register = */ +#define c5_ADFSR=09(AFSR0_EL1 * 2)=09/* Auxiliary Data Fault Status R */ +#define c5_AIFSR=09(AFSR1_EL1 * 2)=09/* Auxiliary Instr Fault Status R */ +#define c6_DFAR=09=09(FAR_EL1 * 2)=09/* Data Fault Address Register */ +#define c6_IFAR=09=09(c6_DFAR + 1)=09/* Instruction Fault Address Register= */ +#define c10_PRRR=09(MAIR_EL1 * 2)=09/* Primary Region Remap Register */ +#define c10_NMRR=09(c10_PRRR + 1)=09/* Normal Memory Remap Register */ +#define c12_VBAR=09(VBAR_EL1 * 2)=09/* Vector Base Address Register */ +#define c13_CID=09=09(CONTEXTIDR_EL1 * 2)=09/* Context ID Register */ +#define c13_TID_URW=09(TPIDR_EL0 * 2)=09/* Thread ID, User R/W */ +#define c13_TID_URO=09(TPIDRRO_EL0 * 2)/* Thread ID, User R/O */ +#define c13_TID_PRIV=09(TPIDR_EL1 * 2)=09/* Thread ID, Privileged */ +#define c10_AMAIR=09(AMAIR_EL1 * 2)=09/* Aux Memory Attr Indirection Reg *= / +#define c14_CNTKCTL=09(CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */ +#define NR_CP15_REGS=09(NR_SYS_REGS * 2) =20 #define ARM_EXCEPTION_IRQ=09 0 #define ARM_EXCEPTION_TRAP=09 1 diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 2fdeb32..3f5830b 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -84,7 +84,10 @@ struct kvm_vcpu_fault_info { =20 struct kvm_cpu_context { =09struct kvm_regs=09gp_regs; -=09u64 sys_regs[NR_SYS_REGS]; +=09union { +=09=09u64 sys_regs[NR_SYS_REGS]; +=09=09u32 cp15[NR_CP15_REGS]; +=09}; }; =20 typedef struct kvm_cpu_context kvm_cpu_context_t; diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/as= m/kvm.h index fb60f90..5b1110c 100644 --- a/arch/arm64/include/uapi/asm/kvm.h +++ b/arch/arm64/include/uapi/asm/kvm.h @@ -23,7 +23,12 @@ #define __ARM_KVM_H__ =20 #define KVM_SPSR_EL1=090 -#define KVM_NR_SPSR=091 +#define KVM_SPSR_SVC=09KVM_SPSR_EL1 +#define KVM_SPSR_ABT=091 +#define KVM_SPSR_UND=092 +#define KVM_SPSR_IRQ=093 +#define KVM_SPSR_FIQ=094 +#define KVM_NR_SPSR=095 =20 #ifndef __ASSEMBLY__ #include --=20 1.8.2.3 From mboxrd@z Thu Jan 1 00:00:00 1970 From: marc.zyngier@arm.com (Marc Zyngier) Date: Tue, 14 May 2013 15:13:50 +0100 Subject: [PATCH v4 22/32] arm64: KVM: define 32bit specific registers In-Reply-To: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com> References: <1368540840-26750-1-git-send-email-marc.zyngier@arm.com> Message-ID: <1368540840-26750-23-git-send-email-marc.zyngier@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Define the 32bit specific registers (SPSRs, cp15...). Most CPU registers are directly mapped to a 64bit register (r0->x0...). Only the SPSRs have separate registers. cp15 registers are also mapped into their 64bit counterpart in most cases. Reviewed-by: Christopher Covington Signed-off-by: Marc Zyngier --- arch/arm64/include/asm/kvm_asm.h | 38 +++++++++++++++++++++++++++++++++++++- arch/arm64/include/asm/kvm_host.h | 5 ++++- arch/arm64/include/uapi/asm/kvm.h | 7 ++++++- 3 files changed, 47 insertions(+), 3 deletions(-) diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h index 591ac21..c92de41 100644 --- a/arch/arm64/include/asm/kvm_asm.h +++ b/arch/arm64/include/asm/kvm_asm.h @@ -42,7 +42,43 @@ #define TPIDR_EL1 18 /* Thread ID, Privileged */ #define AMAIR_EL1 19 /* Aux Memory Attribute Indirection Register */ #define CNTKCTL_EL1 20 /* Timer Control Register (EL1) */ -#define NR_SYS_REGS 21 +/* 32bit specific registers. Keep them at the end of the range */ +#define DACR32_EL2 21 /* Domain Access Control Register */ +#define IFSR32_EL2 22 /* Instruction Fault Status Register */ +#define FPEXC32_EL2 23 /* Floating-Point Exception Control Register */ +#define DBGVCR32_EL2 24 /* Debug Vector Catch Register */ +#define TEECR32_EL1 25 /* ThumbEE Configuration Register */ +#define TEEHBR32_EL1 26 /* ThumbEE Handler Base Register */ +#define NR_SYS_REGS 27 + +/* 32bit mapping */ +#define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */ +#define c0_CSSELR (CSSELR_EL1 * 2)/* Cache Size Selection Register */ +#define c1_SCTLR (SCTLR_EL1 * 2) /* System Control Register */ +#define c1_ACTLR (ACTLR_EL1 * 2) /* Auxiliary Control Register */ +#define c1_CPACR (CPACR_EL1 * 2) /* Coprocessor Access Control */ +#define c2_TTBR0 (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */ +#define c2_TTBR0_high (c2_TTBR0 + 1) /* TTBR0 top 32 bits */ +#define c2_TTBR1 (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */ +#define c2_TTBR1_high (c2_TTBR1 + 1) /* TTBR1 top 32 bits */ +#define c2_TTBCR (TCR_EL1 * 2) /* Translation Table Base Control R. */ +#define c3_DACR (DACR32_EL2 * 2)/* Domain Access Control Register */ +#define c5_DFSR (ESR_EL1 * 2) /* Data Fault Status Register */ +#define c5_IFSR (IFSR32_EL2 * 2)/* Instruction Fault Status Register */ +#define c5_ADFSR (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */ +#define c5_AIFSR (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */ +#define c6_DFAR (FAR_EL1 * 2) /* Data Fault Address Register */ +#define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */ +#define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */ +#define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */ +#define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */ +#define c13_CID (CONTEXTIDR_EL1 * 2) /* Context ID Register */ +#define c13_TID_URW (TPIDR_EL0 * 2) /* Thread ID, User R/W */ +#define c13_TID_URO (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */ +#define c13_TID_PRIV (TPIDR_EL1 * 2) /* Thread ID, Privileged */ +#define c10_AMAIR (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */ +#define c14_CNTKCTL (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */ +#define NR_CP15_REGS (NR_SYS_REGS * 2) #define ARM_EXCEPTION_IRQ 0 #define ARM_EXCEPTION_TRAP 1 diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 2fdeb32..3f5830b 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -84,7 +84,10 @@ struct kvm_vcpu_fault_info { struct kvm_cpu_context { struct kvm_regs gp_regs; - u64 sys_regs[NR_SYS_REGS]; + union { + u64 sys_regs[NR_SYS_REGS]; + u32 cp15[NR_CP15_REGS]; + }; }; typedef struct kvm_cpu_context kvm_cpu_context_t; diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h index fb60f90..5b1110c 100644 --- a/arch/arm64/include/uapi/asm/kvm.h +++ b/arch/arm64/include/uapi/asm/kvm.h @@ -23,7 +23,12 @@ #define __ARM_KVM_H__ #define KVM_SPSR_EL1 0 -#define KVM_NR_SPSR 1 +#define KVM_SPSR_SVC KVM_SPSR_EL1 +#define KVM_SPSR_ABT 1 +#define KVM_SPSR_UND 2 +#define KVM_SPSR_IRQ 3 +#define KVM_SPSR_FIQ 4 +#define KVM_NR_SPSR 5 #ifndef __ASSEMBLY__ #include -- 1.8.2.3