* [RFC PATCH v4 00/18] ARM: DT cpu bindings updates
@ 2013-05-17 15:20 ` Lorenzo Pieralisi
0 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 15:20 UTC (permalink / raw)
To: linux-arm-kernel, devicetree-discuss
Cc: Nicolas Pitre, Jon Medhurst, Dave Martin, Andrew Lunn,
Tony Lindgren, Benjamin Herrenschmidt, Linus Walleij,
Will Deacon, Viresh Kumar, Kukjin Kim, Mark Rutland,
Lennert Buytenhek, Lorenzo Pieralisi, Russell King, Magnus Damm,
Catalin Marinas, Grant Likely, David Brown,
Jean-Christophe Plagniol-Villard, Dinh Nguyen, Arnd Bergmann,
Stephen Warren, Sekhar Nori
This patchset is an update of a previous posting:
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-April/165219.html
v4 changes:
- Replaced WARN* with pr_warn
- Removed tmp_map in arm_dt_init_cpu_maps()
- Rebased against 3.10-rc1
- Patched additional atmel and sunxi dts files
- Removed BUG_ON on !bootcpu_valid, now flagged up as an error
- Added code to reset invalid entries in cpu_logical_map after DT parsing
v3 changes:
- More dts fixes of in-kernel dts
- Defined ARM v8 behaviour with different cpus node #address-cells
- Added pre ARM11 processors suffixes in the cpu node compatible list
- Reordered series
- Reworded #address-cells definition
- Added ARM v8 - cores running on AArch32 bindings example
- Moved WARN* calls on one line to prevent grepping issues
v2 changes:
- Reworded DT cpu bindings
- Split the set, with per-mach specific dts updates
- Updated cpu node compatible string list
- Defined behaviour of OS running on v8 in AArch32
The introduction of DT cpus/cpu bindings for ARM requires well established
rules to enforce the reg property definition for 32-bit and 64-bit ARM
processors, inclusive of legacy and current uniprocessor/SMP systems.
ARM 64 bit architecture also requires dtb compiled for 64-bit configurations
to be reused for kernels running in 32 bit mode, so the cpus/cpu bindings
specification must be made compliant to cope with this configuration.
Patch #1-#2 of this series are fixes and are included to have a clean patch
series and should get reviewed and merged separately.
Patch #3-18, along with some kernel fixes related to DT parsing function,
update the cpu node bindings and in kernel dts files to cope with legacy,
current and upcoming ARM systems.
In-kernel device tree source files are updated to comply with the latest
specification, so thorough testing is required in order to validate all
changes on all affected ARM systems, in particular systems with exotic
MPIDR configurations that are likely to break with the changes provided.
Code relying on the reg property size to be 4-bytes must be updated so that
dtbs compiled for 64-bit kernels can also be used to boot a 32-bit system.
Lorenzo Pieralisi (18):
ARM: kernel: fix arm_dt_init_cpu_maps() to skip non-cpu nodes
ARM: kernel: fix __cpu_logical_map default initialization
Documentation: devicetree: arm: cpus/cpu nodes bindings updates
ARM: dts: am33xx: cpus/cpu nodes dts updates
ARM: dts: armada-370-xp: cpus/cpu node dts updates
ARM: dts: at91: cpus/cpu node dts updates
ARM: dts: exynos5440: cpus/cpu nodes dts updates
ARM: dts: imx: cpus/cpu nodes dts updates
ARM: dts: lpc32xx: cpus/cpu nodes dts updates
ARM: dts: omap: cpus/cpu nodes dts updates
ARM: dts: picoxcell: cpus/cpu nodes dts updates
ARM: dts: prima2: cpus/cpu node dts updates
ARM: dts: pxa2xx: cpus/cpu nodes dts updates
ARM: dts: r8a7740: cpus/cpu nodes dts updates
ARM: dts: sh7372: cpus/cpu nodes dts updates
ARM: dts: spear: cpus/cpu nodes dts updates
ARM: dts: sunxi: cpus/cpu nodes dts updates
ARM: DT: kernel: DT cpus/cpu node bindings update
Documentation/devicetree/bindings/arm/cpus.txt | 459 ++++++++++++++++++++++---
arch/arm/boot/dts/am33xx.dtsi | 4 +
arch/arm/boot/dts/armada-370-xp.dtsi | 4 +
arch/arm/boot/dts/at91rm9200.dtsi | 6 +-
arch/arm/boot/dts/at91sam9260.dtsi | 8 +-
arch/arm/boot/dts/at91sam9263.dtsi | 8 +-
arch/arm/boot/dts/at91sam9g45.dtsi | 8 +-
arch/arm/boot/dts/at91sam9n12.dtsi | 8 +-
arch/arm/boot/dts/at91sam9x5.dtsi | 8 +-
arch/arm/boot/dts/exynos5440.dtsi | 4 +
arch/arm/boot/dts/imx23.dtsi | 8 +-
arch/arm/boot/dts/imx28.dtsi | 8 +-
arch/arm/boot/dts/imx6dl.dtsi | 2 +
arch/arm/boot/dts/imx6q.dtsi | 4 +
arch/arm/boot/dts/lpc32xx.dtsi | 8 +-
arch/arm/boot/dts/omap2.dtsi | 6 +-
arch/arm/boot/dts/omap3.dtsi | 5 +
arch/arm/boot/dts/omap4.dtsi | 7 +
arch/arm/boot/dts/omap5.dtsi | 7 +
arch/arm/boot/dts/picoxcell-pc3x2.dtsi | 8 +-
arch/arm/boot/dts/picoxcell-pc3x3.dtsi | 8 +-
arch/arm/boot/dts/prima2.dtsi | 2 +
arch/arm/boot/dts/pxa2xx.dtsi | 7 +-
arch/arm/boot/dts/r8a7740.dtsi | 4 +
arch/arm/boot/dts/sama5d3.dtsi | 2 +
arch/arm/boot/dts/sh7372.dtsi | 5 +
arch/arm/boot/dts/spear13xx.dtsi | 2 +
arch/arm/boot/dts/spear3xx.dtsi | 8 +-
arch/arm/boot/dts/spear600.dtsi | 8 +-
arch/arm/boot/dts/sun4i-a10.dtsi | 2 +
arch/arm/boot/dts/sun5i-a13.dtsi | 2 +
arch/arm/include/asm/cputype.h | 2 +
arch/arm/include/asm/smp_plat.h | 2 +-
arch/arm/kernel/devtree.c | 149 ++++----
arch/arm/kernel/setup.c | 2 +-
35 files changed, 646 insertions(+), 139 deletions(-)
--
1.8.2.2
^ permalink raw reply [flat|nested] 64+ messages in thread
* [RFC PATCH v4 00/18] ARM: DT cpu bindings updates
@ 2013-05-17 15:20 ` Lorenzo Pieralisi
0 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 15:20 UTC (permalink / raw)
To: linux-arm-kernel
This patchset is an update of a previous posting:
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-April/165219.html
v4 changes:
- Replaced WARN* with pr_warn
- Removed tmp_map in arm_dt_init_cpu_maps()
- Rebased against 3.10-rc1
- Patched additional atmel and sunxi dts files
- Removed BUG_ON on !bootcpu_valid, now flagged up as an error
- Added code to reset invalid entries in cpu_logical_map after DT parsing
v3 changes:
- More dts fixes of in-kernel dts
- Defined ARM v8 behaviour with different cpus node #address-cells
- Added pre ARM11 processors suffixes in the cpu node compatible list
- Reordered series
- Reworded #address-cells definition
- Added ARM v8 - cores running on AArch32 bindings example
- Moved WARN* calls on one line to prevent grepping issues
v2 changes:
- Reworded DT cpu bindings
- Split the set, with per-mach specific dts updates
- Updated cpu node compatible string list
- Defined behaviour of OS running on v8 in AArch32
The introduction of DT cpus/cpu bindings for ARM requires well established
rules to enforce the reg property definition for 32-bit and 64-bit ARM
processors, inclusive of legacy and current uniprocessor/SMP systems.
ARM 64 bit architecture also requires dtb compiled for 64-bit configurations
to be reused for kernels running in 32 bit mode, so the cpus/cpu bindings
specification must be made compliant to cope with this configuration.
Patch #1-#2 of this series are fixes and are included to have a clean patch
series and should get reviewed and merged separately.
Patch #3-18, along with some kernel fixes related to DT parsing function,
update the cpu node bindings and in kernel dts files to cope with legacy,
current and upcoming ARM systems.
In-kernel device tree source files are updated to comply with the latest
specification, so thorough testing is required in order to validate all
changes on all affected ARM systems, in particular systems with exotic
MPIDR configurations that are likely to break with the changes provided.
Code relying on the reg property size to be 4-bytes must be updated so that
dtbs compiled for 64-bit kernels can also be used to boot a 32-bit system.
Lorenzo Pieralisi (18):
ARM: kernel: fix arm_dt_init_cpu_maps() to skip non-cpu nodes
ARM: kernel: fix __cpu_logical_map default initialization
Documentation: devicetree: arm: cpus/cpu nodes bindings updates
ARM: dts: am33xx: cpus/cpu nodes dts updates
ARM: dts: armada-370-xp: cpus/cpu node dts updates
ARM: dts: at91: cpus/cpu node dts updates
ARM: dts: exynos5440: cpus/cpu nodes dts updates
ARM: dts: imx: cpus/cpu nodes dts updates
ARM: dts: lpc32xx: cpus/cpu nodes dts updates
ARM: dts: omap: cpus/cpu nodes dts updates
ARM: dts: picoxcell: cpus/cpu nodes dts updates
ARM: dts: prima2: cpus/cpu node dts updates
ARM: dts: pxa2xx: cpus/cpu nodes dts updates
ARM: dts: r8a7740: cpus/cpu nodes dts updates
ARM: dts: sh7372: cpus/cpu nodes dts updates
ARM: dts: spear: cpus/cpu nodes dts updates
ARM: dts: sunxi: cpus/cpu nodes dts updates
ARM: DT: kernel: DT cpus/cpu node bindings update
Documentation/devicetree/bindings/arm/cpus.txt | 459 ++++++++++++++++++++++---
arch/arm/boot/dts/am33xx.dtsi | 4 +
arch/arm/boot/dts/armada-370-xp.dtsi | 4 +
arch/arm/boot/dts/at91rm9200.dtsi | 6 +-
arch/arm/boot/dts/at91sam9260.dtsi | 8 +-
arch/arm/boot/dts/at91sam9263.dtsi | 8 +-
arch/arm/boot/dts/at91sam9g45.dtsi | 8 +-
arch/arm/boot/dts/at91sam9n12.dtsi | 8 +-
arch/arm/boot/dts/at91sam9x5.dtsi | 8 +-
arch/arm/boot/dts/exynos5440.dtsi | 4 +
arch/arm/boot/dts/imx23.dtsi | 8 +-
arch/arm/boot/dts/imx28.dtsi | 8 +-
arch/arm/boot/dts/imx6dl.dtsi | 2 +
arch/arm/boot/dts/imx6q.dtsi | 4 +
arch/arm/boot/dts/lpc32xx.dtsi | 8 +-
arch/arm/boot/dts/omap2.dtsi | 6 +-
arch/arm/boot/dts/omap3.dtsi | 5 +
arch/arm/boot/dts/omap4.dtsi | 7 +
arch/arm/boot/dts/omap5.dtsi | 7 +
arch/arm/boot/dts/picoxcell-pc3x2.dtsi | 8 +-
arch/arm/boot/dts/picoxcell-pc3x3.dtsi | 8 +-
arch/arm/boot/dts/prima2.dtsi | 2 +
arch/arm/boot/dts/pxa2xx.dtsi | 7 +-
arch/arm/boot/dts/r8a7740.dtsi | 4 +
arch/arm/boot/dts/sama5d3.dtsi | 2 +
arch/arm/boot/dts/sh7372.dtsi | 5 +
arch/arm/boot/dts/spear13xx.dtsi | 2 +
arch/arm/boot/dts/spear3xx.dtsi | 8 +-
arch/arm/boot/dts/spear600.dtsi | 8 +-
arch/arm/boot/dts/sun4i-a10.dtsi | 2 +
arch/arm/boot/dts/sun5i-a13.dtsi | 2 +
arch/arm/include/asm/cputype.h | 2 +
arch/arm/include/asm/smp_plat.h | 2 +-
arch/arm/kernel/devtree.c | 149 ++++----
arch/arm/kernel/setup.c | 2 +-
35 files changed, 646 insertions(+), 139 deletions(-)
--
1.8.2.2
^ permalink raw reply [flat|nested] 64+ messages in thread
* [RFC PATCH v4 01/18] ARM: kernel: fix arm_dt_init_cpu_maps() to skip non-cpu nodes
2013-05-17 15:20 ` Lorenzo Pieralisi
@ 2013-05-17 15:20 ` Lorenzo Pieralisi
-1 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 15:20 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Nicolas Pitre, Jon Medhurst, Andrew Lunn, Will Deacon,
Viresh Kumar, Kukjin Kim, Lennert Buytenhek, Lorenzo Pieralisi,
Russell King, Magnus Damm, Catalin Marinas, Grant Likely,
David Brown, Sekhar Nori, Rob Herring, Simon Horman, Barry Song,
Vinayak Kale, Amit Kucheria
The introduction of the cpu-map topology node in the cpus node implies
that cpus node might have children that are not cpu nodes. The DT
parsing code needs updating otherwise it would check for cpu nodes
properties in nodes that are not required to contain them, resulting
in warnings that have no bearing on bindings defined in the dts source file.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
---
arch/arm/kernel/devtree.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
index 5af04f6..904cad5 100644
--- a/arch/arm/kernel/devtree.c
+++ b/arch/arm/kernel/devtree.c
@@ -92,6 +92,9 @@ void __init arm_dt_init_cpu_maps(void)
for_each_child_of_node(cpus, cpu) {
u32 hwid;
+ if (of_node_cmp(cpu->type, "cpu"))
+ continue;
+
pr_debug(" * %s...\n", cpu->full_name);
/*
* A device tree containing CPU nodes with missing "reg"
--
1.8.2.2
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [RFC PATCH v4 01/18] ARM: kernel: fix arm_dt_init_cpu_maps() to skip non-cpu nodes
@ 2013-05-17 15:20 ` Lorenzo Pieralisi
0 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 15:20 UTC (permalink / raw)
To: linux-arm-kernel
The introduction of the cpu-map topology node in the cpus node implies
that cpus node might have children that are not cpu nodes. The DT
parsing code needs updating otherwise it would check for cpu nodes
properties in nodes that are not required to contain them, resulting
in warnings that have no bearing on bindings defined in the dts source file.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
arch/arm/kernel/devtree.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
index 5af04f6..904cad5 100644
--- a/arch/arm/kernel/devtree.c
+++ b/arch/arm/kernel/devtree.c
@@ -92,6 +92,9 @@ void __init arm_dt_init_cpu_maps(void)
for_each_child_of_node(cpus, cpu) {
u32 hwid;
+ if (of_node_cmp(cpu->type, "cpu"))
+ continue;
+
pr_debug(" * %s...\n", cpu->full_name);
/*
* A device tree containing CPU nodes with missing "reg"
--
1.8.2.2
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [RFC PATCH v4 02/18] ARM: kernel: fix __cpu_logical_map default initialization
2013-05-17 15:20 ` Lorenzo Pieralisi
@ 2013-05-17 15:20 ` Lorenzo Pieralisi
-1 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 15:20 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Nicolas Pitre, Jon Medhurst, Andrew Lunn, Will Deacon,
Viresh Kumar, Kukjin Kim, Lennert Buytenhek, Lorenzo Pieralisi,
Russell King, Magnus Damm, Catalin Marinas, Grant Likely,
David Brown, Sekhar Nori, Rob Herring, Simon Horman, Barry Song,
Vinayak Kale, Amit Kucheria
The __cpu_logical_map array is statically initialized to 0, which is a valid
MPIDR value. To prevent issues with the current implementation, this patch
defines an MPIDR_INVALID value, and statically initializes the
__cpu_logical_map[] array to it. Entries in the arm_dt_init_cpu_maps()
tmp_map array used to stash DT reg properties while parsing DT are initialized
with the MPIDR_INVALID value as well for consistency.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
CC: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>
---
arch/arm/include/asm/cputype.h | 2 ++
arch/arm/include/asm/smp_plat.h | 2 +-
arch/arm/kernel/devtree.c | 2 +-
arch/arm/kernel/setup.c | 2 +-
4 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index 7652712..dba62cb 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -32,6 +32,8 @@
#define MPIDR_HWID_BITMASK 0xFFFFFF
+#define MPIDR_INVALID (~MPIDR_HWID_BITMASK)
+
#define MPIDR_LEVEL_BITS 8
#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index aaa61b6..e789832 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -49,7 +49,7 @@ static inline int cache_ops_need_broadcast(void)
/*
* Logical CPU mapping.
*/
-extern int __cpu_logical_map[];
+extern u32 __cpu_logical_map[];
#define cpu_logical_map(cpu) __cpu_logical_map[cpu]
/*
* Retrieve logical cpu index corresponding to a given MPIDR[23:0]
diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
index 904cad5..0905502 100644
--- a/arch/arm/kernel/devtree.c
+++ b/arch/arm/kernel/devtree.c
@@ -82,7 +82,7 @@ void __init arm_dt_init_cpu_maps(void)
u32 i, j, cpuidx = 1;
u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
- u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = UINT_MAX };
+ u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
bool bootcpu_valid = false;
cpus = of_find_node_by_path("/cpus");
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 6ae71b7..eeac924 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -457,7 +457,7 @@ void notrace cpu_init(void)
: "r14");
}
-int __cpu_logical_map[NR_CPUS];
+u32 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
void __init smp_setup_processor_id(void)
{
--
1.8.2.2
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [RFC PATCH v4 02/18] ARM: kernel: fix __cpu_logical_map default initialization
@ 2013-05-17 15:20 ` Lorenzo Pieralisi
0 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 15:20 UTC (permalink / raw)
To: linux-arm-kernel
The __cpu_logical_map array is statically initialized to 0, which is a valid
MPIDR value. To prevent issues with the current implementation, this patch
defines an MPIDR_INVALID value, and statically initializes the
__cpu_logical_map[] array to it. Entries in the arm_dt_init_cpu_maps()
tmp_map array used to stash DT reg properties while parsing DT are initialized
with the MPIDR_INVALID value as well for consistency.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
CC: Will Deacon <will.deacon@arm.com>
---
arch/arm/include/asm/cputype.h | 2 ++
arch/arm/include/asm/smp_plat.h | 2 +-
arch/arm/kernel/devtree.c | 2 +-
arch/arm/kernel/setup.c | 2 +-
4 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index 7652712..dba62cb 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -32,6 +32,8 @@
#define MPIDR_HWID_BITMASK 0xFFFFFF
+#define MPIDR_INVALID (~MPIDR_HWID_BITMASK)
+
#define MPIDR_LEVEL_BITS 8
#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index aaa61b6..e789832 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -49,7 +49,7 @@ static inline int cache_ops_need_broadcast(void)
/*
* Logical CPU mapping.
*/
-extern int __cpu_logical_map[];
+extern u32 __cpu_logical_map[];
#define cpu_logical_map(cpu) __cpu_logical_map[cpu]
/*
* Retrieve logical cpu index corresponding to a given MPIDR[23:0]
diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
index 904cad5..0905502 100644
--- a/arch/arm/kernel/devtree.c
+++ b/arch/arm/kernel/devtree.c
@@ -82,7 +82,7 @@ void __init arm_dt_init_cpu_maps(void)
u32 i, j, cpuidx = 1;
u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
- u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = UINT_MAX };
+ u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
bool bootcpu_valid = false;
cpus = of_find_node_by_path("/cpus");
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 6ae71b7..eeac924 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -457,7 +457,7 @@ void notrace cpu_init(void)
: "r14");
}
-int __cpu_logical_map[NR_CPUS];
+u32 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
void __init smp_setup_processor_id(void)
{
--
1.8.2.2
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [RFC PATCH v4 03/18] Documentation: devicetree: arm: cpus/cpu nodes bindings updates
2013-05-17 15:20 ` Lorenzo Pieralisi
@ 2013-05-17 15:20 ` Lorenzo Pieralisi
-1 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 15:20 UTC (permalink / raw)
To: linux-arm-kernel, devicetree-discuss
Cc: Nicolas Pitre, Jon Medhurst, Dave Martin, Andrew Lunn,
Tony Lindgren, Benjamin Herrenschmidt, Linus Walleij,
Will Deacon, Viresh Kumar, Kukjin Kim, Mark Rutland,
Lennert Buytenhek, Lorenzo Pieralisi, Russell King, Magnus Damm,
Catalin Marinas, Grant Likely, David Brown,
Jean-Christophe Plagniol-Villard, Dinh Nguyen, Arnd Bergmann,
Stephen Warren, Sekhar Nori
In order to extend the current cpu nodes bindings to newer CPUs
inclusive of AArch64 and to update support for older ARM CPUs this
patch updates device tree documentation for the cpu nodes bindings.
Main changes:
- adds 64-bit bindings
- define usage of #address-cells
- define 32/64 dts compatibility settings
- defines behaviour on pre and post v7 uniprocessor systems
- adds ARM 11MPcore specific reg property definition
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
Documentation/devicetree/bindings/arm/cpus.txt | 459 ++++++++++++++++++++++---
1 file changed, 412 insertions(+), 47 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index f32494d..3fc0c11 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -1,77 +1,442 @@
-* ARM CPUs binding description
+=================
+ARM CPUs bindings
+=================
The device tree allows to describe the layout of CPUs in a system through
the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
defining properties for every cpu.
-Bindings for CPU nodes follow the ePAPR standard, available from:
-
-http://devicetree.org
-
-For the ARM architecture every CPU node must contain the following properties:
-
-- device_type: must be "cpu"
-- reg: property matching the CPU MPIDR[23:0] register bits
- reg[31:24] bits must be set to 0
-- compatible: should be one of:
- "arm,arm1020"
- "arm,arm1020e"
- "arm,arm1022"
- "arm,arm1026"
- "arm,arm720"
- "arm,arm740"
- "arm,arm7tdmi"
- "arm,arm920"
- "arm,arm922"
- "arm,arm925"
- "arm,arm926"
- "arm,arm940"
- "arm,arm946"
- "arm,arm9tdmi"
- "arm,cortex-a5"
- "arm,cortex-a7"
- "arm,cortex-a8"
- "arm,cortex-a9"
- "arm,cortex-a15"
- "arm,arm1136"
- "arm,arm1156"
- "arm,arm1176"
- "arm,arm11mpcore"
- "faraday,fa526"
- "intel,sa110"
- "intel,sa1100"
- "marvell,feroceon"
- "marvell,mohawk"
- "marvell,xsc3"
- "marvell,xscale"
-
-Example:
+Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
+
+https://www.power.org/documentation/epapr-version-1-1/
+
+with updates for 32-bit and 64-bit ARM systems provided in this document.
+
+================================
+Convention used in this document
+================================
+
+This document follows the conventions described in the ePAPR v1.1, with
+the addition:
+
+- square brackets define bitfields, eg reg[7:0] value of the bitfield in
+ the reg property contained in bits 7 down to 0
+
+=====================================
+cpus and cpu node bindings definition
+=====================================
+
+The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
+nodes to be present and contain the properties described below.
+
+- cpus node
+
+ Description: Container of cpu nodes
+
+ The node name must be "cpus".
+
+ A cpus node must define the following properties:
+
+ - #address-cells
+ Usage: required
+ Value type: <u32>
+
+ Definition depends on ARM architecture version and
+ configuration:
+
+ # On uniprocessor ARM architectures previous to v7
+ value must be 0.
+ # On 32-bit ARM 11 MPcore, ARM v7 or later systems
+ value must be 1.
+ # On ARM v8 64-bit systems value must be set to 1
+ or 2. Refer to the cpu node's reg property
+ description for allowed configurations.
+
+ - #size-cells
+ Usage: required
+ Value type: <u32>
+ Definition: must be set to 0
+
+- cpu node
+
+ Description: Describes a CPU in an ARM based system
+
+ PROPERTIES
+
+ - device_type
+ Usage: required
+ Value type: <string>
+ Definition: must be "cpu"
+ - reg
+ Usage and definition depend on ARM architecture version and
+ configuration:
+
+ # On uniprocessor ARM architectures previous to v7
+ this property is optional since they do not define
+ any register that provides a CPU identifier.
+ Any value set in the reg property for these CPUs
+ should be ignored.
+
+ # On ARM 11 MPcore based systems this property is
+ required and matches the CPUID[11:0] register bits.
+
+ Bits [11:0] in the reg cell must be set to
+ bits [11:0] in CPU ID register.
+
+ All other bits in the reg cell must be set to 0.
+
+ # On 32-bit ARM v7 or later systems this property is
+ required and matches the CPU MPIDR[23:0] register
+ bits.
+
+ Bits [23:0] in the reg cell must be set to
+ bits [23:0] in MPIDR.
+
+ All other bits in the reg cell must be set to 0.
+
+ # On ARM v8 64-bit systems, where the reg property
+ size can be 1 or 2 cells (as defined by cpus node's
+ #address-cells property), this property is
+ required and matches:
+
+ - On systems running the OS in AArch32:
+
+ * If the cpus node's #address-cells value is 2:
+
+ The first reg cell must be set to 0.
+
+ The second reg cell bits [23:0] must be set to
+ bits [23:0] of MPIDR_EL1.
+
+ All other bits in the reg cells must be set to 0.
+
+ * If the cpus node's #address-cells value is 1:
+
+ Bits [23:0] in the reg cell must be set to
+ bits [23:0] in MPIDR_EL1.
+
+ All other bits in the reg cell must be 0.
+
+ - On systems running the OS in AArch64:
+
+ * If the cpus node's #address-cells value is 2:
+
+ The first reg cell bits [7:0] must be set to
+ bits [39:32] of MPIDR_EL1.
+
+ The second reg cell bits [23:0] must be set to
+ bits [23:0] of MPIDR_EL1.
+
+ All other bits in the reg cells must be set to 0.
+
+ * If the cpus node's #address-cells value is 1:
+
+ MPIDR_EL1[63:32] is 0 on all processors in the
+ system.
+
+ The reg cell bits [23:0] must be set to
+ bits [23:0] of MPIDR_EL1.
+
+ All other bits in the reg cell must be set to 0.
+
+ - compatible:
+ Usage: required
+ Value type: <string>
+ Definition: should be one of:
+ "arm,arm710t"
+ "arm,arm720t"
+ "arm,arm740t"
+ "arm,arm7ej-s"
+ "arm,arm7tdmi"
+ "arm,arm7tdmi-s"
+ "arm,arm9es"
+ "arm,arm9ej-s"
+ "arm,arm920t"
+ "arm,arm922t"
+ "arm,arm925"
+ "arm,arm926e-s"
+ "arm,arm926ej-s"
+ "arm,arm940t"
+ "arm,arm946e-s"
+ "arm,arm966e-s"
+ "arm,arm968e-s"
+ "arm,arm9tdmi"
+ "arm,arm1020e"
+ "arm,arm1020t"
+ "arm,arm1022e"
+ "arm,arm1026ej-s"
+ "arm,arm1136j-s"
+ "arm,arm1136jf-s"
+ "arm,arm1156t2-s"
+ "arm,arm1156t2f-s"
+ "arm,arm1176jzf"
+ "arm,arm1176jz-s"
+ "arm,arm1176jzf-s"
+ "arm,arm11mpcore"
+ "arm,cortex-a5"
+ "arm,cortex-a7"
+ "arm,cortex-a8"
+ "arm,cortex-a9"
+ "arm,cortex-a15"
+ "arm,cortex-a53"
+ "arm,cortex-a57"
+ "arm,cortex-m0"
+ "arm,cortex-m0+"
+ "arm,cortex-m1"
+ "arm,cortex-m3"
+ "arm,cortex-m4"
+ "arm,cortex-r4"
+ "arm,cortex-r5"
+ "arm,cortex-r7"
+ "faraday,fa526"
+ "intel,sa110"
+ "intel,sa1100"
+ "marvell,feroceon"
+ "marvell,mohawk"
+ "marvell,pj4"
+ "marvell,sheeva-v7"
+ "marvell,xsc3"
+ "marvell,xscale"
+ "qcom,krait"
+ "qcom,scorpion"
+ - enable-method
+ Value type: <stringlist>
+ Usage and definition depend on ARM architecture version and
+ configuration:
+ # On ARM v8 64-bit systems running the OS in AArch64,
+ this property is required and must be one of:
+ "spin-table"
+ "psci"
+ # On ARM 32-bit systems or ARM v8 systems running
+ the OS in AArch32 this property is prohibited.
+
+ - cpu-release-addr
+ Usage: required for systems that have an "enable-method"
+ property value of "spin-table".
+ Value type: <prop-encoded-array>
+ Definition:
+ # On ARM v8 64-bit systems must be a two cell
+ property identifying a 64-bit zero-initialised
+ memory location.
+
+Example 1 (dual-cluster big.LITTLE system 32-bit):
cpus {
#size-cells = <0>;
#address-cells = <1>;
- CPU0: cpu@0 {
+ cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x0>;
};
- CPU1: cpu@1 {
+ cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x1>;
};
- CPU2: cpu@100 {
+ cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x100>;
};
- CPU3: cpu@101 {
+ cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x101>;
};
};
+
+Example 2 (Cortex-A8 uniprocessor 32-bit system):
+
+ cpus {
+ #size-cells = <0>;
+ #address-cells = <1>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a8";
+ reg = <0x0>;
+ };
+ };
+
+Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
+
+ cpus {
+ #size-cells = <0>;
+ #address-cells = <0>;
+
+ cpu {
+ device_type = "cpu";
+ compatible = "arm,arm926ej-s";
+ };
+ };
+
+Example 4 (ARM Cortex-A57 64-bit system running OS in AArch64):
+
+cpus {
+ #size-cells = <0>;
+ #address-cells = <2>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x0>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x1>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x100>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x101>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu@10000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x10000>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu@10001 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x10001>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu@10100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x10100>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu@10101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x10101>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu@100000000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x1 0x0>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu@100000001 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x1 0x1>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu@100000100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x1 0x100>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu@100000101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x1 0x101>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu@100010000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x1 0x10000>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu@100010001 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x1 0x10001>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu@100010100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x1 0x10100>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu@100010101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x1 0x10101>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+};
+
+Example 5 (ARM Cortex-A57 64-bit system running OS in AArch32):
+
+cpus {
+ #size-cells = <0>;
+ #address-cells = <2>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x1>;
+ };
+
+ cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x100>;
+ };
+
+ cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x101>;
+ };
+};
--
1.8.2.2
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [RFC PATCH v4 03/18] Documentation: devicetree: arm: cpus/cpu nodes bindings updates
@ 2013-05-17 15:20 ` Lorenzo Pieralisi
0 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 15:20 UTC (permalink / raw)
To: linux-arm-kernel
In order to extend the current cpu nodes bindings to newer CPUs
inclusive of AArch64 and to update support for older ARM CPUs this
patch updates device tree documentation for the cpu nodes bindings.
Main changes:
- adds 64-bit bindings
- define usage of #address-cells
- define 32/64 dts compatibility settings
- defines behaviour on pre and post v7 uniprocessor systems
- adds ARM 11MPcore specific reg property definition
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
Documentation/devicetree/bindings/arm/cpus.txt | 459 ++++++++++++++++++++++---
1 file changed, 412 insertions(+), 47 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index f32494d..3fc0c11 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -1,77 +1,442 @@
-* ARM CPUs binding description
+=================
+ARM CPUs bindings
+=================
The device tree allows to describe the layout of CPUs in a system through
the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
defining properties for every cpu.
-Bindings for CPU nodes follow the ePAPR standard, available from:
-
-http://devicetree.org
-
-For the ARM architecture every CPU node must contain the following properties:
-
-- device_type: must be "cpu"
-- reg: property matching the CPU MPIDR[23:0] register bits
- reg[31:24] bits must be set to 0
-- compatible: should be one of:
- "arm,arm1020"
- "arm,arm1020e"
- "arm,arm1022"
- "arm,arm1026"
- "arm,arm720"
- "arm,arm740"
- "arm,arm7tdmi"
- "arm,arm920"
- "arm,arm922"
- "arm,arm925"
- "arm,arm926"
- "arm,arm940"
- "arm,arm946"
- "arm,arm9tdmi"
- "arm,cortex-a5"
- "arm,cortex-a7"
- "arm,cortex-a8"
- "arm,cortex-a9"
- "arm,cortex-a15"
- "arm,arm1136"
- "arm,arm1156"
- "arm,arm1176"
- "arm,arm11mpcore"
- "faraday,fa526"
- "intel,sa110"
- "intel,sa1100"
- "marvell,feroceon"
- "marvell,mohawk"
- "marvell,xsc3"
- "marvell,xscale"
-
-Example:
+Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
+
+https://www.power.org/documentation/epapr-version-1-1/
+
+with updates for 32-bit and 64-bit ARM systems provided in this document.
+
+================================
+Convention used in this document
+================================
+
+This document follows the conventions described in the ePAPR v1.1, with
+the addition:
+
+- square brackets define bitfields, eg reg[7:0] value of the bitfield in
+ the reg property contained in bits 7 down to 0
+
+=====================================
+cpus and cpu node bindings definition
+=====================================
+
+The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
+nodes to be present and contain the properties described below.
+
+- cpus node
+
+ Description: Container of cpu nodes
+
+ The node name must be "cpus".
+
+ A cpus node must define the following properties:
+
+ - #address-cells
+ Usage: required
+ Value type: <u32>
+
+ Definition depends on ARM architecture version and
+ configuration:
+
+ # On uniprocessor ARM architectures previous to v7
+ value must be 0.
+ # On 32-bit ARM 11 MPcore, ARM v7 or later systems
+ value must be 1.
+ # On ARM v8 64-bit systems value must be set to 1
+ or 2. Refer to the cpu node's reg property
+ description for allowed configurations.
+
+ - #size-cells
+ Usage: required
+ Value type: <u32>
+ Definition: must be set to 0
+
+- cpu node
+
+ Description: Describes a CPU in an ARM based system
+
+ PROPERTIES
+
+ - device_type
+ Usage: required
+ Value type: <string>
+ Definition: must be "cpu"
+ - reg
+ Usage and definition depend on ARM architecture version and
+ configuration:
+
+ # On uniprocessor ARM architectures previous to v7
+ this property is optional since they do not define
+ any register that provides a CPU identifier.
+ Any value set in the reg property for these CPUs
+ should be ignored.
+
+ # On ARM 11 MPcore based systems this property is
+ required and matches the CPUID[11:0] register bits.
+
+ Bits [11:0] in the reg cell must be set to
+ bits [11:0] in CPU ID register.
+
+ All other bits in the reg cell must be set to 0.
+
+ # On 32-bit ARM v7 or later systems this property is
+ required and matches the CPU MPIDR[23:0] register
+ bits.
+
+ Bits [23:0] in the reg cell must be set to
+ bits [23:0] in MPIDR.
+
+ All other bits in the reg cell must be set to 0.
+
+ # On ARM v8 64-bit systems, where the reg property
+ size can be 1 or 2 cells (as defined by cpus node's
+ #address-cells property), this property is
+ required and matches:
+
+ - On systems running the OS in AArch32:
+
+ * If the cpus node's #address-cells value is 2:
+
+ The first reg cell must be set to 0.
+
+ The second reg cell bits [23:0] must be set to
+ bits [23:0] of MPIDR_EL1.
+
+ All other bits in the reg cells must be set to 0.
+
+ * If the cpus node's #address-cells value is 1:
+
+ Bits [23:0] in the reg cell must be set to
+ bits [23:0] in MPIDR_EL1.
+
+ All other bits in the reg cell must be 0.
+
+ - On systems running the OS in AArch64:
+
+ * If the cpus node's #address-cells value is 2:
+
+ The first reg cell bits [7:0] must be set to
+ bits [39:32] of MPIDR_EL1.
+
+ The second reg cell bits [23:0] must be set to
+ bits [23:0] of MPIDR_EL1.
+
+ All other bits in the reg cells must be set to 0.
+
+ * If the cpus node's #address-cells value is 1:
+
+ MPIDR_EL1[63:32] is 0 on all processors in the
+ system.
+
+ The reg cell bits [23:0] must be set to
+ bits [23:0] of MPIDR_EL1.
+
+ All other bits in the reg cell must be set to 0.
+
+ - compatible:
+ Usage: required
+ Value type: <string>
+ Definition: should be one of:
+ "arm,arm710t"
+ "arm,arm720t"
+ "arm,arm740t"
+ "arm,arm7ej-s"
+ "arm,arm7tdmi"
+ "arm,arm7tdmi-s"
+ "arm,arm9es"
+ "arm,arm9ej-s"
+ "arm,arm920t"
+ "arm,arm922t"
+ "arm,arm925"
+ "arm,arm926e-s"
+ "arm,arm926ej-s"
+ "arm,arm940t"
+ "arm,arm946e-s"
+ "arm,arm966e-s"
+ "arm,arm968e-s"
+ "arm,arm9tdmi"
+ "arm,arm1020e"
+ "arm,arm1020t"
+ "arm,arm1022e"
+ "arm,arm1026ej-s"
+ "arm,arm1136j-s"
+ "arm,arm1136jf-s"
+ "arm,arm1156t2-s"
+ "arm,arm1156t2f-s"
+ "arm,arm1176jzf"
+ "arm,arm1176jz-s"
+ "arm,arm1176jzf-s"
+ "arm,arm11mpcore"
+ "arm,cortex-a5"
+ "arm,cortex-a7"
+ "arm,cortex-a8"
+ "arm,cortex-a9"
+ "arm,cortex-a15"
+ "arm,cortex-a53"
+ "arm,cortex-a57"
+ "arm,cortex-m0"
+ "arm,cortex-m0+"
+ "arm,cortex-m1"
+ "arm,cortex-m3"
+ "arm,cortex-m4"
+ "arm,cortex-r4"
+ "arm,cortex-r5"
+ "arm,cortex-r7"
+ "faraday,fa526"
+ "intel,sa110"
+ "intel,sa1100"
+ "marvell,feroceon"
+ "marvell,mohawk"
+ "marvell,pj4"
+ "marvell,sheeva-v7"
+ "marvell,xsc3"
+ "marvell,xscale"
+ "qcom,krait"
+ "qcom,scorpion"
+ - enable-method
+ Value type: <stringlist>
+ Usage and definition depend on ARM architecture version and
+ configuration:
+ # On ARM v8 64-bit systems running the OS in AArch64,
+ this property is required and must be one of:
+ "spin-table"
+ "psci"
+ # On ARM 32-bit systems or ARM v8 systems running
+ the OS in AArch32 this property is prohibited.
+
+ - cpu-release-addr
+ Usage: required for systems that have an "enable-method"
+ property value of "spin-table".
+ Value type: <prop-encoded-array>
+ Definition:
+ # On ARM v8 64-bit systems must be a two cell
+ property identifying a 64-bit zero-initialised
+ memory location.
+
+Example 1 (dual-cluster big.LITTLE system 32-bit):
cpus {
#size-cells = <0>;
#address-cells = <1>;
- CPU0: cpu at 0 {
+ cpu at 0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x0>;
};
- CPU1: cpu at 1 {
+ cpu at 1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x1>;
};
- CPU2: cpu at 100 {
+ cpu at 100 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x100>;
};
- CPU3: cpu at 101 {
+ cpu at 101 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x101>;
};
};
+
+Example 2 (Cortex-A8 uniprocessor 32-bit system):
+
+ cpus {
+ #size-cells = <0>;
+ #address-cells = <1>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a8";
+ reg = <0x0>;
+ };
+ };
+
+Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
+
+ cpus {
+ #size-cells = <0>;
+ #address-cells = <0>;
+
+ cpu {
+ device_type = "cpu";
+ compatible = "arm,arm926ej-s";
+ };
+ };
+
+Example 4 (ARM Cortex-A57 64-bit system running OS in AArch64):
+
+cpus {
+ #size-cells = <0>;
+ #address-cells = <2>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x0>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x1>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu at 100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x100>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu at 101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x101>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu at 10000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x10000>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu at 10001 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x10001>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu at 10100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x10100>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu at 10101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x10101>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu at 100000000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x1 0x0>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu at 100000001 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x1 0x1>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu at 100000100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x1 0x100>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu at 100000101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x1 0x101>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu at 100010000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x1 0x10000>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu at 100010001 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x1 0x10001>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu at 100010100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x1 0x10100>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu at 100010101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x1 0x10101>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+};
+
+Example 5 (ARM Cortex-A57 64-bit system running OS in AArch32):
+
+cpus {
+ #size-cells = <0>;
+ #address-cells = <2>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x0>;
+ };
+
+ cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x1>;
+ };
+
+ cpu at 100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x100>;
+ };
+
+ cpu at 101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x101>;
+ };
+};
--
1.8.2.2
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [RFC PATCH v4 04/18] ARM: dts: am33xx: cpus/cpu nodes dts updates
2013-05-17 15:20 ` Lorenzo Pieralisi
@ 2013-05-17 15:20 ` Lorenzo Pieralisi
-1 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 15:20 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Nicolas Pitre, Jon Medhurst, Andrew Lunn, Will Deacon,
Viresh Kumar, Kukjin Kim, Lennert Buytenhek, Lorenzo Pieralisi,
Russell King, Magnus Damm, Catalin Marinas, Grant Likely,
David Brown, Sekhar Nori, Rob Herring, Simon Horman, Barry Song,
Vinayak Kale, Amit Kucheria
This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
---
arch/arm/boot/dts/am33xx.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 1460d9b..6827853 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -26,8 +26,12 @@
};
cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a8";
+ device_type = "cpu";
+ reg = <0>;
/*
* To consider voltage drop between PMIC and SoC,
--
1.8.2.2
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [RFC PATCH v4 04/18] ARM: dts: am33xx: cpus/cpu nodes dts updates
@ 2013-05-17 15:20 ` Lorenzo Pieralisi
0 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 15:20 UTC (permalink / raw)
To: linux-arm-kernel
This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
arch/arm/boot/dts/am33xx.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 1460d9b..6827853 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -26,8 +26,12 @@
};
cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
cpu at 0 {
compatible = "arm,cortex-a8";
+ device_type = "cpu";
+ reg = <0>;
/*
* To consider voltage drop between PMIC and SoC,
--
1.8.2.2
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [RFC PATCH v4 05/18] ARM: dts: armada-370-xp: cpus/cpu node dts updates
2013-05-17 15:20 ` Lorenzo Pieralisi
@ 2013-05-17 15:20 ` Lorenzo Pieralisi
-1 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 15:20 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Nicolas Pitre, Jon Medhurst, Andrew Lunn, Will Deacon,
Viresh Kumar, Kukjin Kim, Lennert Buytenhek, Lorenzo Pieralisi,
Russell King, Magnus Damm, Catalin Marinas, Grant Likely,
David Brown, Sekhar Nori, Rob Herring, Simon Horman, Barry Song,
Vinayak Kale, Amit Kucheria
This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
---
arch/arm/boot/dts/armada-370-xp.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 272bbc6..2407903 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -23,8 +23,12 @@
compatible = "marvell,armada-370-xp";
cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
cpu@0 {
compatible = "marvell,sheeva-v7";
+ device_type = "cpu";
+ reg = <0>;
};
};
--
1.8.2.2
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [RFC PATCH v4 05/18] ARM: dts: armada-370-xp: cpus/cpu node dts updates
@ 2013-05-17 15:20 ` Lorenzo Pieralisi
0 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 15:20 UTC (permalink / raw)
To: linux-arm-kernel
This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
arch/arm/boot/dts/armada-370-xp.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 272bbc6..2407903 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -23,8 +23,12 @@
compatible = "marvell,armada-370-xp";
cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
cpu at 0 {
compatible = "marvell,sheeva-v7";
+ device_type = "cpu";
+ reg = <0>;
};
};
--
1.8.2.2
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [RFC PATCH v4 06/18] ARM: dts: at91: cpus/cpu node dts updates
2013-05-17 15:20 ` Lorenzo Pieralisi
@ 2013-05-17 15:20 ` Lorenzo Pieralisi
-1 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 15:20 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Nicolas Pitre, Jon Medhurst, Andrew Lunn, Will Deacon,
Viresh Kumar, Kukjin Kim, Lennert Buytenhek, Lorenzo Pieralisi,
Russell King, Magnus Damm, Catalin Marinas, Grant Likely,
David Brown, Sekhar Nori, Rob Herring, Simon Horman, Barry Song,
Vinayak Kale, Amit Kucheria
This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
Acked-by: Nicolas Ferre <nicolas.ferre-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
---
arch/arm/boot/dts/at91rm9200.dtsi | 6 +++++-
arch/arm/boot/dts/at91sam9260.dtsi | 8 ++++++--
arch/arm/boot/dts/at91sam9263.dtsi | 8 ++++++--
arch/arm/boot/dts/at91sam9g45.dtsi | 8 ++++++--
arch/arm/boot/dts/at91sam9n12.dtsi | 8 ++++++--
arch/arm/boot/dts/at91sam9x5.dtsi | 8 ++++++--
arch/arm/boot/dts/sama5d3.dtsi | 2 ++
7 files changed, 37 insertions(+), 11 deletions(-)
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index 5d3ed5a..0af879a 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -35,8 +35,12 @@
ssc2 = &ssc2;
};
cpus {
- cpu@0 {
+ #address-cells = <0>;
+ #size-cells = <0>;
+
+ cpu {
compatible = "arm,arm920t";
+ device_type = "cpu";
};
};
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 70b5ccb..e1ba7ea 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -32,8 +32,12 @@
ssc0 = &ssc0;
};
cpus {
- cpu@0 {
- compatible = "arm,arm926ejs";
+ #address-cells = <0>;
+ #size-cells = <0>;
+
+ cpu {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
};
};
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 94b58ab..fcd38f8 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -29,8 +29,12 @@
ssc1 = &ssc1;
};
cpus {
- cpu@0 {
- compatible = "arm,arm926ejs";
+ #address-cells = <0>;
+ #size-cells = <0>;
+
+ cpu {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
};
};
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index bf18a73..479a062 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -35,8 +35,12 @@
ssc1 = &ssc1;
};
cpus {
- cpu@0 {
- compatible = "arm,arm926ejs";
+ #address-cells = <0>;
+ #size-cells = <0>;
+
+ cpu {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
};
};
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 3de8e6d..01df681 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -31,8 +31,12 @@
ssc0 = &ssc0;
};
cpus {
- cpu@0 {
- compatible = "arm,arm926ejs";
+ #address-cells = <0>;
+ #size-cells = <0>;
+
+ cpu {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
};
};
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 1145ac3..6d8bd671 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -33,8 +33,12 @@
ssc0 = &ssc0;
};
cpus {
- cpu@0 {
- compatible = "arm,arm926ejs";
+ #address-cells = <0>;
+ #size-cells = <0>;
+
+ cpu {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
};
};
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index 2e643ea..5325371 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -36,7 +36,9 @@
};
cpus {
cpu@0 {
+ device_type = "cpu";
compatible = "arm,cortex-a5";
+ reg = <0x0>;
};
};
--
1.8.2.2
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [RFC PATCH v4 06/18] ARM: dts: at91: cpus/cpu node dts updates
@ 2013-05-17 15:20 ` Lorenzo Pieralisi
0 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 15:20 UTC (permalink / raw)
To: linux-arm-kernel
This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
---
arch/arm/boot/dts/at91rm9200.dtsi | 6 +++++-
arch/arm/boot/dts/at91sam9260.dtsi | 8 ++++++--
arch/arm/boot/dts/at91sam9263.dtsi | 8 ++++++--
arch/arm/boot/dts/at91sam9g45.dtsi | 8 ++++++--
arch/arm/boot/dts/at91sam9n12.dtsi | 8 ++++++--
arch/arm/boot/dts/at91sam9x5.dtsi | 8 ++++++--
arch/arm/boot/dts/sama5d3.dtsi | 2 ++
7 files changed, 37 insertions(+), 11 deletions(-)
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index 5d3ed5a..0af879a 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -35,8 +35,12 @@
ssc2 = &ssc2;
};
cpus {
- cpu at 0 {
+ #address-cells = <0>;
+ #size-cells = <0>;
+
+ cpu {
compatible = "arm,arm920t";
+ device_type = "cpu";
};
};
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 70b5ccb..e1ba7ea 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -32,8 +32,12 @@
ssc0 = &ssc0;
};
cpus {
- cpu at 0 {
- compatible = "arm,arm926ejs";
+ #address-cells = <0>;
+ #size-cells = <0>;
+
+ cpu {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
};
};
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 94b58ab..fcd38f8 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -29,8 +29,12 @@
ssc1 = &ssc1;
};
cpus {
- cpu at 0 {
- compatible = "arm,arm926ejs";
+ #address-cells = <0>;
+ #size-cells = <0>;
+
+ cpu {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
};
};
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index bf18a73..479a062 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -35,8 +35,12 @@
ssc1 = &ssc1;
};
cpus {
- cpu at 0 {
- compatible = "arm,arm926ejs";
+ #address-cells = <0>;
+ #size-cells = <0>;
+
+ cpu {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
};
};
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 3de8e6d..01df681 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -31,8 +31,12 @@
ssc0 = &ssc0;
};
cpus {
- cpu at 0 {
- compatible = "arm,arm926ejs";
+ #address-cells = <0>;
+ #size-cells = <0>;
+
+ cpu {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
};
};
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 1145ac3..6d8bd671 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -33,8 +33,12 @@
ssc0 = &ssc0;
};
cpus {
- cpu at 0 {
- compatible = "arm,arm926ejs";
+ #address-cells = <0>;
+ #size-cells = <0>;
+
+ cpu {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
};
};
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index 2e643ea..5325371 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -36,7 +36,9 @@
};
cpus {
cpu at 0 {
+ device_type = "cpu";
compatible = "arm,cortex-a5";
+ reg = <0x0>;
};
};
--
1.8.2.2
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [RFC PATCH v4 07/18] ARM: dts: exynos5440: cpus/cpu nodes dts updates
2013-05-17 15:20 ` Lorenzo Pieralisi
@ 2013-05-17 15:20 ` Lorenzo Pieralisi
-1 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 15:20 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Nicolas Pitre, Jon Medhurst, Andrew Lunn, Will Deacon,
Viresh Kumar, Kukjin Kim, Lennert Buytenhek, Lorenzo Pieralisi,
Russell King, Magnus Damm, Catalin Marinas, Grant Likely,
David Brown, Sekhar Nori, Rob Herring, Simon Horman, Barry Song,
Vinayak Kale, Amit Kucheria
This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
---
arch/arm/boot/dts/exynos5440.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index f6b1c89..646677e 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -38,18 +38,22 @@
#size-cells = <0>;
cpu@0 {
+ device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0>;
};
cpu@1 {
+ device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <1>;
};
cpu@2 {
+ device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <2>;
};
cpu@3 {
+ device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <3>;
};
--
1.8.2.2
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [RFC PATCH v4 07/18] ARM: dts: exynos5440: cpus/cpu nodes dts updates
@ 2013-05-17 15:20 ` Lorenzo Pieralisi
0 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 15:20 UTC (permalink / raw)
To: linux-arm-kernel
This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
arch/arm/boot/dts/exynos5440.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index f6b1c89..646677e 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -38,18 +38,22 @@
#size-cells = <0>;
cpu at 0 {
+ device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0>;
};
cpu at 1 {
+ device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <1>;
};
cpu at 2 {
+ device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <2>;
};
cpu at 3 {
+ device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <3>;
};
--
1.8.2.2
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [RFC PATCH v4 08/18] ARM: dts: imx: cpus/cpu nodes dts updates
2013-05-17 15:20 ` Lorenzo Pieralisi
@ 2013-05-17 15:20 ` Lorenzo Pieralisi
-1 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 15:20 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Nicolas Pitre, Jon Medhurst, Andrew Lunn, Will Deacon,
Viresh Kumar, Kukjin Kim, Lennert Buytenhek, Lorenzo Pieralisi,
Russell King, Magnus Damm, Catalin Marinas, Grant Likely,
David Brown, Sekhar Nori, Rob Herring, Simon Horman, Barry Song,
Vinayak Kale, Amit Kucheria
This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
Acked-by: Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
arch/arm/boot/dts/imx23.dtsi | 8 ++++++--
arch/arm/boot/dts/imx28.dtsi | 8 ++++++--
arch/arm/boot/dts/imx6dl.dtsi | 2 ++
arch/arm/boot/dts/imx6q.dtsi | 4 ++++
4 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 73fd7d0..587ceef 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -23,8 +23,12 @@
};
cpus {
- cpu@0 {
- compatible = "arm,arm926ejs";
+ #address-cells = <0>;
+ #size-cells = <0>;
+
+ cpu {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
};
};
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 600f7cb..4c10a19 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -32,8 +32,12 @@
};
cpus {
- cpu@0 {
- compatible = "arm,arm926ejs";
+ #address-cells = <0>;
+ #size-cells = <0>;
+
+ cpu {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
};
};
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 5bcdf3a..62dc781 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -18,12 +18,14 @@
cpu@0 {
compatible = "arm,cortex-a9";
+ device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
};
cpu@1 {
compatible = "arm,cortex-a9";
+ device_type = "cpu";
reg = <1>;
next-level-cache = <&L2>;
};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 21e6758..dc54a72 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -18,6 +18,7 @@
cpu@0 {
compatible = "arm,cortex-a9";
+ device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
operating-points = <
@@ -39,18 +40,21 @@
cpu@1 {
compatible = "arm,cortex-a9";
+ device_type = "cpu";
reg = <1>;
next-level-cache = <&L2>;
};
cpu@2 {
compatible = "arm,cortex-a9";
+ device_type = "cpu";
reg = <2>;
next-level-cache = <&L2>;
};
cpu@3 {
compatible = "arm,cortex-a9";
+ device_type = "cpu";
reg = <3>;
next-level-cache = <&L2>;
};
--
1.8.2.2
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [RFC PATCH v4 08/18] ARM: dts: imx: cpus/cpu nodes dts updates
@ 2013-05-17 15:20 ` Lorenzo Pieralisi
0 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 15:20 UTC (permalink / raw)
To: linux-arm-kernel
This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
---
arch/arm/boot/dts/imx23.dtsi | 8 ++++++--
arch/arm/boot/dts/imx28.dtsi | 8 ++++++--
arch/arm/boot/dts/imx6dl.dtsi | 2 ++
arch/arm/boot/dts/imx6q.dtsi | 4 ++++
4 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 73fd7d0..587ceef 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -23,8 +23,12 @@
};
cpus {
- cpu at 0 {
- compatible = "arm,arm926ejs";
+ #address-cells = <0>;
+ #size-cells = <0>;
+
+ cpu {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
};
};
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 600f7cb..4c10a19 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -32,8 +32,12 @@
};
cpus {
- cpu at 0 {
- compatible = "arm,arm926ejs";
+ #address-cells = <0>;
+ #size-cells = <0>;
+
+ cpu {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
};
};
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 5bcdf3a..62dc781 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -18,12 +18,14 @@
cpu at 0 {
compatible = "arm,cortex-a9";
+ device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
};
cpu at 1 {
compatible = "arm,cortex-a9";
+ device_type = "cpu";
reg = <1>;
next-level-cache = <&L2>;
};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 21e6758..dc54a72 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -18,6 +18,7 @@
cpu at 0 {
compatible = "arm,cortex-a9";
+ device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
operating-points = <
@@ -39,18 +40,21 @@
cpu@1 {
compatible = "arm,cortex-a9";
+ device_type = "cpu";
reg = <1>;
next-level-cache = <&L2>;
};
cpu at 2 {
compatible = "arm,cortex-a9";
+ device_type = "cpu";
reg = <2>;
next-level-cache = <&L2>;
};
cpu at 3 {
compatible = "arm,cortex-a9";
+ device_type = "cpu";
reg = <3>;
next-level-cache = <&L2>;
};
--
1.8.2.2
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [RFC PATCH v4 09/18] ARM: dts: lpc32xx: cpus/cpu nodes dts updates
2013-05-17 15:20 ` Lorenzo Pieralisi
@ 2013-05-17 15:20 ` Lorenzo Pieralisi
-1 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 15:20 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Nicolas Pitre, Jon Medhurst, Andrew Lunn, Will Deacon,
Viresh Kumar, Kukjin Kim, Lennert Buytenhek, Lorenzo Pieralisi,
Russell King, Magnus Damm, Catalin Marinas, Grant Likely,
David Brown, Sekhar Nori, Rob Herring, Simon Horman, Barry Song,
Vinayak Kale, Amit Kucheria
This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
---
arch/arm/boot/dts/lpc32xx.dtsi | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index 1582f48..3abebb7 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -18,8 +18,12 @@
interrupt-parent = <&mic>;
cpus {
- cpu@0 {
- compatible = "arm,arm926ejs";
+ #address-cells = <0>;
+ #size-cells = <0>;
+
+ cpu {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
};
};
--
1.8.2.2
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [RFC PATCH v4 09/18] ARM: dts: lpc32xx: cpus/cpu nodes dts updates
@ 2013-05-17 15:20 ` Lorenzo Pieralisi
0 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 15:20 UTC (permalink / raw)
To: linux-arm-kernel
This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
arch/arm/boot/dts/lpc32xx.dtsi | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index 1582f48..3abebb7 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -18,8 +18,12 @@
interrupt-parent = <&mic>;
cpus {
- cpu at 0 {
- compatible = "arm,arm926ejs";
+ #address-cells = <0>;
+ #size-cells = <0>;
+
+ cpu {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
};
};
--
1.8.2.2
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [RFC PATCH v4 10/18] ARM: dts: omap: cpus/cpu nodes dts updates
2013-05-17 15:20 ` Lorenzo Pieralisi
@ 2013-05-17 15:20 ` Lorenzo Pieralisi
-1 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 15:20 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Nicolas Pitre, Jon Medhurst, Andrew Lunn, Will Deacon,
Viresh Kumar, Kukjin Kim, Lennert Buytenhek, Lorenzo Pieralisi,
Russell King, Magnus Damm, Catalin Marinas, Grant Likely,
David Brown, Sekhar Nori, Rob Herring, Simon Horman, Barry Song,
Vinayak Kale, Amit Kucheria
This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
---
arch/arm/boot/dts/omap2.dtsi | 6 +++++-
arch/arm/boot/dts/omap3.dtsi | 5 +++++
arch/arm/boot/dts/omap4.dtsi | 7 +++++++
arch/arm/boot/dts/omap5.dtsi | 7 +++++++
4 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index 37aa748..4aac404 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -21,8 +21,12 @@
};
cpus {
- cpu@0 {
+ #address-cells = <0>;
+ #size-cells = <0>;
+
+ cpu {
compatible = "arm,arm1136jf-s";
+ device_type = "cpu";
};
};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 82a404d..ba05d7f 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -21,8 +21,13 @@
};
cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
cpu@0 {
compatible = "arm,cortex-a8";
+ device_type = "cpu";
+ reg = <0x0>;
};
};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 2a56428..33a9450 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -28,13 +28,20 @@
};
cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
cpu@0 {
compatible = "arm,cortex-a9";
+ device_type = "cpu";
next-level-cache = <&L2>;
+ reg = <0x0>;
};
cpu@1 {
compatible = "arm,cortex-a9";
+ device_type = "cpu";
next-level-cache = <&L2>;
+ reg = <0x1>;
};
};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 3dd7ff8..35a6536 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -34,11 +34,18 @@
};
cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
cpu@0 {
+ device_type = "cpu";
compatible = "arm,cortex-a15";
+ reg = <0x0>;
};
cpu@1 {
+ device_type = "cpu";
compatible = "arm,cortex-a15";
+ reg = <0x1>;
};
};
--
1.8.2.2
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [RFC PATCH v4 10/18] ARM: dts: omap: cpus/cpu nodes dts updates
@ 2013-05-17 15:20 ` Lorenzo Pieralisi
0 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 15:20 UTC (permalink / raw)
To: linux-arm-kernel
This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
arch/arm/boot/dts/omap2.dtsi | 6 +++++-
arch/arm/boot/dts/omap3.dtsi | 5 +++++
arch/arm/boot/dts/omap4.dtsi | 7 +++++++
arch/arm/boot/dts/omap5.dtsi | 7 +++++++
4 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index 37aa748..4aac404 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -21,8 +21,12 @@
};
cpus {
- cpu at 0 {
+ #address-cells = <0>;
+ #size-cells = <0>;
+
+ cpu {
compatible = "arm,arm1136jf-s";
+ device_type = "cpu";
};
};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 82a404d..ba05d7f 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -21,8 +21,13 @@
};
cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
cpu at 0 {
compatible = "arm,cortex-a8";
+ device_type = "cpu";
+ reg = <0x0>;
};
};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 2a56428..33a9450 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -28,13 +28,20 @@
};
cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
cpu at 0 {
compatible = "arm,cortex-a9";
+ device_type = "cpu";
next-level-cache = <&L2>;
+ reg = <0x0>;
};
cpu at 1 {
compatible = "arm,cortex-a9";
+ device_type = "cpu";
next-level-cache = <&L2>;
+ reg = <0x1>;
};
};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 3dd7ff8..35a6536 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -34,11 +34,18 @@
};
cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
cpu at 0 {
+ device_type = "cpu";
compatible = "arm,cortex-a15";
+ reg = <0x0>;
};
cpu at 1 {
+ device_type = "cpu";
compatible = "arm,cortex-a15";
+ reg = <0x1>;
};
};
--
1.8.2.2
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [RFC PATCH v4 11/18] ARM: dts: picoxcell: cpus/cpu nodes dts updates
2013-05-17 15:20 ` Lorenzo Pieralisi
@ 2013-05-17 15:20 ` Lorenzo Pieralisi
-1 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 15:20 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Nicolas Pitre, Jon Medhurst, Andrew Lunn, Will Deacon,
Viresh Kumar, Kukjin Kim, Lennert Buytenhek, Lorenzo Pieralisi,
Russell King, Magnus Damm, Catalin Marinas, Grant Likely,
David Brown, Sekhar Nori, Rob Herring, Simon Horman, Barry Song,
Vinayak Kale, Amit Kucheria
This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
---
arch/arm/boot/dts/picoxcell-pc3x2.dtsi | 8 ++++----
arch/arm/boot/dts/picoxcell-pc3x3.dtsi | 8 ++++----
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
index f0a8c20..533919e 100644
--- a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
+++ b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
@@ -18,13 +18,13 @@
#size-cells = <1>;
cpus {
- #address-cells = <1>;
+ #address-cells = <0>;
#size-cells = <0>;
- cpu@0 {
- compatible = "arm,1176jz-s";
+ cpu {
+ compatible = "arm,arm1176jz-s";
+ device_type = "cpu";
clock-frequency = <400000000>;
- reg = <0>;
d-cache-line-size = <32>;
d-cache-size = <32768>;
i-cache-line-size = <32>;
diff --git a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
index daa962d..ab3e800 100644
--- a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
+++ b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
@@ -18,13 +18,13 @@
#size-cells = <1>;
cpus {
- #address-cells = <1>;
+ #address-cells = <0>;
#size-cells = <0>;
- cpu@0 {
- compatible = "arm,1176jz-s";
+ cpu {
+ compatible = "arm,arm1176jz-s";
+ device_type = "cpu";
cpu-clock = <&arm_clk>, "cpu";
- reg = <0>;
d-cache-line-size = <32>;
d-cache-size = <32768>;
i-cache-line-size = <32>;
--
1.8.2.2
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [RFC PATCH v4 11/18] ARM: dts: picoxcell: cpus/cpu nodes dts updates
@ 2013-05-17 15:20 ` Lorenzo Pieralisi
0 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 15:20 UTC (permalink / raw)
To: linux-arm-kernel
This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
arch/arm/boot/dts/picoxcell-pc3x2.dtsi | 8 ++++----
arch/arm/boot/dts/picoxcell-pc3x3.dtsi | 8 ++++----
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
index f0a8c20..533919e 100644
--- a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
+++ b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
@@ -18,13 +18,13 @@
#size-cells = <1>;
cpus {
- #address-cells = <1>;
+ #address-cells = <0>;
#size-cells = <0>;
- cpu at 0 {
- compatible = "arm,1176jz-s";
+ cpu {
+ compatible = "arm,arm1176jz-s";
+ device_type = "cpu";
clock-frequency = <400000000>;
- reg = <0>;
d-cache-line-size = <32>;
d-cache-size = <32768>;
i-cache-line-size = <32>;
diff --git a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
index daa962d..ab3e800 100644
--- a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
+++ b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
@@ -18,13 +18,13 @@
#size-cells = <1>;
cpus {
- #address-cells = <1>;
+ #address-cells = <0>;
#size-cells = <0>;
- cpu at 0 {
- compatible = "arm,1176jz-s";
+ cpu {
+ compatible = "arm,arm1176jz-s";
+ device_type = "cpu";
cpu-clock = <&arm_clk>, "cpu";
- reg = <0>;
d-cache-line-size = <32>;
d-cache-size = <32768>;
i-cache-line-size = <32>;
--
1.8.2.2
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [RFC PATCH v4 12/18] ARM: dts: prima2: cpus/cpu node dts updates
2013-05-17 15:20 ` Lorenzo Pieralisi
@ 2013-05-17 15:20 ` Lorenzo Pieralisi
-1 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 15:20 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Nicolas Pitre, Jon Medhurst, Andrew Lunn, Will Deacon,
Viresh Kumar, Kukjin Kim, Lennert Buytenhek, Lorenzo Pieralisi,
Russell King, Magnus Damm, Catalin Marinas, Grant Likely,
David Brown, Sekhar Nori, Rob Herring, Simon Horman, Barry Song,
Vinayak Kale, Amit Kucheria
This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
Acked-by: Barry Song <Baohua.Song-kQvG35nSl+M@public.gmane.org>
---
arch/arm/boot/dts/prima2.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index 3329719..02edd89 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -18,6 +18,8 @@
#size-cells = <0>;
cpu@0 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
reg = <0x0>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
--
1.8.2.2
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [RFC PATCH v4 12/18] ARM: dts: prima2: cpus/cpu node dts updates
@ 2013-05-17 15:20 ` Lorenzo Pieralisi
0 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 15:20 UTC (permalink / raw)
To: linux-arm-kernel
This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Barry Song <Baohua.Song@csr.com>
---
arch/arm/boot/dts/prima2.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index 3329719..02edd89 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -18,6 +18,8 @@
#size-cells = <0>;
cpu at 0 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
reg = <0x0>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
--
1.8.2.2
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [RFC PATCH v4 13/18] ARM: dts: pxa2xx: cpus/cpu nodes dts updates
2013-05-17 15:20 ` Lorenzo Pieralisi
@ 2013-05-17 15:20 ` Lorenzo Pieralisi
-1 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 15:20 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Nicolas Pitre, Jon Medhurst, Andrew Lunn, Will Deacon,
Viresh Kumar, Kukjin Kim, Lennert Buytenhek, Lorenzo Pieralisi,
Russell King, Magnus Damm, Catalin Marinas, Grant Likely,
David Brown, Sekhar Nori, Rob Herring, Simon Horman, Barry Song,
Vinayak Kale, Amit Kucheria
This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
---
arch/arm/boot/dts/pxa2xx.dtsi | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi
index f18aad3..a5e90f0 100644
--- a/arch/arm/boot/dts/pxa2xx.dtsi
+++ b/arch/arm/boot/dts/pxa2xx.dtsi
@@ -23,8 +23,11 @@
};
cpus {
- cpu@0 {
- compatible = "arm,xscale";
+ #address-cells = <0>;
+ #size-cells = <0>;
+ cpu {
+ compatible = "marvell,xscale";
+ device_type = "cpu";
};
};
--
1.8.2.2
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [RFC PATCH v4 13/18] ARM: dts: pxa2xx: cpus/cpu nodes dts updates
@ 2013-05-17 15:20 ` Lorenzo Pieralisi
0 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 15:20 UTC (permalink / raw)
To: linux-arm-kernel
This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
arch/arm/boot/dts/pxa2xx.dtsi | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi
index f18aad3..a5e90f0 100644
--- a/arch/arm/boot/dts/pxa2xx.dtsi
+++ b/arch/arm/boot/dts/pxa2xx.dtsi
@@ -23,8 +23,11 @@
};
cpus {
- cpu at 0 {
- compatible = "arm,xscale";
+ #address-cells = <0>;
+ #size-cells = <0>;
+ cpu {
+ compatible = "marvell,xscale";
+ device_type = "cpu";
};
};
--
1.8.2.2
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [RFC PATCH v4 14/18] ARM: dts: r8a7740: cpus/cpu nodes dts updates
2013-05-17 15:20 ` Lorenzo Pieralisi
@ 2013-05-17 15:20 ` Lorenzo Pieralisi
-1 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 15:20 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Nicolas Pitre, Jon Medhurst, Andrew Lunn, Will Deacon,
Viresh Kumar, Kukjin Kim, Lennert Buytenhek, Lorenzo Pieralisi,
Russell King, Magnus Damm, Catalin Marinas, Grant Likely,
David Brown, Sekhar Nori, Rob Herring, Simon Horman, Barry Song,
Vinayak Kale, Amit Kucheria
This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
Acked-by: Simon Horman <horms+renesas-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org>
---
arch/arm/boot/dts/r8a7740.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index 798fa35..8a831e9 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -14,8 +14,12 @@
compatible = "renesas,r8a7740";
cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ reg = <0x0>;
};
};
};
--
1.8.2.2
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [RFC PATCH v4 14/18] ARM: dts: r8a7740: cpus/cpu nodes dts updates
@ 2013-05-17 15:20 ` Lorenzo Pieralisi
0 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 15:20 UTC (permalink / raw)
To: linux-arm-kernel
This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7740.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index 798fa35..8a831e9 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -14,8 +14,12 @@
compatible = "renesas,r8a7740";
cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
cpu at 0 {
compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ reg = <0x0>;
};
};
};
--
1.8.2.2
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [RFC PATCH v4 15/18] ARM: dts: sh7372: cpus/cpu nodes dts updates
2013-05-17 15:20 ` Lorenzo Pieralisi
@ 2013-05-17 15:20 ` Lorenzo Pieralisi
-1 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 15:20 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Nicolas Pitre, Jon Medhurst, Andrew Lunn, Will Deacon,
Viresh Kumar, Kukjin Kim, Lennert Buytenhek, Lorenzo Pieralisi,
Russell King, Magnus Damm, Catalin Marinas, Grant Likely,
David Brown, Sekhar Nori, Rob Herring, Simon Horman, Barry Song,
Vinayak Kale, Amit Kucheria
This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
Acked-by: Simon Horman <horms+renesas-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org>
---
arch/arm/boot/dts/sh7372.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sh7372.dtsi b/arch/arm/boot/dts/sh7372.dtsi
index 677fc60..7bf020e 100644
--- a/arch/arm/boot/dts/sh7372.dtsi
+++ b/arch/arm/boot/dts/sh7372.dtsi
@@ -14,8 +14,13 @@
compatible = "renesas,sh7372";
cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
cpu@0 {
compatible = "arm,cortex-a8";
+ device_type = "cpu";
+ reg = <0x0>;
};
};
};
--
1.8.2.2
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [RFC PATCH v4 15/18] ARM: dts: sh7372: cpus/cpu nodes dts updates
@ 2013-05-17 15:20 ` Lorenzo Pieralisi
0 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 15:20 UTC (permalink / raw)
To: linux-arm-kernel
This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/sh7372.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sh7372.dtsi b/arch/arm/boot/dts/sh7372.dtsi
index 677fc60..7bf020e 100644
--- a/arch/arm/boot/dts/sh7372.dtsi
+++ b/arch/arm/boot/dts/sh7372.dtsi
@@ -14,8 +14,13 @@
compatible = "renesas,sh7372";
cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
cpu at 0 {
compatible = "arm,cortex-a8";
+ device_type = "cpu";
+ reg = <0x0>;
};
};
};
--
1.8.2.2
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [RFC PATCH v4 16/18] ARM: dts: spear: cpus/cpu nodes dts updates
2013-05-17 15:20 ` Lorenzo Pieralisi
@ 2013-05-17 15:20 ` Lorenzo Pieralisi
-1 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 15:20 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Nicolas Pitre, Jon Medhurst, Andrew Lunn, Will Deacon,
Viresh Kumar, Kukjin Kim, Lennert Buytenhek, Lorenzo Pieralisi,
Russell King, Magnus Damm, Catalin Marinas, Grant Likely,
David Brown, Sekhar Nori, Rob Herring, Simon Horman, Barry Song,
Vinayak Kale, Amit Kucheria
This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
Acked-by: Viresh Kumar <viresh.kumar-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
arch/arm/boot/dts/spear13xx.dtsi | 2 ++
arch/arm/boot/dts/spear3xx.dtsi | 8 ++++++--
arch/arm/boot/dts/spear600.dtsi | 8 ++++++--
3 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index 45597fd..4382547 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -22,12 +22,14 @@
cpu@0 {
compatible = "arm,cortex-a9";
+ device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
};
cpu@1 {
compatible = "arm,cortex-a9";
+ device_type = "cpu";
reg = <1>;
next-level-cache = <&L2>;
};
diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi
index c2a852d..f0e3fcf 100644
--- a/arch/arm/boot/dts/spear3xx.dtsi
+++ b/arch/arm/boot/dts/spear3xx.dtsi
@@ -17,8 +17,12 @@
interrupt-parent = <&vic>;
cpus {
- cpu@0 {
- compatible = "arm,arm926ejs";
+ #address-cells = <0>;
+ #size-cells = <0>;
+
+ cpu {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
};
};
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
index 19f99dc..9f60a7b 100644
--- a/arch/arm/boot/dts/spear600.dtsi
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -15,8 +15,12 @@
compatible = "st,spear600";
cpus {
- cpu@0 {
- compatible = "arm,arm926ejs";
+ #address-cells = <0>;
+ #size-cells = <0>;
+
+ cpu {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
};
};
--
1.8.2.2
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [RFC PATCH v4 16/18] ARM: dts: spear: cpus/cpu nodes dts updates
@ 2013-05-17 15:20 ` Lorenzo Pieralisi
0 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 15:20 UTC (permalink / raw)
To: linux-arm-kernel
This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
---
arch/arm/boot/dts/spear13xx.dtsi | 2 ++
arch/arm/boot/dts/spear3xx.dtsi | 8 ++++++--
arch/arm/boot/dts/spear600.dtsi | 8 ++++++--
3 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index 45597fd..4382547 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -22,12 +22,14 @@
cpu at 0 {
compatible = "arm,cortex-a9";
+ device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
};
cpu at 1 {
compatible = "arm,cortex-a9";
+ device_type = "cpu";
reg = <1>;
next-level-cache = <&L2>;
};
diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi
index c2a852d..f0e3fcf 100644
--- a/arch/arm/boot/dts/spear3xx.dtsi
+++ b/arch/arm/boot/dts/spear3xx.dtsi
@@ -17,8 +17,12 @@
interrupt-parent = <&vic>;
cpus {
- cpu at 0 {
- compatible = "arm,arm926ejs";
+ #address-cells = <0>;
+ #size-cells = <0>;
+
+ cpu {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
};
};
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
index 19f99dc..9f60a7b 100644
--- a/arch/arm/boot/dts/spear600.dtsi
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -15,8 +15,12 @@
compatible = "st,spear600";
cpus {
- cpu at 0 {
- compatible = "arm,arm926ejs";
+ #address-cells = <0>;
+ #size-cells = <0>;
+
+ cpu {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
};
};
--
1.8.2.2
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [RFC PATCH v4 17/18] ARM: dts: sunxi: cpus/cpu nodes dts updates
2013-05-17 15:20 ` Lorenzo Pieralisi
@ 2013-05-17 15:21 ` Lorenzo Pieralisi
-1 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 15:21 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Nicolas Pitre, Jon Medhurst, Andrew Lunn, Will Deacon,
Viresh Kumar, Kukjin Kim, Lennert Buytenhek, Lorenzo Pieralisi,
Russell King, Magnus Damm, Catalin Marinas, Grant Likely,
David Brown, Sekhar Nori, Rob Herring, Simon Horman, Barry Song,
Vinayak Kale, Amit Kucheria
This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
Acked-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
arch/arm/boot/dts/sun4i-a10.dtsi | 2 ++
arch/arm/boot/dts/sun5i-a13.dtsi | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index e7ef619..39a8f61 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -17,7 +17,9 @@
cpus {
cpu@0 {
+ device_type = "cpu";
compatible = "arm,cortex-a8";
+ reg = <0x0>;
};
};
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 31fa38f..00a2637 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -18,7 +18,9 @@
cpus {
cpu@0 {
+ device_type = "cpu";
compatible = "arm,cortex-a8";
+ reg = <0x0>;
};
};
--
1.8.2.2
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [RFC PATCH v4 17/18] ARM: dts: sunxi: cpus/cpu nodes dts updates
@ 2013-05-17 15:21 ` Lorenzo Pieralisi
0 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 15:21 UTC (permalink / raw)
To: linux-arm-kernel
This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun4i-a10.dtsi | 2 ++
arch/arm/boot/dts/sun5i-a13.dtsi | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index e7ef619..39a8f61 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -17,7 +17,9 @@
cpus {
cpu at 0 {
+ device_type = "cpu";
compatible = "arm,cortex-a8";
+ reg = <0x0>;
};
};
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 31fa38f..00a2637 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -18,7 +18,9 @@
cpus {
cpu at 0 {
+ device_type = "cpu";
compatible = "arm,cortex-a8";
+ reg = <0x0>;
};
};
--
1.8.2.2
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [RFC PATCH v4 18/18] ARM: DT: kernel: DT cpus/cpu node bindings update
2013-05-17 15:20 ` Lorenzo Pieralisi
@ 2013-05-17 15:21 ` Lorenzo Pieralisi
-1 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 15:21 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
Cc: Nicolas Pitre, Jon Medhurst, Andrew Lunn, Will Deacon,
Viresh Kumar, Kukjin Kim, Lennert Buytenhek, Lorenzo Pieralisi,
Russell King, Magnus Damm, Catalin Marinas, Grant Likely,
David Brown, Sekhar Nori, Rob Herring, Simon Horman, Barry Song,
Vinayak Kale, Amit Kucheria
DT cpu map parsing code must be made compliant with the latest cpus/cpu
nodes bindings updates, hence this patch updates the arm_dt_init_cpu_maps()
function with checks and additional parsing rules.
Uniprocessor systems predating v7 do not parse the cpus node at all
since the reg property is meaningless on those systems.
Device trees for 64-bit systems can be taken as device tree input also
for 64-bit CPUs running in 32-bit mode. The code checks that the reg entries
are zeroed as required in the respective fields and detects automatically
the cpus node #address-cells value so that device tree written for
64-bit ARM platforms (that can have cpus node #address-cells == 2) can still
be taken as input. The correct device tree entries are to be set up by the
boot loader, kernel code just checks that device tree entries in the cpus
node are as expected for a 32-bit CPU (reg[63:24] == 0).
cpu node entries with invalid reg property or containing duplicates are
ignored and the device tree parsing is not stopped anymore when such
entries are encountered, the device tree cpu node entry is just skipped.
A device tree with cpu nodes missing the boot CPU MPIDR is considered
an error and the kernel flags this up as such to trigger firmware updates.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
---
arch/arm/kernel/devtree.c | 146 ++++++++++++++++++++++++++++------------------
1 file changed, 88 insertions(+), 58 deletions(-)
diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
index 0905502..80d6cf24 100644
--- a/arch/arm/kernel/devtree.c
+++ b/arch/arm/kernel/devtree.c
@@ -23,6 +23,7 @@
#include <asm/setup.h>
#include <asm/page.h>
#include <asm/smp_plat.h>
+#include <asm/system_info.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
@@ -72,100 +73,129 @@ void __init arm_dt_memblock_reserve(void)
*/
void __init arm_dt_init_cpu_maps(void)
{
- /*
- * Temp logical map is initialized with UINT_MAX values that are
- * considered invalid logical map entries since the logical map must
- * contain a list of MPIDR[23:0] values where MPIDR[31:24] must
- * read as 0.
- */
struct device_node *cpu, *cpus;
- u32 i, j, cpuidx = 1;
+ u32 i, ac, cpuidx = 1;
+ int len;
u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
- u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
bool bootcpu_valid = false;
cpus = of_find_node_by_path("/cpus");
- if (!cpus)
+ if (!cpus || ((cpu_architecture() < CPU_ARCH_ARMv7) && !is_smp()))
return;
+ if (of_property_read_u32(cpus, "#address-cells", &ac)) {
+ pr_warn("%s invalid #address-cells\n", cpus->full_name);
+ ac = of_n_addr_cells(cpus);
+ }
+ /*
+ * The boot CPU knows its MPIDR and initialize it
+ * to allow DT boot CPU detection.
+ */
+ cpu_logical_map(0) = mpidr;
+
for_each_child_of_node(cpus, cpu) {
- u32 hwid;
+ u64 hwid64;
+ u32 hwid32;
+ const __be32 *prop;
if (of_node_cmp(cpu->type, "cpu"))
continue;
pr_debug(" * %s...\n", cpu->full_name);
/*
- * A device tree containing CPU nodes with missing "reg"
- * properties is considered invalid to build the
- * cpu_logical_map.
+ * A CPU node with missing or wrong "reg" property is
+ * considered invalid to build a cpu_logical_map entry.
*/
- if (of_property_read_u32(cpu, "reg", &hwid)) {
- pr_debug(" * %s missing reg property\n",
- cpu->full_name);
- return;
+ prop = of_get_property(cpu, "reg", &len);
+ if (!prop || len < (ac * sizeof(*prop))) {
+ pr_warn(" * %s node missing/wrong reg property, skipped\n",
+ cpu->full_name);
+ goto next;
}
/*
- * 8 MSBs must be set to 0 in the DT since the reg property
- * defines the MPIDR[23:0].
+ * Always read reg as u64 value.
+ * For dts with #address-cells == 1 hwid64[63:32]
+ * will be set to 0 by of_read_number.
+ * Toss away the top 32 bits and store value in hwid32.
*/
- if (hwid & ~MPIDR_HWID_BITMASK)
- return;
-
+ hwid32 = hwid64 = of_read_number(prop, ac);
+ /*
+ * hwid64[63:24] must be always be 0 since the reg
+ * property defines the MPIDR[23:0] bits regardless
+ * of the cpus node #address-cells value.
+ */
+ if (hwid64 & ~MPIDR_HWID_BITMASK) {
+ pr_warn(" * %s node reg[63:24] must be 0 on 32-bit dts, got %#016llx, skipped\n",
+ cpu->full_name, hwid64);
+ goto next;
+ }
/*
* Duplicate MPIDRs are a recipe for disaster.
* Scan all initialized entries and check for
- * duplicates. If any is found just bail out.
- * temp values were initialized to UINT_MAX
- * to avoid matching valid MPIDR[23:0] values.
+ * duplicates. If any is found just ignore the CPU.
+ * Boot CPU at logical index 0 is not checked to
+ * allow self contained boot CPU detection logic.
*/
- for (j = 0; j < cpuidx; j++)
- if (WARN(tmp_map[j] == hwid, "Duplicate /cpu reg "
- "properties in the DT\n"))
- return;
+ for (i = 1; i < cpuidx; i++)
+ if (cpu_logical_map(i) == hwid32) {
+ pr_warn(" * %s node duplicate cpu reg property, skipped\n",
+ cpu->full_name);
+ goto next;
+ }
/*
- * Build a stashed array of MPIDR values. Numbering scheme
- * requires that if detected the boot CPU must be assigned
- * logical id 0. Other CPUs get sequential indexes starting
- * from 1. If a CPU node with a reg property matching the
- * boot CPU MPIDR is detected, this is recorded so that the
- * logical map built from DT is validated and can be used
- * to override the map created in smp_setup_processor_id().
+ * If a CPU node with a reg property matching the
+ * cpu_logical_map(0) is detected, this is recorded so
+ * that the bootcpu_valid condition can be checked when
+ * DT scanning is completed. Duplicate boot cpu entries
+ * are flagged up if detected.
*/
- if (hwid == mpidr) {
- i = 0;
- bootcpu_valid = true;
- } else {
- i = cpuidx++;
+ if (hwid32 == cpu_logical_map(0)) {
+ if (bootcpu_valid) {
+ pr_warn(" * %s node duplicate boot cpu reg property, skipped\n",
+ cpu->full_name);
+ } else {
+ bootcpu_valid = true;
+ }
+ goto next;
}
+ /*
+ * Build cpu_logical_map array. Numbering scheme
+ * requires that boot CPU is assigned logical id 0.
+ * Other CPUs get sequential indexes starting from 1.
+ */
+ i = cpuidx++;
- if (WARN(cpuidx > nr_cpu_ids, "DT /cpu %u nodes greater than "
- "max cores %u, capping them\n",
- cpuidx, nr_cpu_ids)) {
+ if (cpuidx > nr_cpu_ids) {
+ pr_warn_once("DT cpu %u nodes greater than max cores %u, capping them\n",
+ cpuidx, nr_cpu_ids);
cpuidx = nr_cpu_ids;
- break;
+ goto next;
}
- tmp_map[i] = hwid;
+ cpu_logical_map(i) = hwid32;
+ set_cpu_possible(i, true);
+ pr_debug("cpu_logical_map(%u) 0x%x\n", i, cpu_logical_map(i));
+next: ;
}
-
- if (WARN(!bootcpu_valid, "DT missing boot CPU MPIDR[23:0], "
- "fall back to default cpu_logical_map\n"))
- return;
+ /*
+ * A DT missing the boot CPU MPIDR is a really bad omen
+ * Flag it up as such.
+ */
+ if (!bootcpu_valid)
+ pr_warn("DT missing boot cpu node\n");
/*
- * Since the boot CPU node contains proper data, and all nodes have
- * a reg property, the DT CPU list can be considered valid and the
- * logical map created in smp_setup_processor_id() can be overridden
+ * Since the DT might contain fewer entries than NR_CPUS,
+ * cpu_logical_map entries initialized in smp_setup_processor_id()
+ * but not found in the DT must be overriden with MPIDR_INVALID
+ * values to make sure the cpu_logical_map does not contain stale
+ * MPIDR values.
*/
- for (i = 0; i < cpuidx; i++) {
- set_cpu_possible(i, true);
- cpu_logical_map(i) = tmp_map[i];
- pr_debug("cpu logical map 0x%x\n", cpu_logical_map(i));
- }
+ for (i = cpuidx; i < nr_cpu_ids; i++)
+ cpu_logical_map(i) = MPIDR_INVALID;
}
/**
--
1.8.2.2
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [RFC PATCH v4 18/18] ARM: DT: kernel: DT cpus/cpu node bindings update
@ 2013-05-17 15:21 ` Lorenzo Pieralisi
0 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 15:21 UTC (permalink / raw)
To: linux-arm-kernel
DT cpu map parsing code must be made compliant with the latest cpus/cpu
nodes bindings updates, hence this patch updates the arm_dt_init_cpu_maps()
function with checks and additional parsing rules.
Uniprocessor systems predating v7 do not parse the cpus node at all
since the reg property is meaningless on those systems.
Device trees for 64-bit systems can be taken as device tree input also
for 64-bit CPUs running in 32-bit mode. The code checks that the reg entries
are zeroed as required in the respective fields and detects automatically
the cpus node #address-cells value so that device tree written for
64-bit ARM platforms (that can have cpus node #address-cells == 2) can still
be taken as input. The correct device tree entries are to be set up by the
boot loader, kernel code just checks that device tree entries in the cpus
node are as expected for a 32-bit CPU (reg[63:24] == 0).
cpu node entries with invalid reg property or containing duplicates are
ignored and the device tree parsing is not stopped anymore when such
entries are encountered, the device tree cpu node entry is just skipped.
A device tree with cpu nodes missing the boot CPU MPIDR is considered
an error and the kernel flags this up as such to trigger firmware updates.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
arch/arm/kernel/devtree.c | 146 ++++++++++++++++++++++++++++------------------
1 file changed, 88 insertions(+), 58 deletions(-)
diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
index 0905502..80d6cf24 100644
--- a/arch/arm/kernel/devtree.c
+++ b/arch/arm/kernel/devtree.c
@@ -23,6 +23,7 @@
#include <asm/setup.h>
#include <asm/page.h>
#include <asm/smp_plat.h>
+#include <asm/system_info.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
@@ -72,100 +73,129 @@ void __init arm_dt_memblock_reserve(void)
*/
void __init arm_dt_init_cpu_maps(void)
{
- /*
- * Temp logical map is initialized with UINT_MAX values that are
- * considered invalid logical map entries since the logical map must
- * contain a list of MPIDR[23:0] values where MPIDR[31:24] must
- * read as 0.
- */
struct device_node *cpu, *cpus;
- u32 i, j, cpuidx = 1;
+ u32 i, ac, cpuidx = 1;
+ int len;
u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
- u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
bool bootcpu_valid = false;
cpus = of_find_node_by_path("/cpus");
- if (!cpus)
+ if (!cpus || ((cpu_architecture() < CPU_ARCH_ARMv7) && !is_smp()))
return;
+ if (of_property_read_u32(cpus, "#address-cells", &ac)) {
+ pr_warn("%s invalid #address-cells\n", cpus->full_name);
+ ac = of_n_addr_cells(cpus);
+ }
+ /*
+ * The boot CPU knows its MPIDR and initialize it
+ * to allow DT boot CPU detection.
+ */
+ cpu_logical_map(0) = mpidr;
+
for_each_child_of_node(cpus, cpu) {
- u32 hwid;
+ u64 hwid64;
+ u32 hwid32;
+ const __be32 *prop;
if (of_node_cmp(cpu->type, "cpu"))
continue;
pr_debug(" * %s...\n", cpu->full_name);
/*
- * A device tree containing CPU nodes with missing "reg"
- * properties is considered invalid to build the
- * cpu_logical_map.
+ * A CPU node with missing or wrong "reg" property is
+ * considered invalid to build a cpu_logical_map entry.
*/
- if (of_property_read_u32(cpu, "reg", &hwid)) {
- pr_debug(" * %s missing reg property\n",
- cpu->full_name);
- return;
+ prop = of_get_property(cpu, "reg", &len);
+ if (!prop || len < (ac * sizeof(*prop))) {
+ pr_warn(" * %s node missing/wrong reg property, skipped\n",
+ cpu->full_name);
+ goto next;
}
/*
- * 8 MSBs must be set to 0 in the DT since the reg property
- * defines the MPIDR[23:0].
+ * Always read reg as u64 value.
+ * For dts with #address-cells == 1 hwid64[63:32]
+ * will be set to 0 by of_read_number.
+ * Toss away the top 32 bits and store value in hwid32.
*/
- if (hwid & ~MPIDR_HWID_BITMASK)
- return;
-
+ hwid32 = hwid64 = of_read_number(prop, ac);
+ /*
+ * hwid64[63:24] must be always be 0 since the reg
+ * property defines the MPIDR[23:0] bits regardless
+ * of the cpus node #address-cells value.
+ */
+ if (hwid64 & ~MPIDR_HWID_BITMASK) {
+ pr_warn(" * %s node reg[63:24] must be 0 on 32-bit dts, got %#016llx, skipped\n",
+ cpu->full_name, hwid64);
+ goto next;
+ }
/*
* Duplicate MPIDRs are a recipe for disaster.
* Scan all initialized entries and check for
- * duplicates. If any is found just bail out.
- * temp values were initialized to UINT_MAX
- * to avoid matching valid MPIDR[23:0] values.
+ * duplicates. If any is found just ignore the CPU.
+ * Boot CPU at logical index 0 is not checked to
+ * allow self contained boot CPU detection logic.
*/
- for (j = 0; j < cpuidx; j++)
- if (WARN(tmp_map[j] == hwid, "Duplicate /cpu reg "
- "properties in the DT\n"))
- return;
+ for (i = 1; i < cpuidx; i++)
+ if (cpu_logical_map(i) == hwid32) {
+ pr_warn(" * %s node duplicate cpu reg property, skipped\n",
+ cpu->full_name);
+ goto next;
+ }
/*
- * Build a stashed array of MPIDR values. Numbering scheme
- * requires that if detected the boot CPU must be assigned
- * logical id 0. Other CPUs get sequential indexes starting
- * from 1. If a CPU node with a reg property matching the
- * boot CPU MPIDR is detected, this is recorded so that the
- * logical map built from DT is validated and can be used
- * to override the map created in smp_setup_processor_id().
+ * If a CPU node with a reg property matching the
+ * cpu_logical_map(0) is detected, this is recorded so
+ * that the bootcpu_valid condition can be checked when
+ * DT scanning is completed. Duplicate boot cpu entries
+ * are flagged up if detected.
*/
- if (hwid == mpidr) {
- i = 0;
- bootcpu_valid = true;
- } else {
- i = cpuidx++;
+ if (hwid32 == cpu_logical_map(0)) {
+ if (bootcpu_valid) {
+ pr_warn(" * %s node duplicate boot cpu reg property, skipped\n",
+ cpu->full_name);
+ } else {
+ bootcpu_valid = true;
+ }
+ goto next;
}
+ /*
+ * Build cpu_logical_map array. Numbering scheme
+ * requires that boot CPU is assigned logical id 0.
+ * Other CPUs get sequential indexes starting from 1.
+ */
+ i = cpuidx++;
- if (WARN(cpuidx > nr_cpu_ids, "DT /cpu %u nodes greater than "
- "max cores %u, capping them\n",
- cpuidx, nr_cpu_ids)) {
+ if (cpuidx > nr_cpu_ids) {
+ pr_warn_once("DT cpu %u nodes greater than max cores %u, capping them\n",
+ cpuidx, nr_cpu_ids);
cpuidx = nr_cpu_ids;
- break;
+ goto next;
}
- tmp_map[i] = hwid;
+ cpu_logical_map(i) = hwid32;
+ set_cpu_possible(i, true);
+ pr_debug("cpu_logical_map(%u) 0x%x\n", i, cpu_logical_map(i));
+next: ;
}
-
- if (WARN(!bootcpu_valid, "DT missing boot CPU MPIDR[23:0], "
- "fall back to default cpu_logical_map\n"))
- return;
+ /*
+ * A DT missing the boot CPU MPIDR is a really bad omen
+ * Flag it up as such.
+ */
+ if (!bootcpu_valid)
+ pr_warn("DT missing boot cpu node\n");
/*
- * Since the boot CPU node contains proper data, and all nodes have
- * a reg property, the DT CPU list can be considered valid and the
- * logical map created in smp_setup_processor_id() can be overridden
+ * Since the DT might contain fewer entries than NR_CPUS,
+ * cpu_logical_map entries initialized in smp_setup_processor_id()
+ * but not found in the DT must be overriden with MPIDR_INVALID
+ * values to make sure the cpu_logical_map does not contain stale
+ * MPIDR values.
*/
- for (i = 0; i < cpuidx; i++) {
- set_cpu_possible(i, true);
- cpu_logical_map(i) = tmp_map[i];
- pr_debug("cpu logical map 0x%x\n", cpu_logical_map(i));
- }
+ for (i = cpuidx; i < nr_cpu_ids; i++)
+ cpu_logical_map(i) = MPIDR_INVALID;
}
/**
--
1.8.2.2
^ permalink raw reply related [flat|nested] 64+ messages in thread
* Re: [RFC PATCH v4 02/18] ARM: kernel: fix __cpu_logical_map default initialization
2013-05-17 15:20 ` Lorenzo Pieralisi
@ 2013-05-17 15:46 ` Nicolas Pitre
-1 siblings, 0 replies; 64+ messages in thread
From: Nicolas Pitre @ 2013-05-17 15:46 UTC (permalink / raw)
To: Lorenzo Pieralisi
Cc: Jon Medhurst, Andrew Lunn, Kukjin Kim, Russell King,
Viresh Kumar, devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
Barry Song, Will Deacon, Sekhar Nori, Simon Horman, Rob Herring,
Amit Kucheria, Catalin Marinas, Grant Likely, David Brown,
Vinayak Kale, Lennert Buytenhek,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Magnus Damm
On Fri, 17 May 2013, Lorenzo Pieralisi wrote:
> The __cpu_logical_map array is statically initialized to 0, which is a valid
> MPIDR value. To prevent issues with the current implementation, this patch
> defines an MPIDR_INVALID value, and statically initializes the
> __cpu_logical_map[] array to it. Entries in the arm_dt_init_cpu_maps()
> tmp_map array used to stash DT reg properties while parsing DT are initialized
> with the MPIDR_INVALID value as well for consistency.
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
> CC: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>
Acked-by: Nicolas Pitre <nico-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
> arch/arm/include/asm/cputype.h | 2 ++
> arch/arm/include/asm/smp_plat.h | 2 +-
> arch/arm/kernel/devtree.c | 2 +-
> arch/arm/kernel/setup.c | 2 +-
> 4 files changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
> index 7652712..dba62cb 100644
> --- a/arch/arm/include/asm/cputype.h
> +++ b/arch/arm/include/asm/cputype.h
> @@ -32,6 +32,8 @@
>
> #define MPIDR_HWID_BITMASK 0xFFFFFF
>
> +#define MPIDR_INVALID (~MPIDR_HWID_BITMASK)
> +
> #define MPIDR_LEVEL_BITS 8
> #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
>
> diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
> index aaa61b6..e789832 100644
> --- a/arch/arm/include/asm/smp_plat.h
> +++ b/arch/arm/include/asm/smp_plat.h
> @@ -49,7 +49,7 @@ static inline int cache_ops_need_broadcast(void)
> /*
> * Logical CPU mapping.
> */
> -extern int __cpu_logical_map[];
> +extern u32 __cpu_logical_map[];
> #define cpu_logical_map(cpu) __cpu_logical_map[cpu]
> /*
> * Retrieve logical cpu index corresponding to a given MPIDR[23:0]
> diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
> index 904cad5..0905502 100644
> --- a/arch/arm/kernel/devtree.c
> +++ b/arch/arm/kernel/devtree.c
> @@ -82,7 +82,7 @@ void __init arm_dt_init_cpu_maps(void)
> u32 i, j, cpuidx = 1;
> u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
>
> - u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = UINT_MAX };
> + u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
> bool bootcpu_valid = false;
> cpus = of_find_node_by_path("/cpus");
>
> diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
> index 6ae71b7..eeac924 100644
> --- a/arch/arm/kernel/setup.c
> +++ b/arch/arm/kernel/setup.c
> @@ -457,7 +457,7 @@ void notrace cpu_init(void)
> : "r14");
> }
>
> -int __cpu_logical_map[NR_CPUS];
> +u32 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
>
> void __init smp_setup_processor_id(void)
> {
> --
> 1.8.2.2
>
>
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss
>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [RFC PATCH v4 02/18] ARM: kernel: fix __cpu_logical_map default initialization
@ 2013-05-17 15:46 ` Nicolas Pitre
0 siblings, 0 replies; 64+ messages in thread
From: Nicolas Pitre @ 2013-05-17 15:46 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, 17 May 2013, Lorenzo Pieralisi wrote:
> The __cpu_logical_map array is statically initialized to 0, which is a valid
> MPIDR value. To prevent issues with the current implementation, this patch
> defines an MPIDR_INVALID value, and statically initializes the
> __cpu_logical_map[] array to it. Entries in the arm_dt_init_cpu_maps()
> tmp_map array used to stash DT reg properties while parsing DT are initialized
> with the MPIDR_INVALID value as well for consistency.
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> CC: Will Deacon <will.deacon@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
> ---
> arch/arm/include/asm/cputype.h | 2 ++
> arch/arm/include/asm/smp_plat.h | 2 +-
> arch/arm/kernel/devtree.c | 2 +-
> arch/arm/kernel/setup.c | 2 +-
> 4 files changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
> index 7652712..dba62cb 100644
> --- a/arch/arm/include/asm/cputype.h
> +++ b/arch/arm/include/asm/cputype.h
> @@ -32,6 +32,8 @@
>
> #define MPIDR_HWID_BITMASK 0xFFFFFF
>
> +#define MPIDR_INVALID (~MPIDR_HWID_BITMASK)
> +
> #define MPIDR_LEVEL_BITS 8
> #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
>
> diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
> index aaa61b6..e789832 100644
> --- a/arch/arm/include/asm/smp_plat.h
> +++ b/arch/arm/include/asm/smp_plat.h
> @@ -49,7 +49,7 @@ static inline int cache_ops_need_broadcast(void)
> /*
> * Logical CPU mapping.
> */
> -extern int __cpu_logical_map[];
> +extern u32 __cpu_logical_map[];
> #define cpu_logical_map(cpu) __cpu_logical_map[cpu]
> /*
> * Retrieve logical cpu index corresponding to a given MPIDR[23:0]
> diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
> index 904cad5..0905502 100644
> --- a/arch/arm/kernel/devtree.c
> +++ b/arch/arm/kernel/devtree.c
> @@ -82,7 +82,7 @@ void __init arm_dt_init_cpu_maps(void)
> u32 i, j, cpuidx = 1;
> u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
>
> - u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = UINT_MAX };
> + u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
> bool bootcpu_valid = false;
> cpus = of_find_node_by_path("/cpus");
>
> diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
> index 6ae71b7..eeac924 100644
> --- a/arch/arm/kernel/setup.c
> +++ b/arch/arm/kernel/setup.c
> @@ -457,7 +457,7 @@ void notrace cpu_init(void)
> : "r14");
> }
>
> -int __cpu_logical_map[NR_CPUS];
> +u32 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
>
> void __init smp_setup_processor_id(void)
> {
> --
> 1.8.2.2
>
>
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss at lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss
>
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [RFC PATCH v4 01/18] ARM: kernel: fix arm_dt_init_cpu_maps() to skip non-cpu nodes
2013-05-17 15:20 ` Lorenzo Pieralisi
@ 2013-05-17 15:49 ` Nicolas Pitre
-1 siblings, 0 replies; 64+ messages in thread
From: Nicolas Pitre @ 2013-05-17 15:49 UTC (permalink / raw)
To: Lorenzo Pieralisi
Cc: Jon Medhurst, Andrew Lunn, Will Deacon, Viresh Kumar,
Lennert Buytenhek, Kukjin Kim, Russell King, Magnus Damm,
Catalin Marinas, Grant Likely, David Brown, Sekhar Nori,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Rob Herring,
Simon Horman, Barry Song,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Vinayak Kale,
Amit Kucheria
On Fri, 17 May 2013, Lorenzo Pieralisi wrote:
> The introduction of the cpu-map topology node in the cpus node implies
> that cpus node might have children that are not cpu nodes. The DT
> parsing code needs updating otherwise it would check for cpu nodes
> properties in nodes that are not required to contain them, resulting
> in warnings that have no bearing on bindings defined in the dts source file.
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
Acked-by: Nicolas Pitre <nico-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
> arch/arm/kernel/devtree.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
> index 5af04f6..904cad5 100644
> --- a/arch/arm/kernel/devtree.c
> +++ b/arch/arm/kernel/devtree.c
> @@ -92,6 +92,9 @@ void __init arm_dt_init_cpu_maps(void)
> for_each_child_of_node(cpus, cpu) {
> u32 hwid;
>
> + if (of_node_cmp(cpu->type, "cpu"))
> + continue;
> +
> pr_debug(" * %s...\n", cpu->full_name);
> /*
> * A device tree containing CPU nodes with missing "reg"
> --
> 1.8.2.2
>
>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [RFC PATCH v4 01/18] ARM: kernel: fix arm_dt_init_cpu_maps() to skip non-cpu nodes
@ 2013-05-17 15:49 ` Nicolas Pitre
0 siblings, 0 replies; 64+ messages in thread
From: Nicolas Pitre @ 2013-05-17 15:49 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, 17 May 2013, Lorenzo Pieralisi wrote:
> The introduction of the cpu-map topology node in the cpus node implies
> that cpus node might have children that are not cpu nodes. The DT
> parsing code needs updating otherwise it would check for cpu nodes
> properties in nodes that are not required to contain them, resulting
> in warnings that have no bearing on bindings defined in the dts source file.
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
> ---
> arch/arm/kernel/devtree.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
> index 5af04f6..904cad5 100644
> --- a/arch/arm/kernel/devtree.c
> +++ b/arch/arm/kernel/devtree.c
> @@ -92,6 +92,9 @@ void __init arm_dt_init_cpu_maps(void)
> for_each_child_of_node(cpus, cpu) {
> u32 hwid;
>
> + if (of_node_cmp(cpu->type, "cpu"))
> + continue;
> +
> pr_debug(" * %s...\n", cpu->full_name);
> /*
> * A device tree containing CPU nodes with missing "reg"
> --
> 1.8.2.2
>
>
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [RFC PATCH v4 03/18] Documentation: devicetree: arm: cpus/cpu nodes bindings updates
2013-05-17 15:20 ` Lorenzo Pieralisi
@ 2013-05-17 16:07 ` Nicolas Pitre
-1 siblings, 0 replies; 64+ messages in thread
From: Nicolas Pitre @ 2013-05-17 16:07 UTC (permalink / raw)
To: Lorenzo Pieralisi
Cc: Jon Medhurst, Andrew Lunn, Will Deacon, Viresh Kumar,
Lennert Buytenhek, Kukjin Kim, Russell King, Magnus Damm,
Catalin Marinas, Grant Likely, David Brown, Sekhar Nori,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Rob Herring,
Simon Horman, Barry Song,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Vinayak Kale,
Amit Kucheria
On Fri, 17 May 2013, Lorenzo Pieralisi wrote:
> In order to extend the current cpu nodes bindings to newer CPUs
> inclusive of AArch64 and to update support for older ARM CPUs this
> patch updates device tree documentation for the cpu nodes bindings.
>
> Main changes:
> - adds 64-bit bindings
> - define usage of #address-cells
> - define 32/64 dts compatibility settings
> - defines behaviour on pre and post v7 uniprocessor systems
> - adds ARM 11MPcore specific reg property definition
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
Acked-by: Nicolas Pitre <nico-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
> Documentation/devicetree/bindings/arm/cpus.txt | 459 ++++++++++++++++++++++---
> 1 file changed, 412 insertions(+), 47 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> index f32494d..3fc0c11 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.txt
> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> @@ -1,77 +1,442 @@
> -* ARM CPUs binding description
> +=================
> +ARM CPUs bindings
> +=================
>
> The device tree allows to describe the layout of CPUs in a system through
> the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
> defining properties for every cpu.
>
> -Bindings for CPU nodes follow the ePAPR standard, available from:
> -
> -http://devicetree.org
> -
> -For the ARM architecture every CPU node must contain the following properties:
> -
> -- device_type: must be "cpu"
> -- reg: property matching the CPU MPIDR[23:0] register bits
> - reg[31:24] bits must be set to 0
> -- compatible: should be one of:
> - "arm,arm1020"
> - "arm,arm1020e"
> - "arm,arm1022"
> - "arm,arm1026"
> - "arm,arm720"
> - "arm,arm740"
> - "arm,arm7tdmi"
> - "arm,arm920"
> - "arm,arm922"
> - "arm,arm925"
> - "arm,arm926"
> - "arm,arm940"
> - "arm,arm946"
> - "arm,arm9tdmi"
> - "arm,cortex-a5"
> - "arm,cortex-a7"
> - "arm,cortex-a8"
> - "arm,cortex-a9"
> - "arm,cortex-a15"
> - "arm,arm1136"
> - "arm,arm1156"
> - "arm,arm1176"
> - "arm,arm11mpcore"
> - "faraday,fa526"
> - "intel,sa110"
> - "intel,sa1100"
> - "marvell,feroceon"
> - "marvell,mohawk"
> - "marvell,xsc3"
> - "marvell,xscale"
> -
> -Example:
> +Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
> +
> +https://www.power.org/documentation/epapr-version-1-1/
> +
> +with updates for 32-bit and 64-bit ARM systems provided in this document.
> +
> +================================
> +Convention used in this document
> +================================
> +
> +This document follows the conventions described in the ePAPR v1.1, with
> +the addition:
> +
> +- square brackets define bitfields, eg reg[7:0] value of the bitfield in
> + the reg property contained in bits 7 down to 0
> +
> +=====================================
> +cpus and cpu node bindings definition
> +=====================================
> +
> +The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
> +nodes to be present and contain the properties described below.
> +
> +- cpus node
> +
> + Description: Container of cpu nodes
> +
> + The node name must be "cpus".
> +
> + A cpus node must define the following properties:
> +
> + - #address-cells
> + Usage: required
> + Value type: <u32>
> +
> + Definition depends on ARM architecture version and
> + configuration:
> +
> + # On uniprocessor ARM architectures previous to v7
> + value must be 0.
> + # On 32-bit ARM 11 MPcore, ARM v7 or later systems
> + value must be 1.
> + # On ARM v8 64-bit systems value must be set to 1
> + or 2. Refer to the cpu node's reg property
> + description for allowed configurations.
> +
> + - #size-cells
> + Usage: required
> + Value type: <u32>
> + Definition: must be set to 0
> +
> +- cpu node
> +
> + Description: Describes a CPU in an ARM based system
> +
> + PROPERTIES
> +
> + - device_type
> + Usage: required
> + Value type: <string>
> + Definition: must be "cpu"
> + - reg
> + Usage and definition depend on ARM architecture version and
> + configuration:
> +
> + # On uniprocessor ARM architectures previous to v7
> + this property is optional since they do not define
> + any register that provides a CPU identifier.
> + Any value set in the reg property for these CPUs
> + should be ignored.
> +
> + # On ARM 11 MPcore based systems this property is
> + required and matches the CPUID[11:0] register bits.
> +
> + Bits [11:0] in the reg cell must be set to
> + bits [11:0] in CPU ID register.
> +
> + All other bits in the reg cell must be set to 0.
> +
> + # On 32-bit ARM v7 or later systems this property is
> + required and matches the CPU MPIDR[23:0] register
> + bits.
> +
> + Bits [23:0] in the reg cell must be set to
> + bits [23:0] in MPIDR.
> +
> + All other bits in the reg cell must be set to 0.
> +
> + # On ARM v8 64-bit systems, where the reg property
> + size can be 1 or 2 cells (as defined by cpus node's
> + #address-cells property), this property is
> + required and matches:
> +
> + - On systems running the OS in AArch32:
> +
> + * If the cpus node's #address-cells value is 2:
> +
> + The first reg cell must be set to 0.
> +
> + The second reg cell bits [23:0] must be set to
> + bits [23:0] of MPIDR_EL1.
> +
> + All other bits in the reg cells must be set to 0.
> +
> + * If the cpus node's #address-cells value is 1:
> +
> + Bits [23:0] in the reg cell must be set to
> + bits [23:0] in MPIDR_EL1.
> +
> + All other bits in the reg cell must be 0.
> +
> + - On systems running the OS in AArch64:
> +
> + * If the cpus node's #address-cells value is 2:
> +
> + The first reg cell bits [7:0] must be set to
> + bits [39:32] of MPIDR_EL1.
> +
> + The second reg cell bits [23:0] must be set to
> + bits [23:0] of MPIDR_EL1.
> +
> + All other bits in the reg cells must be set to 0.
> +
> + * If the cpus node's #address-cells value is 1:
> +
> + MPIDR_EL1[63:32] is 0 on all processors in the
> + system.
> +
> + The reg cell bits [23:0] must be set to
> + bits [23:0] of MPIDR_EL1.
> +
> + All other bits in the reg cell must be set to 0.
> +
> + - compatible:
> + Usage: required
> + Value type: <string>
> + Definition: should be one of:
> + "arm,arm710t"
> + "arm,arm720t"
> + "arm,arm740t"
> + "arm,arm7ej-s"
> + "arm,arm7tdmi"
> + "arm,arm7tdmi-s"
> + "arm,arm9es"
> + "arm,arm9ej-s"
> + "arm,arm920t"
> + "arm,arm922t"
> + "arm,arm925"
> + "arm,arm926e-s"
> + "arm,arm926ej-s"
> + "arm,arm940t"
> + "arm,arm946e-s"
> + "arm,arm966e-s"
> + "arm,arm968e-s"
> + "arm,arm9tdmi"
> + "arm,arm1020e"
> + "arm,arm1020t"
> + "arm,arm1022e"
> + "arm,arm1026ej-s"
> + "arm,arm1136j-s"
> + "arm,arm1136jf-s"
> + "arm,arm1156t2-s"
> + "arm,arm1156t2f-s"
> + "arm,arm1176jzf"
> + "arm,arm1176jz-s"
> + "arm,arm1176jzf-s"
> + "arm,arm11mpcore"
> + "arm,cortex-a5"
> + "arm,cortex-a7"
> + "arm,cortex-a8"
> + "arm,cortex-a9"
> + "arm,cortex-a15"
> + "arm,cortex-a53"
> + "arm,cortex-a57"
> + "arm,cortex-m0"
> + "arm,cortex-m0+"
> + "arm,cortex-m1"
> + "arm,cortex-m3"
> + "arm,cortex-m4"
> + "arm,cortex-r4"
> + "arm,cortex-r5"
> + "arm,cortex-r7"
> + "faraday,fa526"
> + "intel,sa110"
> + "intel,sa1100"
> + "marvell,feroceon"
> + "marvell,mohawk"
> + "marvell,pj4"
> + "marvell,sheeva-v7"
> + "marvell,xsc3"
> + "marvell,xscale"
> + "qcom,krait"
> + "qcom,scorpion"
> + - enable-method
> + Value type: <stringlist>
> + Usage and definition depend on ARM architecture version and
> + configuration:
> + # On ARM v8 64-bit systems running the OS in AArch64,
> + this property is required and must be one of:
> + "spin-table"
> + "psci"
> + # On ARM 32-bit systems or ARM v8 systems running
> + the OS in AArch32 this property is prohibited.
> +
> + - cpu-release-addr
> + Usage: required for systems that have an "enable-method"
> + property value of "spin-table".
> + Value type: <prop-encoded-array>
> + Definition:
> + # On ARM v8 64-bit systems must be a two cell
> + property identifying a 64-bit zero-initialised
> + memory location.
> +
> +Example 1 (dual-cluster big.LITTLE system 32-bit):
>
> cpus {
> #size-cells = <0>;
> #address-cells = <1>;
>
> - CPU0: cpu@0 {
> + cpu@0 {
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <0x0>;
> };
>
> - CPU1: cpu@1 {
> + cpu@1 {
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <0x1>;
> };
>
> - CPU2: cpu@100 {
> + cpu@100 {
> device_type = "cpu";
> compatible = "arm,cortex-a7";
> reg = <0x100>;
> };
>
> - CPU3: cpu@101 {
> + cpu@101 {
> device_type = "cpu";
> compatible = "arm,cortex-a7";
> reg = <0x101>;
> };
> };
> +
> +Example 2 (Cortex-A8 uniprocessor 32-bit system):
> +
> + cpus {
> + #size-cells = <0>;
> + #address-cells = <1>;
> +
> + cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a8";
> + reg = <0x0>;
> + };
> + };
> +
> +Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
> +
> + cpus {
> + #size-cells = <0>;
> + #address-cells = <0>;
> +
> + cpu {
> + device_type = "cpu";
> + compatible = "arm,arm926ej-s";
> + };
> + };
> +
> +Example 4 (ARM Cortex-A57 64-bit system running OS in AArch64):
> +
> +cpus {
> + #size-cells = <0>;
> + #address-cells = <2>;
> +
> + cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x0>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0x20000000>;
> + };
> +
> + cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x1>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0x20000000>;
> + };
> +
> + cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x100>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0x20000000>;
> + };
> +
> + cpu@101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x101>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0x20000000>;
> + };
> +
> + cpu@10000 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x10000>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0x20000000>;
> + };
> +
> + cpu@10001 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x10001>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0x20000000>;
> + };
> +
> + cpu@10100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x10100>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0x20000000>;
> + };
> +
> + cpu@10101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x10101>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0x20000000>;
> + };
> +
> + cpu@100000000 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x1 0x0>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0x20000000>;
> + };
> +
> + cpu@100000001 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x1 0x1>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0x20000000>;
> + };
> +
> + cpu@100000100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x1 0x100>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0x20000000>;
> + };
> +
> + cpu@100000101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x1 0x101>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0x20000000>;
> + };
> +
> + cpu@100010000 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x1 0x10000>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0x20000000>;
> + };
> +
> + cpu@100010001 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x1 0x10001>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0x20000000>;
> + };
> +
> + cpu@100010100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x1 0x10100>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0x20000000>;
> + };
> +
> + cpu@100010101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x1 0x10101>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0x20000000>;
> + };
> +};
> +
> +Example 5 (ARM Cortex-A57 64-bit system running OS in AArch32):
> +
> +cpus {
> + #size-cells = <0>;
> + #address-cells = <2>;
> +
> + cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x0>;
> + };
> +
> + cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x1>;
> + };
> +
> + cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x100>;
> + };
> +
> + cpu@101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x101>;
> + };
> +};
> --
> 1.8.2.2
>
>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [RFC PATCH v4 03/18] Documentation: devicetree: arm: cpus/cpu nodes bindings updates
@ 2013-05-17 16:07 ` Nicolas Pitre
0 siblings, 0 replies; 64+ messages in thread
From: Nicolas Pitre @ 2013-05-17 16:07 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, 17 May 2013, Lorenzo Pieralisi wrote:
> In order to extend the current cpu nodes bindings to newer CPUs
> inclusive of AArch64 and to update support for older ARM CPUs this
> patch updates device tree documentation for the cpu nodes bindings.
>
> Main changes:
> - adds 64-bit bindings
> - define usage of #address-cells
> - define 32/64 dts compatibility settings
> - defines behaviour on pre and post v7 uniprocessor systems
> - adds ARM 11MPcore specific reg property definition
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
> ---
> Documentation/devicetree/bindings/arm/cpus.txt | 459 ++++++++++++++++++++++---
> 1 file changed, 412 insertions(+), 47 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> index f32494d..3fc0c11 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.txt
> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> @@ -1,77 +1,442 @@
> -* ARM CPUs binding description
> +=================
> +ARM CPUs bindings
> +=================
>
> The device tree allows to describe the layout of CPUs in a system through
> the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
> defining properties for every cpu.
>
> -Bindings for CPU nodes follow the ePAPR standard, available from:
> -
> -http://devicetree.org
> -
> -For the ARM architecture every CPU node must contain the following properties:
> -
> -- device_type: must be "cpu"
> -- reg: property matching the CPU MPIDR[23:0] register bits
> - reg[31:24] bits must be set to 0
> -- compatible: should be one of:
> - "arm,arm1020"
> - "arm,arm1020e"
> - "arm,arm1022"
> - "arm,arm1026"
> - "arm,arm720"
> - "arm,arm740"
> - "arm,arm7tdmi"
> - "arm,arm920"
> - "arm,arm922"
> - "arm,arm925"
> - "arm,arm926"
> - "arm,arm940"
> - "arm,arm946"
> - "arm,arm9tdmi"
> - "arm,cortex-a5"
> - "arm,cortex-a7"
> - "arm,cortex-a8"
> - "arm,cortex-a9"
> - "arm,cortex-a15"
> - "arm,arm1136"
> - "arm,arm1156"
> - "arm,arm1176"
> - "arm,arm11mpcore"
> - "faraday,fa526"
> - "intel,sa110"
> - "intel,sa1100"
> - "marvell,feroceon"
> - "marvell,mohawk"
> - "marvell,xsc3"
> - "marvell,xscale"
> -
> -Example:
> +Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
> +
> +https://www.power.org/documentation/epapr-version-1-1/
> +
> +with updates for 32-bit and 64-bit ARM systems provided in this document.
> +
> +================================
> +Convention used in this document
> +================================
> +
> +This document follows the conventions described in the ePAPR v1.1, with
> +the addition:
> +
> +- square brackets define bitfields, eg reg[7:0] value of the bitfield in
> + the reg property contained in bits 7 down to 0
> +
> +=====================================
> +cpus and cpu node bindings definition
> +=====================================
> +
> +The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
> +nodes to be present and contain the properties described below.
> +
> +- cpus node
> +
> + Description: Container of cpu nodes
> +
> + The node name must be "cpus".
> +
> + A cpus node must define the following properties:
> +
> + - #address-cells
> + Usage: required
> + Value type: <u32>
> +
> + Definition depends on ARM architecture version and
> + configuration:
> +
> + # On uniprocessor ARM architectures previous to v7
> + value must be 0.
> + # On 32-bit ARM 11 MPcore, ARM v7 or later systems
> + value must be 1.
> + # On ARM v8 64-bit systems value must be set to 1
> + or 2. Refer to the cpu node's reg property
> + description for allowed configurations.
> +
> + - #size-cells
> + Usage: required
> + Value type: <u32>
> + Definition: must be set to 0
> +
> +- cpu node
> +
> + Description: Describes a CPU in an ARM based system
> +
> + PROPERTIES
> +
> + - device_type
> + Usage: required
> + Value type: <string>
> + Definition: must be "cpu"
> + - reg
> + Usage and definition depend on ARM architecture version and
> + configuration:
> +
> + # On uniprocessor ARM architectures previous to v7
> + this property is optional since they do not define
> + any register that provides a CPU identifier.
> + Any value set in the reg property for these CPUs
> + should be ignored.
> +
> + # On ARM 11 MPcore based systems this property is
> + required and matches the CPUID[11:0] register bits.
> +
> + Bits [11:0] in the reg cell must be set to
> + bits [11:0] in CPU ID register.
> +
> + All other bits in the reg cell must be set to 0.
> +
> + # On 32-bit ARM v7 or later systems this property is
> + required and matches the CPU MPIDR[23:0] register
> + bits.
> +
> + Bits [23:0] in the reg cell must be set to
> + bits [23:0] in MPIDR.
> +
> + All other bits in the reg cell must be set to 0.
> +
> + # On ARM v8 64-bit systems, where the reg property
> + size can be 1 or 2 cells (as defined by cpus node's
> + #address-cells property), this property is
> + required and matches:
> +
> + - On systems running the OS in AArch32:
> +
> + * If the cpus node's #address-cells value is 2:
> +
> + The first reg cell must be set to 0.
> +
> + The second reg cell bits [23:0] must be set to
> + bits [23:0] of MPIDR_EL1.
> +
> + All other bits in the reg cells must be set to 0.
> +
> + * If the cpus node's #address-cells value is 1:
> +
> + Bits [23:0] in the reg cell must be set to
> + bits [23:0] in MPIDR_EL1.
> +
> + All other bits in the reg cell must be 0.
> +
> + - On systems running the OS in AArch64:
> +
> + * If the cpus node's #address-cells value is 2:
> +
> + The first reg cell bits [7:0] must be set to
> + bits [39:32] of MPIDR_EL1.
> +
> + The second reg cell bits [23:0] must be set to
> + bits [23:0] of MPIDR_EL1.
> +
> + All other bits in the reg cells must be set to 0.
> +
> + * If the cpus node's #address-cells value is 1:
> +
> + MPIDR_EL1[63:32] is 0 on all processors in the
> + system.
> +
> + The reg cell bits [23:0] must be set to
> + bits [23:0] of MPIDR_EL1.
> +
> + All other bits in the reg cell must be set to 0.
> +
> + - compatible:
> + Usage: required
> + Value type: <string>
> + Definition: should be one of:
> + "arm,arm710t"
> + "arm,arm720t"
> + "arm,arm740t"
> + "arm,arm7ej-s"
> + "arm,arm7tdmi"
> + "arm,arm7tdmi-s"
> + "arm,arm9es"
> + "arm,arm9ej-s"
> + "arm,arm920t"
> + "arm,arm922t"
> + "arm,arm925"
> + "arm,arm926e-s"
> + "arm,arm926ej-s"
> + "arm,arm940t"
> + "arm,arm946e-s"
> + "arm,arm966e-s"
> + "arm,arm968e-s"
> + "arm,arm9tdmi"
> + "arm,arm1020e"
> + "arm,arm1020t"
> + "arm,arm1022e"
> + "arm,arm1026ej-s"
> + "arm,arm1136j-s"
> + "arm,arm1136jf-s"
> + "arm,arm1156t2-s"
> + "arm,arm1156t2f-s"
> + "arm,arm1176jzf"
> + "arm,arm1176jz-s"
> + "arm,arm1176jzf-s"
> + "arm,arm11mpcore"
> + "arm,cortex-a5"
> + "arm,cortex-a7"
> + "arm,cortex-a8"
> + "arm,cortex-a9"
> + "arm,cortex-a15"
> + "arm,cortex-a53"
> + "arm,cortex-a57"
> + "arm,cortex-m0"
> + "arm,cortex-m0+"
> + "arm,cortex-m1"
> + "arm,cortex-m3"
> + "arm,cortex-m4"
> + "arm,cortex-r4"
> + "arm,cortex-r5"
> + "arm,cortex-r7"
> + "faraday,fa526"
> + "intel,sa110"
> + "intel,sa1100"
> + "marvell,feroceon"
> + "marvell,mohawk"
> + "marvell,pj4"
> + "marvell,sheeva-v7"
> + "marvell,xsc3"
> + "marvell,xscale"
> + "qcom,krait"
> + "qcom,scorpion"
> + - enable-method
> + Value type: <stringlist>
> + Usage and definition depend on ARM architecture version and
> + configuration:
> + # On ARM v8 64-bit systems running the OS in AArch64,
> + this property is required and must be one of:
> + "spin-table"
> + "psci"
> + # On ARM 32-bit systems or ARM v8 systems running
> + the OS in AArch32 this property is prohibited.
> +
> + - cpu-release-addr
> + Usage: required for systems that have an "enable-method"
> + property value of "spin-table".
> + Value type: <prop-encoded-array>
> + Definition:
> + # On ARM v8 64-bit systems must be a two cell
> + property identifying a 64-bit zero-initialised
> + memory location.
> +
> +Example 1 (dual-cluster big.LITTLE system 32-bit):
>
> cpus {
> #size-cells = <0>;
> #address-cells = <1>;
>
> - CPU0: cpu at 0 {
> + cpu at 0 {
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <0x0>;
> };
>
> - CPU1: cpu at 1 {
> + cpu at 1 {
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <0x1>;
> };
>
> - CPU2: cpu at 100 {
> + cpu at 100 {
> device_type = "cpu";
> compatible = "arm,cortex-a7";
> reg = <0x100>;
> };
>
> - CPU3: cpu at 101 {
> + cpu at 101 {
> device_type = "cpu";
> compatible = "arm,cortex-a7";
> reg = <0x101>;
> };
> };
> +
> +Example 2 (Cortex-A8 uniprocessor 32-bit system):
> +
> + cpus {
> + #size-cells = <0>;
> + #address-cells = <1>;
> +
> + cpu at 0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a8";
> + reg = <0x0>;
> + };
> + };
> +
> +Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
> +
> + cpus {
> + #size-cells = <0>;
> + #address-cells = <0>;
> +
> + cpu {
> + device_type = "cpu";
> + compatible = "arm,arm926ej-s";
> + };
> + };
> +
> +Example 4 (ARM Cortex-A57 64-bit system running OS in AArch64):
> +
> +cpus {
> + #size-cells = <0>;
> + #address-cells = <2>;
> +
> + cpu at 0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x0>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0x20000000>;
> + };
> +
> + cpu at 1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x1>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0x20000000>;
> + };
> +
> + cpu at 100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x100>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0x20000000>;
> + };
> +
> + cpu at 101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x101>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0x20000000>;
> + };
> +
> + cpu at 10000 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x10000>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0x20000000>;
> + };
> +
> + cpu at 10001 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x10001>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0x20000000>;
> + };
> +
> + cpu at 10100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x10100>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0x20000000>;
> + };
> +
> + cpu at 10101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x10101>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0x20000000>;
> + };
> +
> + cpu at 100000000 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x1 0x0>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0x20000000>;
> + };
> +
> + cpu at 100000001 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x1 0x1>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0x20000000>;
> + };
> +
> + cpu at 100000100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x1 0x100>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0x20000000>;
> + };
> +
> + cpu at 100000101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x1 0x101>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0x20000000>;
> + };
> +
> + cpu at 100010000 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x1 0x10000>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0x20000000>;
> + };
> +
> + cpu at 100010001 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x1 0x10001>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0x20000000>;
> + };
> +
> + cpu at 100010100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x1 0x10100>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0x20000000>;
> + };
> +
> + cpu at 100010101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x1 0x10101>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0x20000000>;
> + };
> +};
> +
> +Example 5 (ARM Cortex-A57 64-bit system running OS in AArch32):
> +
> +cpus {
> + #size-cells = <0>;
> + #address-cells = <2>;
> +
> + cpu at 0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x0>;
> + };
> +
> + cpu at 1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x1>;
> + };
> +
> + cpu at 100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x100>;
> + };
> +
> + cpu at 101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x101>;
> + };
> +};
> --
> 1.8.2.2
>
>
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [RFC PATCH v4 18/18] ARM: DT: kernel: DT cpus/cpu node bindings update
2013-05-17 15:21 ` Lorenzo Pieralisi
@ 2013-05-17 16:22 ` Nicolas Pitre
-1 siblings, 0 replies; 64+ messages in thread
From: Nicolas Pitre @ 2013-05-17 16:22 UTC (permalink / raw)
To: Lorenzo Pieralisi
Cc: Jon Medhurst, Andrew Lunn, Will Deacon, Viresh Kumar,
Lennert Buytenhek, Kukjin Kim, Russell King, Magnus Damm,
Catalin Marinas, Grant Likely, David Brown, Sekhar Nori,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Rob Herring,
Simon Horman, Barry Song,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Vinayak Kale,
Amit Kucheria
On Fri, 17 May 2013, Lorenzo Pieralisi wrote:
> DT cpu map parsing code must be made compliant with the latest cpus/cpu
> nodes bindings updates, hence this patch updates the arm_dt_init_cpu_maps()
> function with checks and additional parsing rules.
>
> Uniprocessor systems predating v7 do not parse the cpus node at all
> since the reg property is meaningless on those systems.
>
> Device trees for 64-bit systems can be taken as device tree input also
> for 64-bit CPUs running in 32-bit mode. The code checks that the reg entries
> are zeroed as required in the respective fields and detects automatically
> the cpus node #address-cells value so that device tree written for
> 64-bit ARM platforms (that can have cpus node #address-cells == 2) can still
> be taken as input. The correct device tree entries are to be set up by the
> boot loader, kernel code just checks that device tree entries in the cpus
> node are as expected for a 32-bit CPU (reg[63:24] == 0).
>
> cpu node entries with invalid reg property or containing duplicates are
> ignored and the device tree parsing is not stopped anymore when such
> entries are encountered, the device tree cpu node entry is just skipped.
>
> A device tree with cpu nodes missing the boot CPU MPIDR is considered
> an error and the kernel flags this up as such to trigger firmware updates.
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
Acked-by: Nicolas Pitre <nico-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
> arch/arm/kernel/devtree.c | 146 ++++++++++++++++++++++++++++------------------
> 1 file changed, 88 insertions(+), 58 deletions(-)
>
> diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
> index 0905502..80d6cf24 100644
> --- a/arch/arm/kernel/devtree.c
> +++ b/arch/arm/kernel/devtree.c
> @@ -23,6 +23,7 @@
> #include <asm/setup.h>
> #include <asm/page.h>
> #include <asm/smp_plat.h>
> +#include <asm/system_info.h>
> #include <asm/mach/arch.h>
> #include <asm/mach-types.h>
>
> @@ -72,100 +73,129 @@ void __init arm_dt_memblock_reserve(void)
> */
> void __init arm_dt_init_cpu_maps(void)
> {
> - /*
> - * Temp logical map is initialized with UINT_MAX values that are
> - * considered invalid logical map entries since the logical map must
> - * contain a list of MPIDR[23:0] values where MPIDR[31:24] must
> - * read as 0.
> - */
> struct device_node *cpu, *cpus;
> - u32 i, j, cpuidx = 1;
> + u32 i, ac, cpuidx = 1;
> + int len;
> u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
>
> - u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
> bool bootcpu_valid = false;
> cpus = of_find_node_by_path("/cpus");
>
> - if (!cpus)
> + if (!cpus || ((cpu_architecture() < CPU_ARCH_ARMv7) && !is_smp()))
> return;
>
> + if (of_property_read_u32(cpus, "#address-cells", &ac)) {
> + pr_warn("%s invalid #address-cells\n", cpus->full_name);
> + ac = of_n_addr_cells(cpus);
> + }
> + /*
> + * The boot CPU knows its MPIDR and initialize it
> + * to allow DT boot CPU detection.
> + */
> + cpu_logical_map(0) = mpidr;
> +
> for_each_child_of_node(cpus, cpu) {
> - u32 hwid;
> + u64 hwid64;
> + u32 hwid32;
> + const __be32 *prop;
>
> if (of_node_cmp(cpu->type, "cpu"))
> continue;
>
> pr_debug(" * %s...\n", cpu->full_name);
> /*
> - * A device tree containing CPU nodes with missing "reg"
> - * properties is considered invalid to build the
> - * cpu_logical_map.
> + * A CPU node with missing or wrong "reg" property is
> + * considered invalid to build a cpu_logical_map entry.
> */
> - if (of_property_read_u32(cpu, "reg", &hwid)) {
> - pr_debug(" * %s missing reg property\n",
> - cpu->full_name);
> - return;
> + prop = of_get_property(cpu, "reg", &len);
> + if (!prop || len < (ac * sizeof(*prop))) {
> + pr_warn(" * %s node missing/wrong reg property, skipped\n",
> + cpu->full_name);
> + goto next;
> }
>
> /*
> - * 8 MSBs must be set to 0 in the DT since the reg property
> - * defines the MPIDR[23:0].
> + * Always read reg as u64 value.
> + * For dts with #address-cells == 1 hwid64[63:32]
> + * will be set to 0 by of_read_number.
> + * Toss away the top 32 bits and store value in hwid32.
> */
> - if (hwid & ~MPIDR_HWID_BITMASK)
> - return;
> -
> + hwid32 = hwid64 = of_read_number(prop, ac);
> + /*
> + * hwid64[63:24] must be always be 0 since the reg
> + * property defines the MPIDR[23:0] bits regardless
> + * of the cpus node #address-cells value.
> + */
> + if (hwid64 & ~MPIDR_HWID_BITMASK) {
> + pr_warn(" * %s node reg[63:24] must be 0 on 32-bit dts, got %#016llx, skipped\n",
> + cpu->full_name, hwid64);
> + goto next;
> + }
> /*
> * Duplicate MPIDRs are a recipe for disaster.
> * Scan all initialized entries and check for
> - * duplicates. If any is found just bail out.
> - * temp values were initialized to UINT_MAX
> - * to avoid matching valid MPIDR[23:0] values.
> + * duplicates. If any is found just ignore the CPU.
> + * Boot CPU at logical index 0 is not checked to
> + * allow self contained boot CPU detection logic.
> */
> - for (j = 0; j < cpuidx; j++)
> - if (WARN(tmp_map[j] == hwid, "Duplicate /cpu reg "
> - "properties in the DT\n"))
> - return;
> + for (i = 1; i < cpuidx; i++)
> + if (cpu_logical_map(i) == hwid32) {
> + pr_warn(" * %s node duplicate cpu reg property, skipped\n",
> + cpu->full_name);
> + goto next;
> + }
>
> /*
> - * Build a stashed array of MPIDR values. Numbering scheme
> - * requires that if detected the boot CPU must be assigned
> - * logical id 0. Other CPUs get sequential indexes starting
> - * from 1. If a CPU node with a reg property matching the
> - * boot CPU MPIDR is detected, this is recorded so that the
> - * logical map built from DT is validated and can be used
> - * to override the map created in smp_setup_processor_id().
> + * If a CPU node with a reg property matching the
> + * cpu_logical_map(0) is detected, this is recorded so
> + * that the bootcpu_valid condition can be checked when
> + * DT scanning is completed. Duplicate boot cpu entries
> + * are flagged up if detected.
> */
> - if (hwid == mpidr) {
> - i = 0;
> - bootcpu_valid = true;
> - } else {
> - i = cpuidx++;
> + if (hwid32 == cpu_logical_map(0)) {
> + if (bootcpu_valid) {
> + pr_warn(" * %s node duplicate boot cpu reg property, skipped\n",
> + cpu->full_name);
> + } else {
> + bootcpu_valid = true;
> + }
> + goto next;
> }
> + /*
> + * Build cpu_logical_map array. Numbering scheme
> + * requires that boot CPU is assigned logical id 0.
> + * Other CPUs get sequential indexes starting from 1.
> + */
> + i = cpuidx++;
>
> - if (WARN(cpuidx > nr_cpu_ids, "DT /cpu %u nodes greater than "
> - "max cores %u, capping them\n",
> - cpuidx, nr_cpu_ids)) {
> + if (cpuidx > nr_cpu_ids) {
> + pr_warn_once("DT cpu %u nodes greater than max cores %u, capping them\n",
> + cpuidx, nr_cpu_ids);
> cpuidx = nr_cpu_ids;
> - break;
> + goto next;
> }
>
> - tmp_map[i] = hwid;
> + cpu_logical_map(i) = hwid32;
> + set_cpu_possible(i, true);
> + pr_debug("cpu_logical_map(%u) 0x%x\n", i, cpu_logical_map(i));
> +next: ;
> }
> -
> - if (WARN(!bootcpu_valid, "DT missing boot CPU MPIDR[23:0], "
> - "fall back to default cpu_logical_map\n"))
> - return;
> + /*
> + * A DT missing the boot CPU MPIDR is a really bad omen
> + * Flag it up as such.
> + */
> + if (!bootcpu_valid)
> + pr_warn("DT missing boot cpu node\n");
>
> /*
> - * Since the boot CPU node contains proper data, and all nodes have
> - * a reg property, the DT CPU list can be considered valid and the
> - * logical map created in smp_setup_processor_id() can be overridden
> + * Since the DT might contain fewer entries than NR_CPUS,
> + * cpu_logical_map entries initialized in smp_setup_processor_id()
> + * but not found in the DT must be overriden with MPIDR_INVALID
> + * values to make sure the cpu_logical_map does not contain stale
> + * MPIDR values.
> */
> - for (i = 0; i < cpuidx; i++) {
> - set_cpu_possible(i, true);
> - cpu_logical_map(i) = tmp_map[i];
> - pr_debug("cpu logical map 0x%x\n", cpu_logical_map(i));
> - }
> + for (i = cpuidx; i < nr_cpu_ids; i++)
> + cpu_logical_map(i) = MPIDR_INVALID;
> }
>
> /**
> --
> 1.8.2.2
>
>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [RFC PATCH v4 18/18] ARM: DT: kernel: DT cpus/cpu node bindings update
@ 2013-05-17 16:22 ` Nicolas Pitre
0 siblings, 0 replies; 64+ messages in thread
From: Nicolas Pitre @ 2013-05-17 16:22 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, 17 May 2013, Lorenzo Pieralisi wrote:
> DT cpu map parsing code must be made compliant with the latest cpus/cpu
> nodes bindings updates, hence this patch updates the arm_dt_init_cpu_maps()
> function with checks and additional parsing rules.
>
> Uniprocessor systems predating v7 do not parse the cpus node at all
> since the reg property is meaningless on those systems.
>
> Device trees for 64-bit systems can be taken as device tree input also
> for 64-bit CPUs running in 32-bit mode. The code checks that the reg entries
> are zeroed as required in the respective fields and detects automatically
> the cpus node #address-cells value so that device tree written for
> 64-bit ARM platforms (that can have cpus node #address-cells == 2) can still
> be taken as input. The correct device tree entries are to be set up by the
> boot loader, kernel code just checks that device tree entries in the cpus
> node are as expected for a 32-bit CPU (reg[63:24] == 0).
>
> cpu node entries with invalid reg property or containing duplicates are
> ignored and the device tree parsing is not stopped anymore when such
> entries are encountered, the device tree cpu node entry is just skipped.
>
> A device tree with cpu nodes missing the boot CPU MPIDR is considered
> an error and the kernel flags this up as such to trigger firmware updates.
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
> ---
> arch/arm/kernel/devtree.c | 146 ++++++++++++++++++++++++++++------------------
> 1 file changed, 88 insertions(+), 58 deletions(-)
>
> diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
> index 0905502..80d6cf24 100644
> --- a/arch/arm/kernel/devtree.c
> +++ b/arch/arm/kernel/devtree.c
> @@ -23,6 +23,7 @@
> #include <asm/setup.h>
> #include <asm/page.h>
> #include <asm/smp_plat.h>
> +#include <asm/system_info.h>
> #include <asm/mach/arch.h>
> #include <asm/mach-types.h>
>
> @@ -72,100 +73,129 @@ void __init arm_dt_memblock_reserve(void)
> */
> void __init arm_dt_init_cpu_maps(void)
> {
> - /*
> - * Temp logical map is initialized with UINT_MAX values that are
> - * considered invalid logical map entries since the logical map must
> - * contain a list of MPIDR[23:0] values where MPIDR[31:24] must
> - * read as 0.
> - */
> struct device_node *cpu, *cpus;
> - u32 i, j, cpuidx = 1;
> + u32 i, ac, cpuidx = 1;
> + int len;
> u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
>
> - u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
> bool bootcpu_valid = false;
> cpus = of_find_node_by_path("/cpus");
>
> - if (!cpus)
> + if (!cpus || ((cpu_architecture() < CPU_ARCH_ARMv7) && !is_smp()))
> return;
>
> + if (of_property_read_u32(cpus, "#address-cells", &ac)) {
> + pr_warn("%s invalid #address-cells\n", cpus->full_name);
> + ac = of_n_addr_cells(cpus);
> + }
> + /*
> + * The boot CPU knows its MPIDR and initialize it
> + * to allow DT boot CPU detection.
> + */
> + cpu_logical_map(0) = mpidr;
> +
> for_each_child_of_node(cpus, cpu) {
> - u32 hwid;
> + u64 hwid64;
> + u32 hwid32;
> + const __be32 *prop;
>
> if (of_node_cmp(cpu->type, "cpu"))
> continue;
>
> pr_debug(" * %s...\n", cpu->full_name);
> /*
> - * A device tree containing CPU nodes with missing "reg"
> - * properties is considered invalid to build the
> - * cpu_logical_map.
> + * A CPU node with missing or wrong "reg" property is
> + * considered invalid to build a cpu_logical_map entry.
> */
> - if (of_property_read_u32(cpu, "reg", &hwid)) {
> - pr_debug(" * %s missing reg property\n",
> - cpu->full_name);
> - return;
> + prop = of_get_property(cpu, "reg", &len);
> + if (!prop || len < (ac * sizeof(*prop))) {
> + pr_warn(" * %s node missing/wrong reg property, skipped\n",
> + cpu->full_name);
> + goto next;
> }
>
> /*
> - * 8 MSBs must be set to 0 in the DT since the reg property
> - * defines the MPIDR[23:0].
> + * Always read reg as u64 value.
> + * For dts with #address-cells == 1 hwid64[63:32]
> + * will be set to 0 by of_read_number.
> + * Toss away the top 32 bits and store value in hwid32.
> */
> - if (hwid & ~MPIDR_HWID_BITMASK)
> - return;
> -
> + hwid32 = hwid64 = of_read_number(prop, ac);
> + /*
> + * hwid64[63:24] must be always be 0 since the reg
> + * property defines the MPIDR[23:0] bits regardless
> + * of the cpus node #address-cells value.
> + */
> + if (hwid64 & ~MPIDR_HWID_BITMASK) {
> + pr_warn(" * %s node reg[63:24] must be 0 on 32-bit dts, got %#016llx, skipped\n",
> + cpu->full_name, hwid64);
> + goto next;
> + }
> /*
> * Duplicate MPIDRs are a recipe for disaster.
> * Scan all initialized entries and check for
> - * duplicates. If any is found just bail out.
> - * temp values were initialized to UINT_MAX
> - * to avoid matching valid MPIDR[23:0] values.
> + * duplicates. If any is found just ignore the CPU.
> + * Boot CPU at logical index 0 is not checked to
> + * allow self contained boot CPU detection logic.
> */
> - for (j = 0; j < cpuidx; j++)
> - if (WARN(tmp_map[j] == hwid, "Duplicate /cpu reg "
> - "properties in the DT\n"))
> - return;
> + for (i = 1; i < cpuidx; i++)
> + if (cpu_logical_map(i) == hwid32) {
> + pr_warn(" * %s node duplicate cpu reg property, skipped\n",
> + cpu->full_name);
> + goto next;
> + }
>
> /*
> - * Build a stashed array of MPIDR values. Numbering scheme
> - * requires that if detected the boot CPU must be assigned
> - * logical id 0. Other CPUs get sequential indexes starting
> - * from 1. If a CPU node with a reg property matching the
> - * boot CPU MPIDR is detected, this is recorded so that the
> - * logical map built from DT is validated and can be used
> - * to override the map created in smp_setup_processor_id().
> + * If a CPU node with a reg property matching the
> + * cpu_logical_map(0) is detected, this is recorded so
> + * that the bootcpu_valid condition can be checked when
> + * DT scanning is completed. Duplicate boot cpu entries
> + * are flagged up if detected.
> */
> - if (hwid == mpidr) {
> - i = 0;
> - bootcpu_valid = true;
> - } else {
> - i = cpuidx++;
> + if (hwid32 == cpu_logical_map(0)) {
> + if (bootcpu_valid) {
> + pr_warn(" * %s node duplicate boot cpu reg property, skipped\n",
> + cpu->full_name);
> + } else {
> + bootcpu_valid = true;
> + }
> + goto next;
> }
> + /*
> + * Build cpu_logical_map array. Numbering scheme
> + * requires that boot CPU is assigned logical id 0.
> + * Other CPUs get sequential indexes starting from 1.
> + */
> + i = cpuidx++;
>
> - if (WARN(cpuidx > nr_cpu_ids, "DT /cpu %u nodes greater than "
> - "max cores %u, capping them\n",
> - cpuidx, nr_cpu_ids)) {
> + if (cpuidx > nr_cpu_ids) {
> + pr_warn_once("DT cpu %u nodes greater than max cores %u, capping them\n",
> + cpuidx, nr_cpu_ids);
> cpuidx = nr_cpu_ids;
> - break;
> + goto next;
> }
>
> - tmp_map[i] = hwid;
> + cpu_logical_map(i) = hwid32;
> + set_cpu_possible(i, true);
> + pr_debug("cpu_logical_map(%u) 0x%x\n", i, cpu_logical_map(i));
> +next: ;
> }
> -
> - if (WARN(!bootcpu_valid, "DT missing boot CPU MPIDR[23:0], "
> - "fall back to default cpu_logical_map\n"))
> - return;
> + /*
> + * A DT missing the boot CPU MPIDR is a really bad omen
> + * Flag it up as such.
> + */
> + if (!bootcpu_valid)
> + pr_warn("DT missing boot cpu node\n");
>
> /*
> - * Since the boot CPU node contains proper data, and all nodes have
> - * a reg property, the DT CPU list can be considered valid and the
> - * logical map created in smp_setup_processor_id() can be overridden
> + * Since the DT might contain fewer entries than NR_CPUS,
> + * cpu_logical_map entries initialized in smp_setup_processor_id()
> + * but not found in the DT must be overriden with MPIDR_INVALID
> + * values to make sure the cpu_logical_map does not contain stale
> + * MPIDR values.
> */
> - for (i = 0; i < cpuidx; i++) {
> - set_cpu_possible(i, true);
> - cpu_logical_map(i) = tmp_map[i];
> - pr_debug("cpu logical map 0x%x\n", cpu_logical_map(i));
> - }
> + for (i = cpuidx; i < nr_cpu_ids; i++)
> + cpu_logical_map(i) = MPIDR_INVALID;
> }
>
> /**
> --
> 1.8.2.2
>
>
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [RFC PATCH v4 01/18] ARM: kernel: fix arm_dt_init_cpu_maps() to skip non-cpu nodes
2013-05-17 15:20 ` Lorenzo Pieralisi
@ 2013-05-17 16:31 ` Rob Herring
-1 siblings, 0 replies; 64+ messages in thread
From: Rob Herring @ 2013-05-17 16:31 UTC (permalink / raw)
To: Lorenzo Pieralisi
Cc: Nicolas Pitre, Jon Medhurst, Kukjin Kim, Russell King,
Andrew Lunn, Viresh Kumar,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Barry Song,
Will Deacon, Sekhar Nori, Simon Horman, Rob Herring,
Amit Kucheria, Catalin Marinas, Grant Likely, David Brown,
Vinayak Kale, Lennert Buytenhek,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Magnus Damm
On Fri, May 17, 2013 at 10:20 AM, Lorenzo Pieralisi
<lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org> wrote:
> The introduction of the cpu-map topology node in the cpus node implies
> that cpus node might have children that are not cpu nodes. The DT
> parsing code needs updating otherwise it would check for cpu nodes
> properties in nodes that are not required to contain them, resulting
> in warnings that have no bearing on bindings defined in the dts source file.
Great, so a new DT with cpu-map entries may not work with old kernels.
Please check the behavior. This should go to stable kernels.
Rob
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
> ---
> arch/arm/kernel/devtree.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
> index 5af04f6..904cad5 100644
> --- a/arch/arm/kernel/devtree.c
> +++ b/arch/arm/kernel/devtree.c
> @@ -92,6 +92,9 @@ void __init arm_dt_init_cpu_maps(void)
> for_each_child_of_node(cpus, cpu) {
> u32 hwid;
>
> + if (of_node_cmp(cpu->type, "cpu"))
> + continue;
> +
> pr_debug(" * %s...\n", cpu->full_name);
> /*
> * A device tree containing CPU nodes with missing "reg"
> --
> 1.8.2.2
>
>
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss
^ permalink raw reply [flat|nested] 64+ messages in thread
* [RFC PATCH v4 01/18] ARM: kernel: fix arm_dt_init_cpu_maps() to skip non-cpu nodes
@ 2013-05-17 16:31 ` Rob Herring
0 siblings, 0 replies; 64+ messages in thread
From: Rob Herring @ 2013-05-17 16:31 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, May 17, 2013 at 10:20 AM, Lorenzo Pieralisi
<lorenzo.pieralisi@arm.com> wrote:
> The introduction of the cpu-map topology node in the cpus node implies
> that cpus node might have children that are not cpu nodes. The DT
> parsing code needs updating otherwise it would check for cpu nodes
> properties in nodes that are not required to contain them, resulting
> in warnings that have no bearing on bindings defined in the dts source file.
Great, so a new DT with cpu-map entries may not work with old kernels.
Please check the behavior. This should go to stable kernels.
Rob
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> ---
> arch/arm/kernel/devtree.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
> index 5af04f6..904cad5 100644
> --- a/arch/arm/kernel/devtree.c
> +++ b/arch/arm/kernel/devtree.c
> @@ -92,6 +92,9 @@ void __init arm_dt_init_cpu_maps(void)
> for_each_child_of_node(cpus, cpu) {
> u32 hwid;
>
> + if (of_node_cmp(cpu->type, "cpu"))
> + continue;
> +
> pr_debug(" * %s...\n", cpu->full_name);
> /*
> * A device tree containing CPU nodes with missing "reg"
> --
> 1.8.2.2
>
>
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss at lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [RFC PATCH v4 01/18] ARM: kernel: fix arm_dt_init_cpu_maps() to skip non-cpu nodes
2013-05-17 16:31 ` Rob Herring
@ 2013-05-17 17:04 ` Lorenzo Pieralisi
-1 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 17:04 UTC (permalink / raw)
To: Rob Herring
Cc: Nicolas Pitre, Jon Medhurst, Kukjin Kim, Russell King,
Andrew Lunn, Viresh Kumar,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Barry Song,
Will Deacon, Sekhar Nori, Simon Horman,
rob.herring-bsGFqQB8/DxBDgjK7y7TUQ, Amit Kucheria,
Catalin Marinas, grant.likely-QSEj5FYQhm4dnm+yROfE0A,
David Brown, Vinayak Kale, Lennert Buytenhek,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Magnus Damm
On Fri, May 17, 2013 at 05:31:18PM +0100, Rob Herring wrote:
> On Fri, May 17, 2013 at 10:20 AM, Lorenzo Pieralisi
> <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org> wrote:
> > The introduction of the cpu-map topology node in the cpus node implies
> > that cpus node might have children that are not cpu nodes. The DT
> > parsing code needs updating otherwise it would check for cpu nodes
> > properties in nodes that are not required to contain them, resulting
> > in warnings that have no bearing on bindings defined in the dts source file.
>
> Great, so a new DT with cpu-map entries may not work with old kernels.
> Please check the behavior. This should go to stable kernels.
You are right, and I do not see any other solution if we want the
cpu-map node to live in the cpus node; at the time we added the cpus/cpu
bindings we thought that the cpus node's children would be restricted to cpu
nodes, and well, we are changing that, this is one of the consequences.
Yes, this patch should go to stable kernels, I will do that.
Lorenzo
> Rob
>
> >
> > Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
> > ---
> > arch/arm/kernel/devtree.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
> > index 5af04f6..904cad5 100644
> > --- a/arch/arm/kernel/devtree.c
> > +++ b/arch/arm/kernel/devtree.c
> > @@ -92,6 +92,9 @@ void __init arm_dt_init_cpu_maps(void)
> > for_each_child_of_node(cpus, cpu) {
> > u32 hwid;
> >
> > + if (of_node_cmp(cpu->type, "cpu"))
> > + continue;
> > +
> > pr_debug(" * %s...\n", cpu->full_name);
> > /*
> > * A device tree containing CPU nodes with missing "reg"
> > --
> > 1.8.2.2
> >
> >
> > _______________________________________________
> > devicetree-discuss mailing list
> > devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org
> > https://lists.ozlabs.org/listinfo/devicetree-discuss
>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [RFC PATCH v4 01/18] ARM: kernel: fix arm_dt_init_cpu_maps() to skip non-cpu nodes
@ 2013-05-17 17:04 ` Lorenzo Pieralisi
0 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-05-17 17:04 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, May 17, 2013 at 05:31:18PM +0100, Rob Herring wrote:
> On Fri, May 17, 2013 at 10:20 AM, Lorenzo Pieralisi
> <lorenzo.pieralisi@arm.com> wrote:
> > The introduction of the cpu-map topology node in the cpus node implies
> > that cpus node might have children that are not cpu nodes. The DT
> > parsing code needs updating otherwise it would check for cpu nodes
> > properties in nodes that are not required to contain them, resulting
> > in warnings that have no bearing on bindings defined in the dts source file.
>
> Great, so a new DT with cpu-map entries may not work with old kernels.
> Please check the behavior. This should go to stable kernels.
You are right, and I do not see any other solution if we want the
cpu-map node to live in the cpus node; at the time we added the cpus/cpu
bindings we thought that the cpus node's children would be restricted to cpu
nodes, and well, we are changing that, this is one of the consequences.
Yes, this patch should go to stable kernels, I will do that.
Lorenzo
> Rob
>
> >
> > Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> > ---
> > arch/arm/kernel/devtree.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
> > index 5af04f6..904cad5 100644
> > --- a/arch/arm/kernel/devtree.c
> > +++ b/arch/arm/kernel/devtree.c
> > @@ -92,6 +92,9 @@ void __init arm_dt_init_cpu_maps(void)
> > for_each_child_of_node(cpus, cpu) {
> > u32 hwid;
> >
> > + if (of_node_cmp(cpu->type, "cpu"))
> > + continue;
> > +
> > pr_debug(" * %s...\n", cpu->full_name);
> > /*
> > * A device tree containing CPU nodes with missing "reg"
> > --
> > 1.8.2.2
> >
> >
> > _______________________________________________
> > devicetree-discuss mailing list
> > devicetree-discuss at lists.ozlabs.org
> > https://lists.ozlabs.org/listinfo/devicetree-discuss
>
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [RFC PATCH v4 05/18] ARM: dts: armada-370-xp: cpus/cpu node dts updates
2013-05-17 15:20 ` Lorenzo Pieralisi
@ 2013-05-17 17:16 ` Gregory CLEMENT
-1 siblings, 0 replies; 64+ messages in thread
From: Gregory CLEMENT @ 2013-05-17 17:16 UTC (permalink / raw)
To: Lorenzo Pieralisi
Cc: Nicolas Pitre, Jon Medhurst, Catalin Marinas, Andrew Lunn,
Will Deacon, Lennert Buytenhek, Kukjin Kim, Russell King,
Magnus Damm, Viresh Kumar, Grant Likely, David Brown,
Sekhar Nori, devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
Rob Herring, Simon Horman, Barry Song,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Amit Kucheria,
Vinayak Kale
On 05/17/2013 05:20 PM, Lorenzo Pieralisi wrote:
> This patch updates the in-kernel dts files according to the latest cpus
> and cpu bindings updates for ARM.
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
> ---
> arch/arm/boot/dts/armada-370-xp.dtsi | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
> index 272bbc6..2407903 100644
> --- a/arch/arm/boot/dts/armada-370-xp.dtsi
> +++ b/arch/arm/boot/dts/armada-370-xp.dtsi
> @@ -23,8 +23,12 @@
> compatible = "marvell,armada-370-xp";
>
> cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> cpu@0 {
> compatible = "marvell,sheeva-v7";
> + device_type = "cpu";
> + reg = <0>;
> };
> };
>
>
Acked-by: Gregory CLEMENT <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 64+ messages in thread
* [RFC PATCH v4 05/18] ARM: dts: armada-370-xp: cpus/cpu node dts updates
@ 2013-05-17 17:16 ` Gregory CLEMENT
0 siblings, 0 replies; 64+ messages in thread
From: Gregory CLEMENT @ 2013-05-17 17:16 UTC (permalink / raw)
To: linux-arm-kernel
On 05/17/2013 05:20 PM, Lorenzo Pieralisi wrote:
> This patch updates the in-kernel dts files according to the latest cpus
> and cpu bindings updates for ARM.
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> ---
> arch/arm/boot/dts/armada-370-xp.dtsi | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
> index 272bbc6..2407903 100644
> --- a/arch/arm/boot/dts/armada-370-xp.dtsi
> +++ b/arch/arm/boot/dts/armada-370-xp.dtsi
> @@ -23,8 +23,12 @@
> compatible = "marvell,armada-370-xp";
>
> cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> cpu at 0 {
> compatible = "marvell,sheeva-v7";
> + device_type = "cpu";
> + reg = <0>;
> };
> };
>
>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [RFC PATCH v4 03/18] Documentation: devicetree: arm: cpus/cpu nodes bindings updates
2013-05-17 15:20 ` Lorenzo Pieralisi
@ 2013-07-12 14:47 ` Rob Herring
-1 siblings, 0 replies; 64+ messages in thread
From: Rob Herring @ 2013-07-12 14:47 UTC (permalink / raw)
To: Lorenzo Pieralisi
Cc: Nicolas Pitre, Jon Medhurst, Catalin Marinas, Andrew Lunn,
Will Deacon, Lennert Buytenhek, Kukjin Kim, Russell King,
Magnus Damm, Viresh Kumar, Grant Likely, David Brown,
Sekhar Nori, devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
Rob Herring, Simon Horman, Barry Song,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Amit Kucheria,
Vinayak Kale
On Fri, May 17, 2013 at 10:20 AM, Lorenzo Pieralisi
<lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org> wrote:
> In order to extend the current cpu nodes bindings to newer CPUs
> inclusive of AArch64 and to update support for older ARM CPUs this
> patch updates device tree documentation for the cpu nodes bindings.
Sorry for the long delay on this, but I'm still not happy with the binding here.
> Main changes:
> - adds 64-bit bindings
> - define usage of #address-cells
> - define 32/64 dts compatibility settings
> - defines behaviour on pre and post v7 uniprocessor systems
> - adds ARM 11MPcore specific reg property definition
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
> ---
> Documentation/devicetree/bindings/arm/cpus.txt | 459 ++++++++++++++++++++++---
> 1 file changed, 412 insertions(+), 47 deletions(-)
[snip]
> + # On ARM v8 64-bit systems, where the reg property
> + size can be 1 or 2 cells (as defined by cpus node's
> + #address-cells property), this property is
> + required and matches:
> +
> + - On systems running the OS in AArch32:
The DTS cannot change based on 32-bit or 64-bit OS.
> +
> + * If the cpus node's #address-cells value is 2:
> +
> + The first reg cell must be set to 0.
> +
> + The second reg cell bits [23:0] must be set to
> + bits [23:0] of MPIDR_EL1.
> +
> + All other bits in the reg cells must be set to 0.
> +
> + * If the cpus node's #address-cells value is 1:
> +
> + Bits [23:0] in the reg cell must be set to
> + bits [23:0] in MPIDR_EL1.
> +
> + All other bits in the reg cell must be 0.
> +
> + - On systems running the OS in AArch64:
> +
> + * If the cpus node's #address-cells value is 2:
> +
> + The first reg cell bits [7:0] must be set to
> + bits [39:32] of MPIDR_EL1.
> +
> + The second reg cell bits [23:0] must be set to
> + bits [23:0] of MPIDR_EL1.
> +
> + All other bits in the reg cells must be set to 0.
> +
> + * If the cpus node's #address-cells value is 1:
> +
> + MPIDR_EL1[63:32] is 0 on all processors in the
> + system.
Your logic is backwards here. If the MPIDR_EL1[63:32] is 0, then
#address-cells can be 1. You could say the upper bits are ignored and
treated as 0. However, you should simplify all this and just mandate
that #address-cells must be 2 for ARMv8 or more generally must match
the size of the MPIDR. If we want to boot a 32-bit kernel, then the
kernel will have to adapt to support this.
> +
> + The reg cell bits [23:0] must be set to
> + bits [23:0] of MPIDR_EL1.
> +
> + All other bits in the reg cell must be set to 0.
> +
> + - compatible:
> + Usage: required
> + Value type: <string>
> + Definition: should be one of:
> + "arm,arm710t"
> + "arm,arm720t"
> + "arm,arm740t"
> + "arm,arm7ej-s"
> + "arm,arm7tdmi"
> + "arm,arm7tdmi-s"
> + "arm,arm9es"
> + "arm,arm9ej-s"
> + "arm,arm920t"
> + "arm,arm922t"
> + "arm,arm925"
> + "arm,arm926e-s"
> + "arm,arm926ej-s"
> + "arm,arm940t"
> + "arm,arm946e-s"
> + "arm,arm966e-s"
> + "arm,arm968e-s"
> + "arm,arm9tdmi"
> + "arm,arm1020e"
> + "arm,arm1020t"
> + "arm,arm1022e"
> + "arm,arm1026ej-s"
> + "arm,arm1136j-s"
> + "arm,arm1136jf-s"
> + "arm,arm1156t2-s"
> + "arm,arm1156t2f-s"
> + "arm,arm1176jzf"
> + "arm,arm1176jz-s"
> + "arm,arm1176jzf-s"
> + "arm,arm11mpcore"
> + "arm,cortex-a5"
> + "arm,cortex-a7"
> + "arm,cortex-a8"
> + "arm,cortex-a9"
> + "arm,cortex-a15"
> + "arm,cortex-a53"
> + "arm,cortex-a57"
> + "arm,cortex-m0"
> + "arm,cortex-m0+"
> + "arm,cortex-m1"
> + "arm,cortex-m3"
> + "arm,cortex-m4"
> + "arm,cortex-r4"
> + "arm,cortex-r5"
> + "arm,cortex-r7"
> + "faraday,fa526"
> + "intel,sa110"
> + "intel,sa1100"
> + "marvell,feroceon"
> + "marvell,mohawk"
> + "marvell,pj4"
> + "marvell,sheeva-v7"
> + "marvell,xsc3"
> + "marvell,xscale"
> + "qcom,krait"
> + "qcom,scorpion"
> + - enable-method
> + Value type: <stringlist>
> + Usage and definition depend on ARM architecture version and
> + configuration:
> + # On ARM v8 64-bit systems running the OS in AArch64,
Again, the DTS can't depend on the OS type.
> + this property is required and must be one of:
> + "spin-table"
> + "psci"
> + # On ARM 32-bit systems or ARM v8 systems running
> + the OS in AArch32 this property is prohibited.
I still don't get the distinction between 32 and 64 bit here. On
32-bit, you have 3 choices: psci, spin-table, or SoC specific. So make
this property optional for 32-bit and mandatory for 64-bit.
> +
> + - cpu-release-addr
> + Usage: required for systems that have an "enable-method"
> + property value of "spin-table".
> + Value type: <prop-encoded-array>
> + Definition:
> + # On ARM v8 64-bit systems must be a two cell
> + property identifying a 64-bit zero-initialised
> + memory location.
As I mentioned previously, isn't some wake-up method needed? Most
systems will be in wfi or wfe rather than continuously spinning.
Rob
^ permalink raw reply [flat|nested] 64+ messages in thread
* [RFC PATCH v4 03/18] Documentation: devicetree: arm: cpus/cpu nodes bindings updates
@ 2013-07-12 14:47 ` Rob Herring
0 siblings, 0 replies; 64+ messages in thread
From: Rob Herring @ 2013-07-12 14:47 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, May 17, 2013 at 10:20 AM, Lorenzo Pieralisi
<lorenzo.pieralisi@arm.com> wrote:
> In order to extend the current cpu nodes bindings to newer CPUs
> inclusive of AArch64 and to update support for older ARM CPUs this
> patch updates device tree documentation for the cpu nodes bindings.
Sorry for the long delay on this, but I'm still not happy with the binding here.
> Main changes:
> - adds 64-bit bindings
> - define usage of #address-cells
> - define 32/64 dts compatibility settings
> - defines behaviour on pre and post v7 uniprocessor systems
> - adds ARM 11MPcore specific reg property definition
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> ---
> Documentation/devicetree/bindings/arm/cpus.txt | 459 ++++++++++++++++++++++---
> 1 file changed, 412 insertions(+), 47 deletions(-)
[snip]
> + # On ARM v8 64-bit systems, where the reg property
> + size can be 1 or 2 cells (as defined by cpus node's
> + #address-cells property), this property is
> + required and matches:
> +
> + - On systems running the OS in AArch32:
The DTS cannot change based on 32-bit or 64-bit OS.
> +
> + * If the cpus node's #address-cells value is 2:
> +
> + The first reg cell must be set to 0.
> +
> + The second reg cell bits [23:0] must be set to
> + bits [23:0] of MPIDR_EL1.
> +
> + All other bits in the reg cells must be set to 0.
> +
> + * If the cpus node's #address-cells value is 1:
> +
> + Bits [23:0] in the reg cell must be set to
> + bits [23:0] in MPIDR_EL1.
> +
> + All other bits in the reg cell must be 0.
> +
> + - On systems running the OS in AArch64:
> +
> + * If the cpus node's #address-cells value is 2:
> +
> + The first reg cell bits [7:0] must be set to
> + bits [39:32] of MPIDR_EL1.
> +
> + The second reg cell bits [23:0] must be set to
> + bits [23:0] of MPIDR_EL1.
> +
> + All other bits in the reg cells must be set to 0.
> +
> + * If the cpus node's #address-cells value is 1:
> +
> + MPIDR_EL1[63:32] is 0 on all processors in the
> + system.
Your logic is backwards here. If the MPIDR_EL1[63:32] is 0, then
#address-cells can be 1. You could say the upper bits are ignored and
treated as 0. However, you should simplify all this and just mandate
that #address-cells must be 2 for ARMv8 or more generally must match
the size of the MPIDR. If we want to boot a 32-bit kernel, then the
kernel will have to adapt to support this.
> +
> + The reg cell bits [23:0] must be set to
> + bits [23:0] of MPIDR_EL1.
> +
> + All other bits in the reg cell must be set to 0.
> +
> + - compatible:
> + Usage: required
> + Value type: <string>
> + Definition: should be one of:
> + "arm,arm710t"
> + "arm,arm720t"
> + "arm,arm740t"
> + "arm,arm7ej-s"
> + "arm,arm7tdmi"
> + "arm,arm7tdmi-s"
> + "arm,arm9es"
> + "arm,arm9ej-s"
> + "arm,arm920t"
> + "arm,arm922t"
> + "arm,arm925"
> + "arm,arm926e-s"
> + "arm,arm926ej-s"
> + "arm,arm940t"
> + "arm,arm946e-s"
> + "arm,arm966e-s"
> + "arm,arm968e-s"
> + "arm,arm9tdmi"
> + "arm,arm1020e"
> + "arm,arm1020t"
> + "arm,arm1022e"
> + "arm,arm1026ej-s"
> + "arm,arm1136j-s"
> + "arm,arm1136jf-s"
> + "arm,arm1156t2-s"
> + "arm,arm1156t2f-s"
> + "arm,arm1176jzf"
> + "arm,arm1176jz-s"
> + "arm,arm1176jzf-s"
> + "arm,arm11mpcore"
> + "arm,cortex-a5"
> + "arm,cortex-a7"
> + "arm,cortex-a8"
> + "arm,cortex-a9"
> + "arm,cortex-a15"
> + "arm,cortex-a53"
> + "arm,cortex-a57"
> + "arm,cortex-m0"
> + "arm,cortex-m0+"
> + "arm,cortex-m1"
> + "arm,cortex-m3"
> + "arm,cortex-m4"
> + "arm,cortex-r4"
> + "arm,cortex-r5"
> + "arm,cortex-r7"
> + "faraday,fa526"
> + "intel,sa110"
> + "intel,sa1100"
> + "marvell,feroceon"
> + "marvell,mohawk"
> + "marvell,pj4"
> + "marvell,sheeva-v7"
> + "marvell,xsc3"
> + "marvell,xscale"
> + "qcom,krait"
> + "qcom,scorpion"
> + - enable-method
> + Value type: <stringlist>
> + Usage and definition depend on ARM architecture version and
> + configuration:
> + # On ARM v8 64-bit systems running the OS in AArch64,
Again, the DTS can't depend on the OS type.
> + this property is required and must be one of:
> + "spin-table"
> + "psci"
> + # On ARM 32-bit systems or ARM v8 systems running
> + the OS in AArch32 this property is prohibited.
I still don't get the distinction between 32 and 64 bit here. On
32-bit, you have 3 choices: psci, spin-table, or SoC specific. So make
this property optional for 32-bit and mandatory for 64-bit.
> +
> + - cpu-release-addr
> + Usage: required for systems that have an "enable-method"
> + property value of "spin-table".
> + Value type: <prop-encoded-array>
> + Definition:
> + # On ARM v8 64-bit systems must be a two cell
> + property identifying a 64-bit zero-initialised
> + memory location.
As I mentioned previously, isn't some wake-up method needed? Most
systems will be in wfi or wfe rather than continuously spinning.
Rob
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [RFC PATCH v4 03/18] Documentation: devicetree: arm: cpus/cpu nodes bindings updates
2013-07-12 14:47 ` Rob Herring
@ 2013-07-15 9:34 ` Lorenzo Pieralisi
-1 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-07-15 9:34 UTC (permalink / raw)
To: Rob Herring
Cc: Nicolas Pitre, Jon Medhurst, Catalin Marinas, Andrew Lunn,
Will Deacon, Lennert Buytenhek, Kukjin Kim, Russell King,
Magnus Damm, Viresh Kumar, grant.likely-QSEj5FYQhm4dnm+yROfE0A,
David Brown, Sekhar Nori,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
rob.herring-bsGFqQB8/DxBDgjK7y7TUQ, Simon Horman, Barry Song,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Amit Kucheria,
Vinayak Kale
On Fri, Jul 12, 2013 at 03:47:17PM +0100, Rob Herring wrote:
> On Fri, May 17, 2013 at 10:20 AM, Lorenzo Pieralisi
> <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org> wrote:
> > In order to extend the current cpu nodes bindings to newer CPUs
> > inclusive of AArch64 and to update support for older ARM CPUs this
> > patch updates device tree documentation for the cpu nodes bindings.
>
> Sorry for the long delay on this, but I'm still not happy with the binding here.
I had to ask Russell again to drop the bindings patches from the patch
system, and this is not acceptable since two months have passed and the
entire series was reviewed, acked and partially merged. I will review
these bindings again but I would like to understand who should give the final
go ahead to get these patches queued for upstreaming, I can't continue
updating this stuff forever.
> > Main changes:
> > - adds 64-bit bindings
> > - define usage of #address-cells
> > - define 32/64 dts compatibility settings
> > - defines behaviour on pre and post v7 uniprocessor systems
> > - adds ARM 11MPcore specific reg property definition
> >
> > Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
> > ---
> > Documentation/devicetree/bindings/arm/cpus.txt | 459 ++++++++++++++++++++++---
> > 1 file changed, 412 insertions(+), 47 deletions(-)
>
> [snip]
>
> > + # On ARM v8 64-bit systems, where the reg property
> > + size can be 1 or 2 cells (as defined by cpus node's
> > + #address-cells property), this property is
> > + required and matches:
> > +
> > + - On systems running the OS in AArch32:
>
> The DTS cannot change based on 32-bit or 64-bit OS.
"On systems running the OS in AArch32" implies a dependency on the
HW execution state. Since the DT is used to configure OSs I thought that
could be a valid sentence. Unfortunately this stuff is not C, so I
reiterate my point above, before changing it I would like to understand
who should say the wording is ok otherwise we could argue forever.
> > +
> > + * If the cpus node's #address-cells value is 2:
> > +
> > + The first reg cell must be set to 0.
> > +
> > + The second reg cell bits [23:0] must be set to
> > + bits [23:0] of MPIDR_EL1.
> > +
> > + All other bits in the reg cells must be set to 0.
> > +
> > + * If the cpus node's #address-cells value is 1:
> > +
> > + Bits [23:0] in the reg cell must be set to
> > + bits [23:0] in MPIDR_EL1.
> > +
> > + All other bits in the reg cell must be 0.
> > +
> > + - On systems running the OS in AArch64:
> > +
> > + * If the cpus node's #address-cells value is 2:
> > +
> > + The first reg cell bits [7:0] must be set to
> > + bits [39:32] of MPIDR_EL1.
> > +
> > + The second reg cell bits [23:0] must be set to
> > + bits [23:0] of MPIDR_EL1.
> > +
> > + All other bits in the reg cells must be set to 0.
> > +
> > + * If the cpus node's #address-cells value is 1:
> > +
> > + MPIDR_EL1[63:32] is 0 on all processors in the
> > + system.
>
> Your logic is backwards here. If the MPIDR_EL1[63:32] is 0, then
> #address-cells can be 1. You could say the upper bits are ignored and
> treated as 0. However, you should simplify all this and just mandate
> that #address-cells must be 2 for ARMv8 or more generally must match
> the size of the MPIDR. If we want to boot a 32-bit kernel, then the
> kernel will have to adapt to support this.
Fair enough I will see how I can reword it.
> > +
> > + The reg cell bits [23:0] must be set to
> > + bits [23:0] of MPIDR_EL1.
> > +
> > + All other bits in the reg cell must be set to 0.
> > +
> > + - compatible:
> > + Usage: required
> > + Value type: <string>
> > + Definition: should be one of:
> > + "arm,arm710t"
> > + "arm,arm720t"
> > + "arm,arm740t"
> > + "arm,arm7ej-s"
> > + "arm,arm7tdmi"
> > + "arm,arm7tdmi-s"
> > + "arm,arm9es"
> > + "arm,arm9ej-s"
> > + "arm,arm920t"
> > + "arm,arm922t"
> > + "arm,arm925"
> > + "arm,arm926e-s"
> > + "arm,arm926ej-s"
> > + "arm,arm940t"
> > + "arm,arm946e-s"
> > + "arm,arm966e-s"
> > + "arm,arm968e-s"
> > + "arm,arm9tdmi"
> > + "arm,arm1020e"
> > + "arm,arm1020t"
> > + "arm,arm1022e"
> > + "arm,arm1026ej-s"
> > + "arm,arm1136j-s"
> > + "arm,arm1136jf-s"
> > + "arm,arm1156t2-s"
> > + "arm,arm1156t2f-s"
> > + "arm,arm1176jzf"
> > + "arm,arm1176jz-s"
> > + "arm,arm1176jzf-s"
> > + "arm,arm11mpcore"
> > + "arm,cortex-a5"
> > + "arm,cortex-a7"
> > + "arm,cortex-a8"
> > + "arm,cortex-a9"
> > + "arm,cortex-a15"
> > + "arm,cortex-a53"
> > + "arm,cortex-a57"
> > + "arm,cortex-m0"
> > + "arm,cortex-m0+"
> > + "arm,cortex-m1"
> > + "arm,cortex-m3"
> > + "arm,cortex-m4"
> > + "arm,cortex-r4"
> > + "arm,cortex-r5"
> > + "arm,cortex-r7"
> > + "faraday,fa526"
> > + "intel,sa110"
> > + "intel,sa1100"
> > + "marvell,feroceon"
> > + "marvell,mohawk"
> > + "marvell,pj4"
> > + "marvell,sheeva-v7"
> > + "marvell,xsc3"
> > + "marvell,xscale"
> > + "qcom,krait"
> > + "qcom,scorpion"
> > + - enable-method
> > + Value type: <stringlist>
> > + Usage and definition depend on ARM architecture version and
> > + configuration:
> > + # On ARM v8 64-bit systems running the OS in AArch64,
>
> Again, the DTS can't depend on the OS type.
It was meant to make it dependent on the execution state.
> > + this property is required and must be one of:
> > + "spin-table"
> > + "psci"
> > + # On ARM 32-bit systems or ARM v8 systems running
> > + the OS in AArch32 this property is prohibited.
>
> I still don't get the distinction between 32 and 64 bit here. On
> 32-bit, you have 3 choices: psci, spin-table, or SoC specific. So make
> this property optional for 32-bit and mandatory for 64-bit.
Ok.
> > +
> > + - cpu-release-addr
> > + Usage: required for systems that have an "enable-method"
> > + property value of "spin-table".
> > + Value type: <prop-encoded-array>
> > + Definition:
> > + # On ARM v8 64-bit systems must be a two cell
> > + property identifying a 64-bit zero-initialised
> > + memory location.
>
> As I mentioned previously, isn't some wake-up method needed? Most
> systems will be in wfi or wfe rather than continuously spinning.
Mmm...this can become a minefield, wfe, wfi, CPU in reset..this needs some
thought.
Thanks,
Lorenzo
^ permalink raw reply [flat|nested] 64+ messages in thread
* [RFC PATCH v4 03/18] Documentation: devicetree: arm: cpus/cpu nodes bindings updates
@ 2013-07-15 9:34 ` Lorenzo Pieralisi
0 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-07-15 9:34 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jul 12, 2013 at 03:47:17PM +0100, Rob Herring wrote:
> On Fri, May 17, 2013 at 10:20 AM, Lorenzo Pieralisi
> <lorenzo.pieralisi@arm.com> wrote:
> > In order to extend the current cpu nodes bindings to newer CPUs
> > inclusive of AArch64 and to update support for older ARM CPUs this
> > patch updates device tree documentation for the cpu nodes bindings.
>
> Sorry for the long delay on this, but I'm still not happy with the binding here.
I had to ask Russell again to drop the bindings patches from the patch
system, and this is not acceptable since two months have passed and the
entire series was reviewed, acked and partially merged. I will review
these bindings again but I would like to understand who should give the final
go ahead to get these patches queued for upstreaming, I can't continue
updating this stuff forever.
> > Main changes:
> > - adds 64-bit bindings
> > - define usage of #address-cells
> > - define 32/64 dts compatibility settings
> > - defines behaviour on pre and post v7 uniprocessor systems
> > - adds ARM 11MPcore specific reg property definition
> >
> > Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> > ---
> > Documentation/devicetree/bindings/arm/cpus.txt | 459 ++++++++++++++++++++++---
> > 1 file changed, 412 insertions(+), 47 deletions(-)
>
> [snip]
>
> > + # On ARM v8 64-bit systems, where the reg property
> > + size can be 1 or 2 cells (as defined by cpus node's
> > + #address-cells property), this property is
> > + required and matches:
> > +
> > + - On systems running the OS in AArch32:
>
> The DTS cannot change based on 32-bit or 64-bit OS.
"On systems running the OS in AArch32" implies a dependency on the
HW execution state. Since the DT is used to configure OSs I thought that
could be a valid sentence. Unfortunately this stuff is not C, so I
reiterate my point above, before changing it I would like to understand
who should say the wording is ok otherwise we could argue forever.
> > +
> > + * If the cpus node's #address-cells value is 2:
> > +
> > + The first reg cell must be set to 0.
> > +
> > + The second reg cell bits [23:0] must be set to
> > + bits [23:0] of MPIDR_EL1.
> > +
> > + All other bits in the reg cells must be set to 0.
> > +
> > + * If the cpus node's #address-cells value is 1:
> > +
> > + Bits [23:0] in the reg cell must be set to
> > + bits [23:0] in MPIDR_EL1.
> > +
> > + All other bits in the reg cell must be 0.
> > +
> > + - On systems running the OS in AArch64:
> > +
> > + * If the cpus node's #address-cells value is 2:
> > +
> > + The first reg cell bits [7:0] must be set to
> > + bits [39:32] of MPIDR_EL1.
> > +
> > + The second reg cell bits [23:0] must be set to
> > + bits [23:0] of MPIDR_EL1.
> > +
> > + All other bits in the reg cells must be set to 0.
> > +
> > + * If the cpus node's #address-cells value is 1:
> > +
> > + MPIDR_EL1[63:32] is 0 on all processors in the
> > + system.
>
> Your logic is backwards here. If the MPIDR_EL1[63:32] is 0, then
> #address-cells can be 1. You could say the upper bits are ignored and
> treated as 0. However, you should simplify all this and just mandate
> that #address-cells must be 2 for ARMv8 or more generally must match
> the size of the MPIDR. If we want to boot a 32-bit kernel, then the
> kernel will have to adapt to support this.
Fair enough I will see how I can reword it.
> > +
> > + The reg cell bits [23:0] must be set to
> > + bits [23:0] of MPIDR_EL1.
> > +
> > + All other bits in the reg cell must be set to 0.
> > +
> > + - compatible:
> > + Usage: required
> > + Value type: <string>
> > + Definition: should be one of:
> > + "arm,arm710t"
> > + "arm,arm720t"
> > + "arm,arm740t"
> > + "arm,arm7ej-s"
> > + "arm,arm7tdmi"
> > + "arm,arm7tdmi-s"
> > + "arm,arm9es"
> > + "arm,arm9ej-s"
> > + "arm,arm920t"
> > + "arm,arm922t"
> > + "arm,arm925"
> > + "arm,arm926e-s"
> > + "arm,arm926ej-s"
> > + "arm,arm940t"
> > + "arm,arm946e-s"
> > + "arm,arm966e-s"
> > + "arm,arm968e-s"
> > + "arm,arm9tdmi"
> > + "arm,arm1020e"
> > + "arm,arm1020t"
> > + "arm,arm1022e"
> > + "arm,arm1026ej-s"
> > + "arm,arm1136j-s"
> > + "arm,arm1136jf-s"
> > + "arm,arm1156t2-s"
> > + "arm,arm1156t2f-s"
> > + "arm,arm1176jzf"
> > + "arm,arm1176jz-s"
> > + "arm,arm1176jzf-s"
> > + "arm,arm11mpcore"
> > + "arm,cortex-a5"
> > + "arm,cortex-a7"
> > + "arm,cortex-a8"
> > + "arm,cortex-a9"
> > + "arm,cortex-a15"
> > + "arm,cortex-a53"
> > + "arm,cortex-a57"
> > + "arm,cortex-m0"
> > + "arm,cortex-m0+"
> > + "arm,cortex-m1"
> > + "arm,cortex-m3"
> > + "arm,cortex-m4"
> > + "arm,cortex-r4"
> > + "arm,cortex-r5"
> > + "arm,cortex-r7"
> > + "faraday,fa526"
> > + "intel,sa110"
> > + "intel,sa1100"
> > + "marvell,feroceon"
> > + "marvell,mohawk"
> > + "marvell,pj4"
> > + "marvell,sheeva-v7"
> > + "marvell,xsc3"
> > + "marvell,xscale"
> > + "qcom,krait"
> > + "qcom,scorpion"
> > + - enable-method
> > + Value type: <stringlist>
> > + Usage and definition depend on ARM architecture version and
> > + configuration:
> > + # On ARM v8 64-bit systems running the OS in AArch64,
>
> Again, the DTS can't depend on the OS type.
It was meant to make it dependent on the execution state.
> > + this property is required and must be one of:
> > + "spin-table"
> > + "psci"
> > + # On ARM 32-bit systems or ARM v8 systems running
> > + the OS in AArch32 this property is prohibited.
>
> I still don't get the distinction between 32 and 64 bit here. On
> 32-bit, you have 3 choices: psci, spin-table, or SoC specific. So make
> this property optional for 32-bit and mandatory for 64-bit.
Ok.
> > +
> > + - cpu-release-addr
> > + Usage: required for systems that have an "enable-method"
> > + property value of "spin-table".
> > + Value type: <prop-encoded-array>
> > + Definition:
> > + # On ARM v8 64-bit systems must be a two cell
> > + property identifying a 64-bit zero-initialised
> > + memory location.
>
> As I mentioned previously, isn't some wake-up method needed? Most
> systems will be in wfi or wfe rather than continuously spinning.
Mmm...this can become a minefield, wfe, wfi, CPU in reset..this needs some
thought.
Thanks,
Lorenzo
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [RFC PATCH v4 03/18] Documentation: devicetree: arm: cpus/cpu nodes bindings updates
2013-07-15 9:34 ` Lorenzo Pieralisi
@ 2013-07-15 18:50 ` Rob Herring
-1 siblings, 0 replies; 64+ messages in thread
From: Rob Herring @ 2013-07-15 18:50 UTC (permalink / raw)
To: Lorenzo Pieralisi
Cc: Nicolas Pitre, Jon Medhurst, Catalin Marinas, Andrew Lunn,
Will Deacon, Lennert Buytenhek, Kukjin Kim, Russell King,
Magnus Damm, Viresh Kumar, grant.likely-QSEj5FYQhm4dnm+yROfE0A,
David Brown, Sekhar Nori,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Simon Horman,
Barry Song, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Amit Kucheria, Vinayak Kale
On 07/15/2013 04:34 AM, Lorenzo Pieralisi wrote:
> On Fri, Jul 12, 2013 at 03:47:17PM +0100, Rob Herring wrote:
>> On Fri, May 17, 2013 at 10:20 AM, Lorenzo Pieralisi
>> <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org> wrote:
>>> In order to extend the current cpu nodes bindings to newer CPUs
>>> inclusive of AArch64 and to update support for older ARM CPUs this
>>> patch updates device tree documentation for the cpu nodes bindings.
>>
>> Sorry for the long delay on this, but I'm still not happy with the binding here.
>
> I had to ask Russell again to drop the bindings patches from the patch
> system, and this is not acceptable since two months have passed and the
> entire series was reviewed, acked and partially merged. I will review
> these bindings again but I would like to understand who should give the final
> go ahead to get these patches queued for upstreaming, I can't continue
> updating this stuff forever.
Most of my comments are for 64-bit. So don't blame me that it had to be
reverted. I said up front I was concerned about this change breaking
things and it appears it did. New kernels must not require a new DT.
But yes, this should have been reviewed more quickly. We're working on a
plan to help address DT binding reviews. We have not enforced that Grant
and I must ack all bindings, but in this case you certainly need mine
since I have reviewed it and if you want to me to pull it.
>>> Main changes:
>>> - adds 64-bit bindings
>>> - define usage of #address-cells
>>> - define 32/64 dts compatibility settings
>>> - defines behaviour on pre and post v7 uniprocessor systems
>>> - adds ARM 11MPcore specific reg property definition
>>>
>>> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
>>> ---
>>> Documentation/devicetree/bindings/arm/cpus.txt | 459 ++++++++++++++++++++++---
>>> 1 file changed, 412 insertions(+), 47 deletions(-)
>>
>> [snip]
>>
>>> + # On ARM v8 64-bit systems, where the reg property
>>> + size can be 1 or 2 cells (as defined by cpus node's
>>> + #address-cells property), this property is
>>> + required and matches:
>>> +
>>> + - On systems running the OS in AArch32:
>>
>> The DTS cannot change based on 32-bit or 64-bit OS.
>
> "On systems running the OS in AArch32" implies a dependency on the
> HW execution state. Since the DT is used to configure OSs I thought that
> could be a valid sentence. Unfortunately this stuff is not C, so I
> reiterate my point above, before changing it I would like to understand
> who should say the wording is ok otherwise we could argue forever.
It does configure the OS, but not for 32 vs. 64 bit. That is more of a
problem for the bootloader to know which mode to boot in and covered
under something like Documentation/arm/Booting. Booting ARM vs. Thumb
mode would be similar situation.
Think about how your PC boots and add to that having a DTB as part of
the firmware shipped with your PC. Then the end user can install a
32-bit or 64-bit OS on it. That is the usecase that needs to be
supported and having different DTB for 32 and 64 bit is totally broken
and doesn't even help solve that problem.
>>> +
>>> + - cpu-release-addr
>>> + Usage: required for systems that have an "enable-method"
>>> + property value of "spin-table".
>>> + Value type: <prop-encoded-array>
>>> + Definition:
>>> + # On ARM v8 64-bit systems must be a two cell
>>> + property identifying a 64-bit zero-initialised
>>> + memory location.
>>
>> As I mentioned previously, isn't some wake-up method needed? Most
>> systems will be in wfi or wfe rather than continuously spinning.
>
> Mmm...this can become a minefield, wfe, wfi, CPU in reset..this needs some
> thought.
Yes, it is today and standardizing this is a good thing. Which is what
PSCI does. So why are you adding the spintable at all? Are you trying to
set this as the standard for non-PSCI enabled platforms? Why not just
say v8 boot interface is PSCI. Sure, we'll probably have to deal with
other methods, but documenting something else here is not going to
prevent that problem. I don't think a simple spintable would even work
for any/most current platforms. I'd think we'd want to define something
that would work for existing platforms (chances are new platforms will
work like vendors' existing 32-bit platforms).
Rob
^ permalink raw reply [flat|nested] 64+ messages in thread
* [RFC PATCH v4 03/18] Documentation: devicetree: arm: cpus/cpu nodes bindings updates
@ 2013-07-15 18:50 ` Rob Herring
0 siblings, 0 replies; 64+ messages in thread
From: Rob Herring @ 2013-07-15 18:50 UTC (permalink / raw)
To: linux-arm-kernel
On 07/15/2013 04:34 AM, Lorenzo Pieralisi wrote:
> On Fri, Jul 12, 2013 at 03:47:17PM +0100, Rob Herring wrote:
>> On Fri, May 17, 2013 at 10:20 AM, Lorenzo Pieralisi
>> <lorenzo.pieralisi@arm.com> wrote:
>>> In order to extend the current cpu nodes bindings to newer CPUs
>>> inclusive of AArch64 and to update support for older ARM CPUs this
>>> patch updates device tree documentation for the cpu nodes bindings.
>>
>> Sorry for the long delay on this, but I'm still not happy with the binding here.
>
> I had to ask Russell again to drop the bindings patches from the patch
> system, and this is not acceptable since two months have passed and the
> entire series was reviewed, acked and partially merged. I will review
> these bindings again but I would like to understand who should give the final
> go ahead to get these patches queued for upstreaming, I can't continue
> updating this stuff forever.
Most of my comments are for 64-bit. So don't blame me that it had to be
reverted. I said up front I was concerned about this change breaking
things and it appears it did. New kernels must not require a new DT.
But yes, this should have been reviewed more quickly. We're working on a
plan to help address DT binding reviews. We have not enforced that Grant
and I must ack all bindings, but in this case you certainly need mine
since I have reviewed it and if you want to me to pull it.
>>> Main changes:
>>> - adds 64-bit bindings
>>> - define usage of #address-cells
>>> - define 32/64 dts compatibility settings
>>> - defines behaviour on pre and post v7 uniprocessor systems
>>> - adds ARM 11MPcore specific reg property definition
>>>
>>> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
>>> ---
>>> Documentation/devicetree/bindings/arm/cpus.txt | 459 ++++++++++++++++++++++---
>>> 1 file changed, 412 insertions(+), 47 deletions(-)
>>
>> [snip]
>>
>>> + # On ARM v8 64-bit systems, where the reg property
>>> + size can be 1 or 2 cells (as defined by cpus node's
>>> + #address-cells property), this property is
>>> + required and matches:
>>> +
>>> + - On systems running the OS in AArch32:
>>
>> The DTS cannot change based on 32-bit or 64-bit OS.
>
> "On systems running the OS in AArch32" implies a dependency on the
> HW execution state. Since the DT is used to configure OSs I thought that
> could be a valid sentence. Unfortunately this stuff is not C, so I
> reiterate my point above, before changing it I would like to understand
> who should say the wording is ok otherwise we could argue forever.
It does configure the OS, but not for 32 vs. 64 bit. That is more of a
problem for the bootloader to know which mode to boot in and covered
under something like Documentation/arm/Booting. Booting ARM vs. Thumb
mode would be similar situation.
Think about how your PC boots and add to that having a DTB as part of
the firmware shipped with your PC. Then the end user can install a
32-bit or 64-bit OS on it. That is the usecase that needs to be
supported and having different DTB for 32 and 64 bit is totally broken
and doesn't even help solve that problem.
>>> +
>>> + - cpu-release-addr
>>> + Usage: required for systems that have an "enable-method"
>>> + property value of "spin-table".
>>> + Value type: <prop-encoded-array>
>>> + Definition:
>>> + # On ARM v8 64-bit systems must be a two cell
>>> + property identifying a 64-bit zero-initialised
>>> + memory location.
>>
>> As I mentioned previously, isn't some wake-up method needed? Most
>> systems will be in wfi or wfe rather than continuously spinning.
>
> Mmm...this can become a minefield, wfe, wfi, CPU in reset..this needs some
> thought.
Yes, it is today and standardizing this is a good thing. Which is what
PSCI does. So why are you adding the spintable at all? Are you trying to
set this as the standard for non-PSCI enabled platforms? Why not just
say v8 boot interface is PSCI. Sure, we'll probably have to deal with
other methods, but documenting something else here is not going to
prevent that problem. I don't think a simple spintable would even work
for any/most current platforms. I'd think we'd want to define something
that would work for existing platforms (chances are new platforms will
work like vendors' existing 32-bit platforms).
Rob
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [RFC PATCH v4 03/18] Documentation: devicetree: arm: cpus/cpu nodes bindings updates
2013-07-15 18:50 ` Rob Herring
@ 2013-07-16 9:45 ` Lorenzo Pieralisi
-1 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-07-16 9:45 UTC (permalink / raw)
To: Rob Herring
Cc: Nicolas Pitre, Jon Medhurst, Catalin Marinas, Andrew Lunn,
Will Deacon, Lennert Buytenhek, Kukjin Kim, Russell King,
Magnus Damm, Viresh Kumar, grant.likely-QSEj5FYQhm4dnm+yROfE0A,
David Brown, Sekhar Nori,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Simon Horman,
Barry Song, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Amit Kucheria, Vinayak Kale
On Mon, Jul 15, 2013 at 07:50:46PM +0100, Rob Herring wrote:
> On 07/15/2013 04:34 AM, Lorenzo Pieralisi wrote:
> > On Fri, Jul 12, 2013 at 03:47:17PM +0100, Rob Herring wrote:
> >> On Fri, May 17, 2013 at 10:20 AM, Lorenzo Pieralisi
> >> <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org> wrote:
> >>> In order to extend the current cpu nodes bindings to newer CPUs
> >>> inclusive of AArch64 and to update support for older ARM CPUs this
> >>> patch updates device tree documentation for the cpu nodes bindings.
> >>
> >> Sorry for the long delay on this, but I'm still not happy with the binding here.
> >
> > I had to ask Russell again to drop the bindings patches from the patch
> > system, and this is not acceptable since two months have passed and the
> > entire series was reviewed, acked and partially merged. I will review
> > these bindings again but I would like to understand who should give the final
> > go ahead to get these patches queued for upstreaming, I can't continue
> > updating this stuff forever.
>
> Most of my comments are for 64-bit. So don't blame me that it had to be
> reverted. I said up front I was concerned about this change breaking
> things and it appears it did. New kernels must not require a new DT.
The patches in Russell's tree do not break anything, I asked him to drop
them since, if we change the bindings again, those patches change and have
to be reworked. It was not meant to blame you at all, just saying that
the process to get this stuff in the kernel should be defined properly
and patches reviewed in a timely fashion.
And for legacy reasons the situation related to cpu/cpus node bindings
is a complicated one, there are bindings in the ePAPR, bindings in the
kernel, people are confused and with this set we wanted to draw a
line. For arm64 this is an absolute must.
I disagree with you on the "new kernels must not require a new DT".
That's true if bindings are well defined, not for a mix of legacy ePAPR and
bindings-in-the-kernel.
What's the DT standard for ARM cpu/cpus node ? ePAPR ? In kernel docs ?
A combination thereof ? Things are not clear cut and I do not like that, it
is confusing.
> But yes, this should have been reviewed more quickly. We're working on a
> plan to help address DT binding reviews. We have not enforced that Grant
> and I must ack all bindings, but in this case you certainly need mine
> since I have reviewed it and if you want to me to pull it.
Good, that's all I wanted to know, thanks.
> >>> Main changes:
> >>> - adds 64-bit bindings
> >>> - define usage of #address-cells
> >>> - define 32/64 dts compatibility settings
> >>> - defines behaviour on pre and post v7 uniprocessor systems
> >>> - adds ARM 11MPcore specific reg property definition
> >>>
> >>> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
> >>> ---
> >>> Documentation/devicetree/bindings/arm/cpus.txt | 459 ++++++++++++++++++++++---
> >>> 1 file changed, 412 insertions(+), 47 deletions(-)
> >>
> >> [snip]
> >>
> >>> + # On ARM v8 64-bit systems, where the reg property
> >>> + size can be 1 or 2 cells (as defined by cpus node's
> >>> + #address-cells property), this property is
> >>> + required and matches:
> >>> +
> >>> + - On systems running the OS in AArch32:
> >>
> >> The DTS cannot change based on 32-bit or 64-bit OS.
> >
> > "On systems running the OS in AArch32" implies a dependency on the
> > HW execution state. Since the DT is used to configure OSs I thought that
> > could be a valid sentence. Unfortunately this stuff is not C, so I
> > reiterate my point above, before changing it I would like to understand
> > who should say the wording is ok otherwise we could argue forever.
>
> It does configure the OS, but not for 32 vs. 64 bit. That is more of a
> problem for the bootloader to know which mode to boot in and covered
> under something like Documentation/arm/Booting. Booting ARM vs. Thumb
> mode would be similar situation.
>
> Think about how your PC boots and add to that having a DTB as part of
> the firmware shipped with your PC. Then the end user can install a
> 32-bit or 64-bit OS on it. That is the usecase that needs to be
> supported and having different DTB for 32 and 64 bit is totally broken
> and doesn't even help solve that problem.
I will give it more thought, point taken.
> >>> +
> >>> + - cpu-release-addr
> >>> + Usage: required for systems that have an "enable-method"
> >>> + property value of "spin-table".
> >>> + Value type: <prop-encoded-array>
> >>> + Definition:
> >>> + # On ARM v8 64-bit systems must be a two cell
> >>> + property identifying a 64-bit zero-initialised
> >>> + memory location.
> >>
> >> As I mentioned previously, isn't some wake-up method needed? Most
> >> systems will be in wfi or wfe rather than continuously spinning.
> >
> > Mmm...this can become a minefield, wfe, wfi, CPU in reset..this needs some
> > thought.
>
> Yes, it is today and standardizing this is a good thing. Which is what
> PSCI does. So why are you adding the spintable at all? Are you trying to
> set this as the standard for non-PSCI enabled platforms? Why not just
> say v8 boot interface is PSCI. Sure, we'll probably have to deal with
> other methods, but documenting something else here is not going to
> prevent that problem. I don't think a simple spintable would even work
> for any/most current platforms. I'd think we'd want to define something
> that would work for existing platforms (chances are new platforms will
> work like vendors' existing 32-bit platforms).
"spin-table" is how the current v8 kernel boots, I am not adding
anything. It is documented in Documentation/arm64/booting.txt.
I have to add the possible wake-up method(s) to the definition of
spin-table here.
Just adding PSCI is tempting but not viable, that would make people
think that's the only allowed method and that's not acceptable.
While defining the process for the introduction of new DT bindings
please consider how we have to deal with legacy bindings designed for
PowerPC that people tend to reuse for ARM ("status" property in cpu
nodes is next, as James highlighted in another thread).
We are doing that in a case by case fashion and that's becoming a nightmare.
Thank you !
Lorenzo
^ permalink raw reply [flat|nested] 64+ messages in thread
* [RFC PATCH v4 03/18] Documentation: devicetree: arm: cpus/cpu nodes bindings updates
@ 2013-07-16 9:45 ` Lorenzo Pieralisi
0 siblings, 0 replies; 64+ messages in thread
From: Lorenzo Pieralisi @ 2013-07-16 9:45 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jul 15, 2013 at 07:50:46PM +0100, Rob Herring wrote:
> On 07/15/2013 04:34 AM, Lorenzo Pieralisi wrote:
> > On Fri, Jul 12, 2013 at 03:47:17PM +0100, Rob Herring wrote:
> >> On Fri, May 17, 2013 at 10:20 AM, Lorenzo Pieralisi
> >> <lorenzo.pieralisi@arm.com> wrote:
> >>> In order to extend the current cpu nodes bindings to newer CPUs
> >>> inclusive of AArch64 and to update support for older ARM CPUs this
> >>> patch updates device tree documentation for the cpu nodes bindings.
> >>
> >> Sorry for the long delay on this, but I'm still not happy with the binding here.
> >
> > I had to ask Russell again to drop the bindings patches from the patch
> > system, and this is not acceptable since two months have passed and the
> > entire series was reviewed, acked and partially merged. I will review
> > these bindings again but I would like to understand who should give the final
> > go ahead to get these patches queued for upstreaming, I can't continue
> > updating this stuff forever.
>
> Most of my comments are for 64-bit. So don't blame me that it had to be
> reverted. I said up front I was concerned about this change breaking
> things and it appears it did. New kernels must not require a new DT.
The patches in Russell's tree do not break anything, I asked him to drop
them since, if we change the bindings again, those patches change and have
to be reworked. It was not meant to blame you at all, just saying that
the process to get this stuff in the kernel should be defined properly
and patches reviewed in a timely fashion.
And for legacy reasons the situation related to cpu/cpus node bindings
is a complicated one, there are bindings in the ePAPR, bindings in the
kernel, people are confused and with this set we wanted to draw a
line. For arm64 this is an absolute must.
I disagree with you on the "new kernels must not require a new DT".
That's true if bindings are well defined, not for a mix of legacy ePAPR and
bindings-in-the-kernel.
What's the DT standard for ARM cpu/cpus node ? ePAPR ? In kernel docs ?
A combination thereof ? Things are not clear cut and I do not like that, it
is confusing.
> But yes, this should have been reviewed more quickly. We're working on a
> plan to help address DT binding reviews. We have not enforced that Grant
> and I must ack all bindings, but in this case you certainly need mine
> since I have reviewed it and if you want to me to pull it.
Good, that's all I wanted to know, thanks.
> >>> Main changes:
> >>> - adds 64-bit bindings
> >>> - define usage of #address-cells
> >>> - define 32/64 dts compatibility settings
> >>> - defines behaviour on pre and post v7 uniprocessor systems
> >>> - adds ARM 11MPcore specific reg property definition
> >>>
> >>> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> >>> ---
> >>> Documentation/devicetree/bindings/arm/cpus.txt | 459 ++++++++++++++++++++++---
> >>> 1 file changed, 412 insertions(+), 47 deletions(-)
> >>
> >> [snip]
> >>
> >>> + # On ARM v8 64-bit systems, where the reg property
> >>> + size can be 1 or 2 cells (as defined by cpus node's
> >>> + #address-cells property), this property is
> >>> + required and matches:
> >>> +
> >>> + - On systems running the OS in AArch32:
> >>
> >> The DTS cannot change based on 32-bit or 64-bit OS.
> >
> > "On systems running the OS in AArch32" implies a dependency on the
> > HW execution state. Since the DT is used to configure OSs I thought that
> > could be a valid sentence. Unfortunately this stuff is not C, so I
> > reiterate my point above, before changing it I would like to understand
> > who should say the wording is ok otherwise we could argue forever.
>
> It does configure the OS, but not for 32 vs. 64 bit. That is more of a
> problem for the bootloader to know which mode to boot in and covered
> under something like Documentation/arm/Booting. Booting ARM vs. Thumb
> mode would be similar situation.
>
> Think about how your PC boots and add to that having a DTB as part of
> the firmware shipped with your PC. Then the end user can install a
> 32-bit or 64-bit OS on it. That is the usecase that needs to be
> supported and having different DTB for 32 and 64 bit is totally broken
> and doesn't even help solve that problem.
I will give it more thought, point taken.
> >>> +
> >>> + - cpu-release-addr
> >>> + Usage: required for systems that have an "enable-method"
> >>> + property value of "spin-table".
> >>> + Value type: <prop-encoded-array>
> >>> + Definition:
> >>> + # On ARM v8 64-bit systems must be a two cell
> >>> + property identifying a 64-bit zero-initialised
> >>> + memory location.
> >>
> >> As I mentioned previously, isn't some wake-up method needed? Most
> >> systems will be in wfi or wfe rather than continuously spinning.
> >
> > Mmm...this can become a minefield, wfe, wfi, CPU in reset..this needs some
> > thought.
>
> Yes, it is today and standardizing this is a good thing. Which is what
> PSCI does. So why are you adding the spintable at all? Are you trying to
> set this as the standard for non-PSCI enabled platforms? Why not just
> say v8 boot interface is PSCI. Sure, we'll probably have to deal with
> other methods, but documenting something else here is not going to
> prevent that problem. I don't think a simple spintable would even work
> for any/most current platforms. I'd think we'd want to define something
> that would work for existing platforms (chances are new platforms will
> work like vendors' existing 32-bit platforms).
"spin-table" is how the current v8 kernel boots, I am not adding
anything. It is documented in Documentation/arm64/booting.txt.
I have to add the possible wake-up method(s) to the definition of
spin-table here.
Just adding PSCI is tempting but not viable, that would make people
think that's the only allowed method and that's not acceptable.
While defining the process for the introduction of new DT bindings
please consider how we have to deal with legacy bindings designed for
PowerPC that people tend to reuse for ARM ("status" property in cpu
nodes is next, as James highlighted in another thread).
We are doing that in a case by case fashion and that's becoming a nightmare.
Thank you !
Lorenzo
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [RFC PATCH v4 03/18] Documentation: devicetree: arm: cpus/cpu nodes bindings updates
2013-07-12 14:47 ` Rob Herring
@ 2013-07-16 11:25 ` Dave Martin
-1 siblings, 0 replies; 64+ messages in thread
From: Dave Martin @ 2013-07-16 11:25 UTC (permalink / raw)
To: Rob Herring
Cc: Nicolas Pitre, Jon Medhurst, Dave Martin, Catalin Marinas,
Andrew Lunn, Tony Lindgren, Benjamin Herrenschmidt,
Linus Walleij, Will Deacon, Mark Rutland, Lennert Buytenhek,
Lorenzo Pieralisi, Russell King, Magnus Damm, Viresh Kumar,
Grant Likely, David Brown, Jean-Christophe Plagniol-Villard,
Dinh Nguyen, Arnd Bergmann, Stephen Warren, Sekhar Nori,
devicetree-discuss
On Fri, Jul 12, 2013 at 09:47:17AM -0500, Rob Herring wrote:
> On Fri, May 17, 2013 at 10:20 AM, Lorenzo Pieralisi
> <lorenzo.pieralisi@arm.com> wrote:
> > In order to extend the current cpu nodes bindings to newer CPUs
> > inclusive of AArch64 and to update support for older ARM CPUs this
> > patch updates device tree documentation for the cpu nodes bindings.
>
> Sorry for the long delay on this, but I'm still not happy with the binding here.
>
> > Main changes:
> > - adds 64-bit bindings
> > - define usage of #address-cells
> > - define 32/64 dts compatibility settings
> > - defines behaviour on pre and post v7 uniprocessor systems
> > - adds ARM 11MPcore specific reg property definition
> >
> > Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> > ---
> > Documentation/devicetree/bindings/arm/cpus.txt | 459 ++++++++++++++++++++++---
> > 1 file changed, 412 insertions(+), 47 deletions(-)
>
> [snip]
>
> > + # On ARM v8 64-bit systems, where the reg property
> > + size can be 1 or 2 cells (as defined by cpus node's
> > + #address-cells property), this property is
> > + required and matches:
> > +
> > + - On systems running the OS in AArch32:
>
> The DTS cannot change based on 32-bit or 64-bit OS.
>
> > +
> > + * If the cpus node's #address-cells value is 2:
> > +
> > + The first reg cell must be set to 0.
> > +
> > + The second reg cell bits [23:0] must be set to
> > + bits [23:0] of MPIDR_EL1.
> > +
> > + All other bits in the reg cells must be set to 0.
> > +
> > + * If the cpus node's #address-cells value is 1:
> > +
> > + Bits [23:0] in the reg cell must be set to
> > + bits [23:0] in MPIDR_EL1.
> > +
> > + All other bits in the reg cell must be 0.
> > +
> > + - On systems running the OS in AArch64:
> > +
> > + * If the cpus node's #address-cells value is 2:
> > +
> > + The first reg cell bits [7:0] must be set to
> > + bits [39:32] of MPIDR_EL1.
> > +
> > + The second reg cell bits [23:0] must be set to
> > + bits [23:0] of MPIDR_EL1.
> > +
> > + All other bits in the reg cells must be set to 0.
> > +
> > + * If the cpus node's #address-cells value is 1:
> > +
> > + MPIDR_EL1[63:32] is 0 on all processors in the
> > + system.
>
> Your logic is backwards here. If the MPIDR_EL1[63:32] is 0, then
> #address-cells can be 1. You could say the upper bits are ignored and
> treated as 0. However, you should simplify all this and just mandate
> that #address-cells must be 2 for ARMv8 or more generally must match
> the size of the MPIDR. If we want to boot a 32-bit kernel, then the
> kernel will have to adapt to support this.
I'd support this, opting for a clean split.
Strictly speaking, it should be this:
AArch64-capable hardware: #address-cells = 2
non-AArch64-capable hardware: #address-cells = 1
The only time it is valid to have #address-cells = 1 on AArch64-capable
hardware is in an AArch32 virtual machine (in which case, the DT anyway
describes the VM and not the real hardware).
However, due to the awkwardness of defining precisely what "AArch64-
capable hardware" means in a world containing firmware and hypervisors,
it might be better (if slightly less correct) to go with:
v8 hardware: #address-cells must be 2
<=v7 hardware: #address-cells must be 1
If the firmware boots an AArch32 payload natively on AArch64-capable
v8 hardware, it's the firmware's job to ensure that non-addressable
CPUs are properly quiesced and shut down, otherwise the setup is
pretty broken -- DT can't solve that one, nor can Linux, so we shouldn't
try. Linux just needs to discard the non-addressable CPUs and maybe
print out a warning.
Cheers
---Dave
^ permalink raw reply [flat|nested] 64+ messages in thread
* [RFC PATCH v4 03/18] Documentation: devicetree: arm: cpus/cpu nodes bindings updates
@ 2013-07-16 11:25 ` Dave Martin
0 siblings, 0 replies; 64+ messages in thread
From: Dave Martin @ 2013-07-16 11:25 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jul 12, 2013 at 09:47:17AM -0500, Rob Herring wrote:
> On Fri, May 17, 2013 at 10:20 AM, Lorenzo Pieralisi
> <lorenzo.pieralisi@arm.com> wrote:
> > In order to extend the current cpu nodes bindings to newer CPUs
> > inclusive of AArch64 and to update support for older ARM CPUs this
> > patch updates device tree documentation for the cpu nodes bindings.
>
> Sorry for the long delay on this, but I'm still not happy with the binding here.
>
> > Main changes:
> > - adds 64-bit bindings
> > - define usage of #address-cells
> > - define 32/64 dts compatibility settings
> > - defines behaviour on pre and post v7 uniprocessor systems
> > - adds ARM 11MPcore specific reg property definition
> >
> > Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> > ---
> > Documentation/devicetree/bindings/arm/cpus.txt | 459 ++++++++++++++++++++++---
> > 1 file changed, 412 insertions(+), 47 deletions(-)
>
> [snip]
>
> > + # On ARM v8 64-bit systems, where the reg property
> > + size can be 1 or 2 cells (as defined by cpus node's
> > + #address-cells property), this property is
> > + required and matches:
> > +
> > + - On systems running the OS in AArch32:
>
> The DTS cannot change based on 32-bit or 64-bit OS.
>
> > +
> > + * If the cpus node's #address-cells value is 2:
> > +
> > + The first reg cell must be set to 0.
> > +
> > + The second reg cell bits [23:0] must be set to
> > + bits [23:0] of MPIDR_EL1.
> > +
> > + All other bits in the reg cells must be set to 0.
> > +
> > + * If the cpus node's #address-cells value is 1:
> > +
> > + Bits [23:0] in the reg cell must be set to
> > + bits [23:0] in MPIDR_EL1.
> > +
> > + All other bits in the reg cell must be 0.
> > +
> > + - On systems running the OS in AArch64:
> > +
> > + * If the cpus node's #address-cells value is 2:
> > +
> > + The first reg cell bits [7:0] must be set to
> > + bits [39:32] of MPIDR_EL1.
> > +
> > + The second reg cell bits [23:0] must be set to
> > + bits [23:0] of MPIDR_EL1.
> > +
> > + All other bits in the reg cells must be set to 0.
> > +
> > + * If the cpus node's #address-cells value is 1:
> > +
> > + MPIDR_EL1[63:32] is 0 on all processors in the
> > + system.
>
> Your logic is backwards here. If the MPIDR_EL1[63:32] is 0, then
> #address-cells can be 1. You could say the upper bits are ignored and
> treated as 0. However, you should simplify all this and just mandate
> that #address-cells must be 2 for ARMv8 or more generally must match
> the size of the MPIDR. If we want to boot a 32-bit kernel, then the
> kernel will have to adapt to support this.
I'd support this, opting for a clean split.
Strictly speaking, it should be this:
AArch64-capable hardware: #address-cells = 2
non-AArch64-capable hardware: #address-cells = 1
The only time it is valid to have #address-cells = 1 on AArch64-capable
hardware is in an AArch32 virtual machine (in which case, the DT anyway
describes the VM and not the real hardware).
However, due to the awkwardness of defining precisely what "AArch64-
capable hardware" means in a world containing firmware and hypervisors,
it might be better (if slightly less correct) to go with:
v8 hardware: #address-cells must be 2
<=v7 hardware: #address-cells must be 1
If the firmware boots an AArch32 payload natively on AArch64-capable
v8 hardware, it's the firmware's job to ensure that non-addressable
CPUs are properly quiesced and shut down, otherwise the setup is
pretty broken -- DT can't solve that one, nor can Linux, so we shouldn't
try. Linux just needs to discard the non-addressable CPUs and maybe
print out a warning.
Cheers
---Dave
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [RFC PATCH v4 03/18] Documentation: devicetree: arm: cpus/cpu nodes bindings updates
2013-07-16 9:45 ` Lorenzo Pieralisi
@ 2013-07-17 3:22 ` Rob Herring
-1 siblings, 0 replies; 64+ messages in thread
From: Rob Herring @ 2013-07-17 3:22 UTC (permalink / raw)
To: Lorenzo Pieralisi
Cc: Nicolas Pitre, Jon Medhurst, Catalin Marinas, Andrew Lunn,
Will Deacon, Lennert Buytenhek, Kukjin Kim, Russell King,
Magnus Damm, Viresh Kumar, grant.likely-QSEj5FYQhm4dnm+yROfE0A,
David Brown, Sekhar Nori,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Simon Horman,
Barry Song, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Amit Kucheria, Vinayak Kale
On 07/16/2013 04:45 AM, Lorenzo Pieralisi wrote:
> On Mon, Jul 15, 2013 at 07:50:46PM +0100, Rob Herring wrote:
>> On 07/15/2013 04:34 AM, Lorenzo Pieralisi wrote:
>>> On Fri, Jul 12, 2013 at 03:47:17PM +0100, Rob Herring wrote:
>>>> On Fri, May 17, 2013 at 10:20 AM, Lorenzo Pieralisi
>>>> <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org> wrote:
>>>>> In order to extend the current cpu nodes bindings to newer CPUs
>>>>> inclusive of AArch64 and to update support for older ARM CPUs this
>>>>> patch updates device tree documentation for the cpu nodes bindings.
>>>>
>>>> Sorry for the long delay on this, but I'm still not happy with the binding here.
>>>
>>> I had to ask Russell again to drop the bindings patches from the patch
>>> system, and this is not acceptable since two months have passed and the
>>> entire series was reviewed, acked and partially merged. I will review
>>> these bindings again but I would like to understand who should give the final
>>> go ahead to get these patches queued for upstreaming, I can't continue
>>> updating this stuff forever.
>>
>> Most of my comments are for 64-bit. So don't blame me that it had to be
>> reverted. I said up front I was concerned about this change breaking
>> things and it appears it did. New kernels must not require a new DT.
>
> The patches in Russell's tree do not break anything, I asked him to drop
> them since, if we change the bindings again, those patches change and have
> to be reworked. It was not meant to blame you at all, just saying that
> the process to get this stuff in the kernel should be defined properly
> and patches reviewed in a timely fashion.
>
> And for legacy reasons the situation related to cpu/cpus node bindings
> is a complicated one, there are bindings in the ePAPR, bindings in the
> kernel, people are confused and with this set we wanted to draw a
> line. For arm64 this is an absolute must.
>
> I disagree with you on the "new kernels must not require a new DT".
> That's true if bindings are well defined, not for a mix of legacy ePAPR and
> bindings-in-the-kernel.
Well defined depends on the platform. For purposes of a single cluster
ARM system, the ePAPR was pretty much sufficient for cpu node
description. The initial discussion was whether we even needed cpu nodes
at all.
We're always going to have something new that we did not account for. So
even for well defined bindings, we'll have to make changes/extensions at
some point. It just needs to be years, not months for changes.
> What's the DT standard for ARM cpu/cpus node ? ePAPR ? In kernel docs ?
> A combination thereof ? Things are not clear cut and I do not like that, it
> is confusing.
ePAPR is a guideline, but in the end it is a PowerPC document. In some
cases we can just use what it defines and in others we need to deviate.
In an ideal world, we would create the equivalent for ARM or figure out
how to merge ARM requirements with ePAPR. However, since UEFI and ACPI
are going to solve all our problems, no one seems interested in defining
a more formal document.
To further complicate things, there is also the original OF
specification to follow as well. So I would say all the docs apply and
the order of priority is DT binding docs, ePAPR, OF specs. The DT
binding docs need to be complete enough to avoid confusion.
Rob
^ permalink raw reply [flat|nested] 64+ messages in thread
* [RFC PATCH v4 03/18] Documentation: devicetree: arm: cpus/cpu nodes bindings updates
@ 2013-07-17 3:22 ` Rob Herring
0 siblings, 0 replies; 64+ messages in thread
From: Rob Herring @ 2013-07-17 3:22 UTC (permalink / raw)
To: linux-arm-kernel
On 07/16/2013 04:45 AM, Lorenzo Pieralisi wrote:
> On Mon, Jul 15, 2013 at 07:50:46PM +0100, Rob Herring wrote:
>> On 07/15/2013 04:34 AM, Lorenzo Pieralisi wrote:
>>> On Fri, Jul 12, 2013 at 03:47:17PM +0100, Rob Herring wrote:
>>>> On Fri, May 17, 2013 at 10:20 AM, Lorenzo Pieralisi
>>>> <lorenzo.pieralisi@arm.com> wrote:
>>>>> In order to extend the current cpu nodes bindings to newer CPUs
>>>>> inclusive of AArch64 and to update support for older ARM CPUs this
>>>>> patch updates device tree documentation for the cpu nodes bindings.
>>>>
>>>> Sorry for the long delay on this, but I'm still not happy with the binding here.
>>>
>>> I had to ask Russell again to drop the bindings patches from the patch
>>> system, and this is not acceptable since two months have passed and the
>>> entire series was reviewed, acked and partially merged. I will review
>>> these bindings again but I would like to understand who should give the final
>>> go ahead to get these patches queued for upstreaming, I can't continue
>>> updating this stuff forever.
>>
>> Most of my comments are for 64-bit. So don't blame me that it had to be
>> reverted. I said up front I was concerned about this change breaking
>> things and it appears it did. New kernels must not require a new DT.
>
> The patches in Russell's tree do not break anything, I asked him to drop
> them since, if we change the bindings again, those patches change and have
> to be reworked. It was not meant to blame you at all, just saying that
> the process to get this stuff in the kernel should be defined properly
> and patches reviewed in a timely fashion.
>
> And for legacy reasons the situation related to cpu/cpus node bindings
> is a complicated one, there are bindings in the ePAPR, bindings in the
> kernel, people are confused and with this set we wanted to draw a
> line. For arm64 this is an absolute must.
>
> I disagree with you on the "new kernels must not require a new DT".
> That's true if bindings are well defined, not for a mix of legacy ePAPR and
> bindings-in-the-kernel.
Well defined depends on the platform. For purposes of a single cluster
ARM system, the ePAPR was pretty much sufficient for cpu node
description. The initial discussion was whether we even needed cpu nodes
at all.
We're always going to have something new that we did not account for. So
even for well defined bindings, we'll have to make changes/extensions at
some point. It just needs to be years, not months for changes.
> What's the DT standard for ARM cpu/cpus node ? ePAPR ? In kernel docs ?
> A combination thereof ? Things are not clear cut and I do not like that, it
> is confusing.
ePAPR is a guideline, but in the end it is a PowerPC document. In some
cases we can just use what it defines and in others we need to deviate.
In an ideal world, we would create the equivalent for ARM or figure out
how to merge ARM requirements with ePAPR. However, since UEFI and ACPI
are going to solve all our problems, no one seems interested in defining
a more formal document.
To further complicate things, there is also the original OF
specification to follow as well. So I would say all the docs apply and
the order of priority is DT binding docs, ePAPR, OF specs. The DT
binding docs need to be complete enough to avoid confusion.
Rob
^ permalink raw reply [flat|nested] 64+ messages in thread
end of thread, other threads:[~2013-07-17 3:22 UTC | newest]
Thread overview: 64+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-05-17 15:20 [RFC PATCH v4 00/18] ARM: DT cpu bindings updates Lorenzo Pieralisi
2013-05-17 15:20 ` Lorenzo Pieralisi
2013-05-17 15:20 ` [RFC PATCH v4 03/18] Documentation: devicetree: arm: cpus/cpu nodes " Lorenzo Pieralisi
2013-05-17 15:20 ` Lorenzo Pieralisi
[not found] ` <1368804061-4421-4-git-send-email-lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
2013-05-17 16:07 ` Nicolas Pitre
2013-05-17 16:07 ` Nicolas Pitre
2013-07-12 14:47 ` Rob Herring
2013-07-12 14:47 ` Rob Herring
[not found] ` <CAL_JsqLANi5UoVyRMsa6XoQ+_KnmTQDfTz++shEh-dZ3FQGZaQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2013-07-15 9:34 ` Lorenzo Pieralisi
2013-07-15 9:34 ` Lorenzo Pieralisi
[not found] ` <20130715093406.GC15904-7AyDDHkRsp3ZROr8t4l/smS4ubULX0JqMm0uRHvK7Nw@public.gmane.org>
2013-07-15 18:50 ` Rob Herring
2013-07-15 18:50 ` Rob Herring
[not found] ` <51E44486.7050806-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2013-07-16 9:45 ` Lorenzo Pieralisi
2013-07-16 9:45 ` Lorenzo Pieralisi
[not found] ` <20130716094508.GA28503-7AyDDHkRsp3ZROr8t4l/smS4ubULX0JqMm0uRHvK7Nw@public.gmane.org>
2013-07-17 3:22 ` Rob Herring
2013-07-17 3:22 ` Rob Herring
2013-07-16 11:25 ` Dave Martin
2013-07-16 11:25 ` Dave Martin
[not found] ` <1368804061-4421-1-git-send-email-lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
2013-05-17 15:20 ` [RFC PATCH v4 01/18] ARM: kernel: fix arm_dt_init_cpu_maps() to skip non-cpu nodes Lorenzo Pieralisi
2013-05-17 15:20 ` Lorenzo Pieralisi
[not found] ` <1368804061-4421-2-git-send-email-lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
2013-05-17 15:49 ` Nicolas Pitre
2013-05-17 15:49 ` Nicolas Pitre
2013-05-17 16:31 ` Rob Herring
2013-05-17 16:31 ` Rob Herring
[not found] ` <CAL_JsqLdbbsBeEaUT5BcxjZnbjEiu=qsPsynxCXdgi1J=ejzTg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2013-05-17 17:04 ` Lorenzo Pieralisi
2013-05-17 17:04 ` Lorenzo Pieralisi
2013-05-17 15:20 ` [RFC PATCH v4 02/18] ARM: kernel: fix __cpu_logical_map default initialization Lorenzo Pieralisi
2013-05-17 15:20 ` Lorenzo Pieralisi
[not found] ` <1368804061-4421-3-git-send-email-lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
2013-05-17 15:46 ` Nicolas Pitre
2013-05-17 15:46 ` Nicolas Pitre
2013-05-17 15:20 ` [RFC PATCH v4 04/18] ARM: dts: am33xx: cpus/cpu nodes dts updates Lorenzo Pieralisi
2013-05-17 15:20 ` Lorenzo Pieralisi
2013-05-17 15:20 ` [RFC PATCH v4 05/18] ARM: dts: armada-370-xp: cpus/cpu node " Lorenzo Pieralisi
2013-05-17 15:20 ` Lorenzo Pieralisi
[not found] ` <1368804061-4421-6-git-send-email-lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
2013-05-17 17:16 ` Gregory CLEMENT
2013-05-17 17:16 ` Gregory CLEMENT
2013-05-17 15:20 ` [RFC PATCH v4 06/18] ARM: dts: at91: " Lorenzo Pieralisi
2013-05-17 15:20 ` Lorenzo Pieralisi
2013-05-17 15:20 ` [RFC PATCH v4 07/18] ARM: dts: exynos5440: cpus/cpu nodes " Lorenzo Pieralisi
2013-05-17 15:20 ` Lorenzo Pieralisi
2013-05-17 15:20 ` [RFC PATCH v4 08/18] ARM: dts: imx: " Lorenzo Pieralisi
2013-05-17 15:20 ` Lorenzo Pieralisi
2013-05-17 15:20 ` [RFC PATCH v4 09/18] ARM: dts: lpc32xx: " Lorenzo Pieralisi
2013-05-17 15:20 ` Lorenzo Pieralisi
2013-05-17 15:20 ` [RFC PATCH v4 10/18] ARM: dts: omap: " Lorenzo Pieralisi
2013-05-17 15:20 ` Lorenzo Pieralisi
2013-05-17 15:20 ` [RFC PATCH v4 11/18] ARM: dts: picoxcell: " Lorenzo Pieralisi
2013-05-17 15:20 ` Lorenzo Pieralisi
2013-05-17 15:20 ` [RFC PATCH v4 12/18] ARM: dts: prima2: cpus/cpu node " Lorenzo Pieralisi
2013-05-17 15:20 ` Lorenzo Pieralisi
2013-05-17 15:20 ` [RFC PATCH v4 13/18] ARM: dts: pxa2xx: cpus/cpu nodes " Lorenzo Pieralisi
2013-05-17 15:20 ` Lorenzo Pieralisi
2013-05-17 15:20 ` [RFC PATCH v4 14/18] ARM: dts: r8a7740: " Lorenzo Pieralisi
2013-05-17 15:20 ` Lorenzo Pieralisi
2013-05-17 15:20 ` [RFC PATCH v4 15/18] ARM: dts: sh7372: " Lorenzo Pieralisi
2013-05-17 15:20 ` Lorenzo Pieralisi
2013-05-17 15:20 ` [RFC PATCH v4 16/18] ARM: dts: spear: " Lorenzo Pieralisi
2013-05-17 15:20 ` Lorenzo Pieralisi
2013-05-17 15:21 ` [RFC PATCH v4 17/18] ARM: dts: sunxi: " Lorenzo Pieralisi
2013-05-17 15:21 ` Lorenzo Pieralisi
2013-05-17 15:21 ` [RFC PATCH v4 18/18] ARM: DT: kernel: DT cpus/cpu node bindings update Lorenzo Pieralisi
2013-05-17 15:21 ` Lorenzo Pieralisi
[not found] ` <1368804061-4421-19-git-send-email-lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
2013-05-17 16:22 ` Nicolas Pitre
2013-05-17 16:22 ` Nicolas Pitre
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.