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* [PATCH 00/31] shared pch display pll rework
@ 2013-06-05 11:34 Daniel Vetter
  2013-06-05 11:34 ` [PATCH 01/31] drm/i915: fix up pch pll handling in ->mode_set Daniel Vetter
                   ` (31 more replies)
  0 siblings, 32 replies; 84+ messages in thread
From: Daniel Vetter @ 2013-06-05 11:34 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

Hi all,

So originally I've only set out to create a more paranoid version of Jesse's hw
state reconstruction for the shared pch display plls. But then I've noticed that
the current code still smells broken (very first patch) and decided that we
should abstract the refcounting and hw state readout/compare logic from the
platform details a bit, so that we can reuse it on e.g. Haswell.

Since it's tricky code, it's split up in a lot of rather small patches itching
forward towards the goal. In the end we have
- new vfuncs to hide the platform details for ->enable/disable/mode_set of a
  shared display pll.
- hw state readout and compare for both the display plls alone and their
  use by display pipes.

Not yet done is:
- Moving the pll selection logic into the compute config stage of the modeset
  sequence. So atomic modeset still needs more work, we only notice the lack of
  a suitable dpll in the mode_set stage.
- Seperating the platform logic to pick a suitable from the get refcounting.
  This might be needed for Haswell (but I'm not sure yet how to best map the
  different Haswell plls).
- Convert Haswell ddi pll code over to this so that fastboot/atomic modeset can
  work there, too.

Series contains a few parts:

- patch 1: Fixup modeset on a shared dpll - we could change the dpll config if
  it's in use by another pipe.
- patches 2-7: Prep work, improved assert checks and moving the current state
  into the pipe_config (but not yet taking advantage of that at all).
- patches 8-13: Refactor the shared dpll code and add ->enable/disable hooks.
- patches 14-17: Basic (i.e. on/off) state readout for shared dplls + a bit of
  follow-up cleanup.
- patches 18-22: hw state readout for the full register state and follow-up
  cleanups taking advantage of that. By this point fastboot has enough state
  recovered to correctly take over pch dplls from the bios. While doing so I've
  also aligned the ilk+ pch pll enable sequenc with the i9xx dpll enable
  sequence - too much cargo cult seems to have added a bit of cruft on the ilk
  paths.
- patches 23-29: Since I've banged my head badly against the lvds enabling
  sequence while developing the above I've figured I'll clean up that mess (and
  bake the hard-learned lessons into code with asserts). It also fixes the pll
  enabling sequence on vlv/i9xx, so at the end we no longer call an ->enable
  function anywhere from ->mode_set!
- patches 30-31: Two afterthoughts on top ;-)

Comments, flames, testing and review highly welcome.

Cheers, Daniel

Daniel Vetter (31):
  drm/i915: fix up pch pll handling in ->mode_set
  drm/i915: conditionally disable pch resources in ilk_crtc_disable
  drm/i915: lock down pch pll accouting some more
  drm/i915: s/pch_pll/shared_dpll/
  drm/i915: switch crtc->shared_dpll from a pointer to an enum
  drm/i915: move shared_dpll into the pipe config
  drm/i915: refactor PCH_DPLL_SEL #defines
  drm/i915: hw state readout for shared pch plls
  drm/i915: consolidate ->num_shared_dplls assignement
  drm/i915: metadata for shared dplls
  drm/i915: scrap register address storage
  drm/i915: enable/disable hooks for shared dplls
  drm/i915: drop crtc checking from assert_shared_dpll
  drm/i915: display pll hw state readout and checking
  drm/i915: extract readout_hw_state from setup_hw_state
  drm/i915: split up intel_modeset_check_state
  drm/i915: WARN on lack of shared dpll
  drm/i915: hw state readout and cross-checking for shared dplls
  drm/i915: fix up pch pll enabling for pixel multipliers
  drm/i915: simplify the reduced clock handling for pch plls
  drm/i915: consolidate pch pll enable sequence
  drm/i915: use sw tracked state to select shared dplls
  drm/i915: duplicate intel_enable_pll into i9xx and vlv versions
  drm/i915: asserts for lvds pre_enable
  drm/i915: move encoder pre enable hooks togther on ilk+
  drm/i915: hw state readout for i9xx dplls
  drm/i915: move i9xx dpll enabling into crtc enable function
  drm/i915: s/pre_pll/pre/ on the lvds port enable function
  drm/i915: clean up vlv ->pre_pll_enable and pll enable sequence
  drm/i915: Fix up cpt pixel multiplier enable sequence
  drm/i915: clear DPLL reg when disabling i9xx dplls

 drivers/gpu/drm/i915/i915_drv.c      |   7 -
 drivers/gpu/drm/i915/i915_drv.h      |  42 +-
 drivers/gpu/drm/i915/i915_reg.h      |  18 +-
 drivers/gpu/drm/i915/i915_ums.c      |   2 +-
 drivers/gpu/drm/i915/intel_display.c | 853 ++++++++++++++++++++---------------
 drivers/gpu/drm/i915/intel_drv.h     |  24 +-
 drivers/gpu/drm/i915/intel_lvds.c    |  21 +-
 7 files changed, 573 insertions(+), 394 deletions(-)

-- 
1.7.11.7

^ permalink raw reply	[flat|nested] 84+ messages in thread

* [PATCH 01/31] drm/i915: fix up pch pll handling in ->mode_set
  2013-06-05 11:34 [PATCH 00/31] shared pch display pll rework Daniel Vetter
@ 2013-06-05 11:34 ` Daniel Vetter
  2013-06-05 11:34 ` [PATCH 02/31] drm/i915: conditionally disable pch resources in ilk_crtc_disable Daniel Vetter
                   ` (30 subsequent siblings)
  31 siblings, 0 replies; 84+ messages in thread
From: Daniel Vetter @ 2013-06-05 11:34 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

We ->mode_set is called we can't just blindly reuse an existing pll
since that might be shared with a different, still active pch output.

v2: Only update the pll settings when the pch pll is know to be
unused, otherwise we can wreak havoc with a running pipe. Which in the
case of DP will likely result in a black screen due to loss of link
lock.

v3: Tighten up the asserts a bit more, especially make sure that the
pch pll is still enabled when we try to disable it. This would have
caught the bug fixed in this patch.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 35 +++++++++++++++++++----------------
 1 file changed, 19 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f29063b..3bdb695 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1397,7 +1397,8 @@ static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
 	/* PCH refclock must be enabled first */
 	assert_pch_refclk_enabled(dev_priv);
 
-	if (pll->active++ && pll->on) {
+	if (pll->active++) {
+		WARN_ON(!pll->on);
 		assert_pch_pll_enabled(dev_priv, pll, NULL);
 		return;
 	}
@@ -1438,10 +1439,9 @@ static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
 		return;
 	}
 
-	if (--pll->active) {
-		assert_pch_pll_enabled(dev_priv, pll, NULL);
+	assert_pch_pll_enabled(dev_priv, pll, NULL);
+	if (--pll->active)
 		return;
-	}
 
 	DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
 
@@ -3048,9 +3048,9 @@ static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u3
 
 	pll = intel_crtc->pch_pll;
 	if (pll) {
-		DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
+		DRM_DEBUG_KMS("CRTC:%d dropping existing PCH PLL %x\n",
 			      intel_crtc->base.base.id, pll->pll_reg);
-		goto prepare;
+		intel_put_pch_pll(intel_crtc);
 	}
 
 	if (HAS_PCH_IBX(dev_priv->dev)) {
@@ -3095,19 +3095,22 @@ static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u3
 
 found:
 	intel_crtc->pch_pll = pll;
-	pll->refcount++;
 	DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
-prepare: /* separate function? */
-	DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
+	if (pll->active == 0) {
+		DRM_DEBUG_DRIVER("setting up pll %d\n", i);
+		WARN_ON(pll->on);
+		assert_pch_pll_disabled(dev_priv, pll, NULL);
 
-	/* Wait for the clocks to stabilize before rewriting the regs */
-	I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
-	POSTING_READ(pll->pll_reg);
-	udelay(150);
+		/* Wait for the clocks to stabilize before rewriting the regs */
+		I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
+		POSTING_READ(pll->pll_reg);
+		udelay(150);
+
+		I915_WRITE(pll->fp0_reg, fp);
+		I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
+	}
+	pll->refcount++;
 
-	I915_WRITE(pll->fp0_reg, fp);
-	I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
-	pll->on = false;
 	return pll;
 }
 
-- 
1.7.11.7

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* [PATCH 02/31] drm/i915: conditionally disable pch resources in ilk_crtc_disable
  2013-06-05 11:34 [PATCH 00/31] shared pch display pll rework Daniel Vetter
  2013-06-05 11:34 ` [PATCH 01/31] drm/i915: fix up pch pll handling in ->mode_set Daniel Vetter
@ 2013-06-05 11:34 ` Daniel Vetter
  2013-06-05 11:34 ` [PATCH 03/31] drm/i915: lock down pch pll accouting some more Daniel Vetter
                   ` (29 subsequent siblings)
  31 siblings, 0 replies; 84+ messages in thread
From: Daniel Vetter @ 2013-06-05 11:34 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

Simlar to how disable already works on haswell. This is possible
since we now carefully track the pch state in the pipe config.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 69 +++++++++++++++++++-----------------
 1 file changed, 37 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3bdb695..56fb6ed 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3380,7 +3380,9 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
 	if (dev_priv->cfb_plane == plane)
 		intel_disable_fbc(dev);
 
-	intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
+	if (intel_crtc->config.has_pch_encoder)
+		intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
+
 	intel_disable_pipe(dev_priv, pipe);
 
 	ironlake_pfit_disable(intel_crtc);
@@ -3389,42 +3391,45 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
 		if (encoder->post_disable)
 			encoder->post_disable(encoder);
 
-	ironlake_fdi_disable(crtc);
+	if (intel_crtc->config.has_pch_encoder) {
+		ironlake_fdi_disable(crtc);
 
-	ironlake_disable_pch_transcoder(dev_priv, pipe);
-	intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
+		ironlake_disable_pch_transcoder(dev_priv, pipe);
+		intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
 
-	if (HAS_PCH_CPT(dev)) {
-		/* disable TRANS_DP_CTL */
-		reg = TRANS_DP_CTL(pipe);
-		temp = I915_READ(reg);
-		temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
-		temp |= TRANS_DP_PORT_SEL_NONE;
-		I915_WRITE(reg, temp);
-
-		/* disable DPLL_SEL */
-		temp = I915_READ(PCH_DPLL_SEL);
-		switch (pipe) {
-		case 0:
-			temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
-			break;
-		case 1:
-			temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
-			break;
-		case 2:
-			/* C shares PLL A or B */
-			temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
-			break;
-		default:
-			BUG(); /* wtf */
+		if (HAS_PCH_CPT(dev)) {
+			/* disable TRANS_DP_CTL */
+			reg = TRANS_DP_CTL(pipe);
+			temp = I915_READ(reg);
+			temp &= ~(TRANS_DP_OUTPUT_ENABLE |
+				  TRANS_DP_PORT_SEL_MASK);
+			temp |= TRANS_DP_PORT_SEL_NONE;
+			I915_WRITE(reg, temp);
+
+			/* disable DPLL_SEL */
+			temp = I915_READ(PCH_DPLL_SEL);
+			switch (pipe) {
+			case 0:
+				temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
+				break;
+			case 1:
+				temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
+				break;
+			case 2:
+				/* C shares PLL A or B */
+				temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
+				break;
+			default:
+				BUG(); /* wtf */
+			}
+			I915_WRITE(PCH_DPLL_SEL, temp);
 		}
-		I915_WRITE(PCH_DPLL_SEL, temp);
-	}
 
-	/* disable PCH DPLL */
-	intel_disable_pch_pll(intel_crtc);
+		/* disable PCH DPLL */
+		intel_disable_pch_pll(intel_crtc);
 
-	ironlake_fdi_pll_disable(intel_crtc);
+		ironlake_fdi_pll_disable(intel_crtc);
+	}
 
 	intel_crtc->active = false;
 	intel_update_watermarks(dev);
-- 
1.7.11.7

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* [PATCH 03/31] drm/i915: lock down pch pll accouting some more
  2013-06-05 11:34 [PATCH 00/31] shared pch display pll rework Daniel Vetter
  2013-06-05 11:34 ` [PATCH 01/31] drm/i915: fix up pch pll handling in ->mode_set Daniel Vetter
  2013-06-05 11:34 ` [PATCH 02/31] drm/i915: conditionally disable pch resources in ilk_crtc_disable Daniel Vetter
@ 2013-06-05 11:34 ` Daniel Vetter
  2013-06-07 16:32   ` Ville Syrjälä
  2013-06-05 11:34 ` [PATCH 04/31] drm/i915: s/pch_pll/shared_dpll/ Daniel Vetter
                   ` (28 subsequent siblings)
  31 siblings, 1 reply; 84+ messages in thread
From: Daniel Vetter @ 2013-06-05 11:34 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

Before I start to make a complete mess out of this, crank up
the paranoia level a bit.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 56fb6ed..39e977f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1440,6 +1440,7 @@ static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
 	}
 
 	assert_pch_pll_enabled(dev_priv, pll, NULL);
+	WARN_ON(!pll->on);
 	if (--pll->active)
 		return;
 
@@ -3031,12 +3032,18 @@ static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
 	if (pll == NULL)
 		return;
 
+	WARN_ON(!intel_crtc->config.has_pch_encoder);
+
 	if (pll->refcount == 0) {
 		WARN(1, "bad PCH PLL refcount\n");
 		return;
 	}
 
-	--pll->refcount;
+	if (--pll->refcount == 0) {
+		WARN_ON(pll->on);
+		WARN_ON(pll->active);
+	}
+
 	intel_crtc->pch_pll = NULL;
 }
 
-- 
1.7.11.7

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* [PATCH 04/31] drm/i915: s/pch_pll/shared_dpll/
  2013-06-05 11:34 [PATCH 00/31] shared pch display pll rework Daniel Vetter
                   ` (2 preceding siblings ...)
  2013-06-05 11:34 ` [PATCH 03/31] drm/i915: lock down pch pll accouting some more Daniel Vetter
@ 2013-06-05 11:34 ` Daniel Vetter
  2013-06-05 11:34 ` [PATCH 05/31] drm/i915: switch crtc->shared_dpll from a pointer to an enum Daniel Vetter
                   ` (27 subsequent siblings)
  31 siblings, 0 replies; 84+ messages in thread
From: Daniel Vetter @ 2013-06-05 11:34 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

For fastboot we need some support to read out the sharing state of
plls, at least for platforms where they can be shared (or freely
assigned at least). Now for ivb we already have pretty extensive
infrastructure for tracking pch plls, and it took us an aweful lot of
tries to get that remotely right. Note that hsw could also share plls,
but even now they're already freely assignable. So we need this on
more than just ivb.

So on top of the usual fastboot fun pll sharing seems to be an
additional step up in fragility. Hence a common infrastructure for all
shared/freely assignable display plls seems to be in order.

The plan is to have a bit of dpll hw state readout code, which can be
used individually, but also to fill in the pipe config. The hw state
cross check code will then use that information to make sure that
after every modeset every pipe still is connected to a pll which still
has the correct configuration - a lot of the pch pll sharing bugs
where due to incorrect sharing.

We start this endeavour with a simple s/pch_pll/shared_dpll/ rename
job.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_drv.c      |  14 ++---
 drivers/gpu/drm/i915/i915_drv.h      |   6 +-
 drivers/gpu/drm/i915/intel_display.c | 112 +++++++++++++++++------------------
 drivers/gpu/drm/i915/intel_drv.h     |   2 +-
 4 files changed, 67 insertions(+), 67 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 59ff745..0672f34 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -457,7 +457,7 @@ void intel_detect_pch(struct drm_device *dev)
 	 */
 	if (INTEL_INFO(dev)->num_pipes == 0) {
 		dev_priv->pch_type = PCH_NOP;
-		dev_priv->num_pch_pll = 0;
+		dev_priv->num_shared_dpll = 0;
 		return;
 	}
 
@@ -476,34 +476,34 @@ void intel_detect_pch(struct drm_device *dev)
 
 			if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_IBX;
-				dev_priv->num_pch_pll = 2;
+				dev_priv->num_shared_dpll = 2;
 				DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 				WARN_ON(!IS_GEN5(dev));
 			} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_CPT;
-				dev_priv->num_pch_pll = 2;
+				dev_priv->num_shared_dpll = 2;
 				DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 				WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 			} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 				/* PantherPoint is CPT compatible */
 				dev_priv->pch_type = PCH_CPT;
-				dev_priv->num_pch_pll = 2;
+				dev_priv->num_shared_dpll = 2;
 				DRM_DEBUG_KMS("Found PatherPoint PCH\n");
 				WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 			} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_LPT;
-				dev_priv->num_pch_pll = 0;
+				dev_priv->num_shared_dpll = 0;
 				DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 				WARN_ON(!IS_HASWELL(dev));
 				WARN_ON(IS_ULT(dev));
 			} else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_LPT;
-				dev_priv->num_pch_pll = 0;
+				dev_priv->num_shared_dpll = 0;
 				DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 				WARN_ON(!IS_HASWELL(dev));
 				WARN_ON(!IS_ULT(dev));
 			}
-			BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
+			BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
 		}
 		pci_dev_put(pch);
 	}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2cdbf9ca..f41f42f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -132,7 +132,7 @@ enum hpd_pin {
 	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
 		if ((intel_encoder)->base.crtc == (__crtc))
 
-struct intel_pch_pll {
+struct intel_shared_dpll {
 	int refcount; /* count of number of CRTCs sharing this PLL */
 	int active; /* count of number of active CRTCs (i.e. DPMS on) */
 	bool on; /* is the PLL actually active? Disabled during modeset */
@@ -1017,7 +1017,6 @@ typedef struct drm_i915_private {
 	u32 hpd_event_bits;
 	struct timer_list hotplug_reenable_timer;
 
-	int num_pch_pll;
 	int num_plane;
 
 	unsigned long cfb_size;
@@ -1078,7 +1077,8 @@ typedef struct drm_i915_private {
 	struct drm_crtc *pipe_to_crtc_mapping[3];
 	wait_queue_head_t pending_flip_queue;
 
-	struct intel_pch_pll pch_plls[I915_NUM_PLLS];
+	int num_shared_dpll;
+	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
 	struct intel_ddi_plls ddi_plls;
 
 	/* Reclocking support */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 39e977f..daf12b5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -892,10 +892,10 @@ static void assert_pll(struct drm_i915_private *dev_priv,
 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 
 /* For ILK+ */
-static void assert_pch_pll(struct drm_i915_private *dev_priv,
-			   struct intel_pch_pll *pll,
-			   struct intel_crtc *crtc,
-			   bool state)
+static void assert_shared_dpll(struct drm_i915_private *dev_priv,
+			       struct intel_shared_dpll *pll,
+			       struct intel_crtc *crtc,
+			       bool state)
 {
 	u32 val;
 	bool cur_state;
@@ -934,8 +934,8 @@ static void assert_pch_pll(struct drm_i915_private *dev_priv,
 		}
 	}
 }
-#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
-#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
+#define assert_shared_dpll_enabled(d, p, c) assert_shared_dpll(d, p, c, true)
+#define assert_shared_dpll_disabled(d, p, c) assert_shared_dpll(d, p, c, false)
 
 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 			  enum pipe pipe, bool state)
@@ -1367,23 +1367,23 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
 }
 
 /**
- * ironlake_enable_pch_pll - enable PCH PLL
+ * ironlake_enable_shared_dpll - enable PCH PLL
  * @dev_priv: i915 private structure
  * @pipe: pipe PLL to enable
  *
  * The PCH PLL needs to be enabled before the PCH transcoder, since it
  * drives the transcoder clock.
  */
-static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
+static void ironlake_enable_shared_dpll(struct intel_crtc *intel_crtc)
 {
 	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
-	struct intel_pch_pll *pll;
+	struct intel_shared_dpll *pll;
 	int reg;
 	u32 val;
 
 	/* PCH PLLs only available on ILK, SNB and IVB */
 	BUG_ON(dev_priv->info->gen < 5);
-	pll = intel_crtc->pch_pll;
+	pll = intel_crtc->shared_dpll;
 	if (pll == NULL)
 		return;
 
@@ -1399,7 +1399,7 @@ static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
 
 	if (pll->active++) {
 		WARN_ON(!pll->on);
-		assert_pch_pll_enabled(dev_priv, pll, NULL);
+		assert_shared_dpll_enabled(dev_priv, pll, NULL);
 		return;
 	}
 
@@ -1415,10 +1415,10 @@ static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
 	pll->on = true;
 }
 
-static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
+static void intel_disable_shared_dpll(struct intel_crtc *intel_crtc)
 {
 	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
-	struct intel_pch_pll *pll = intel_crtc->pch_pll;
+	struct intel_shared_dpll *pll = intel_crtc->shared_dpll;
 	int reg;
 	u32 val;
 
@@ -1435,11 +1435,11 @@ static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
 		      intel_crtc->base.base.id);
 
 	if (WARN_ON(pll->active == 0)) {
-		assert_pch_pll_disabled(dev_priv, pll, NULL);
+		assert_shared_dpll_disabled(dev_priv, pll, NULL);
 		return;
 	}
 
-	assert_pch_pll_enabled(dev_priv, pll, NULL);
+	assert_shared_dpll_enabled(dev_priv, pll, NULL);
 	WARN_ON(!pll->on);
 	if (--pll->active)
 		return;
@@ -1470,9 +1470,9 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
 	BUG_ON(dev_priv->info->gen < 5);
 
 	/* Make sure PCH DPLL is enabled */
-	assert_pch_pll_enabled(dev_priv,
-			       to_intel_crtc(crtc)->pch_pll,
-			       to_intel_crtc(crtc));
+	assert_shared_dpll_enabled(dev_priv,
+				   to_intel_crtc(crtc)->shared_dpll,
+				   to_intel_crtc(crtc));
 
 	/* FDI must be feeding us bits for PCH ports */
 	assert_fdi_tx_enabled(dev_priv, pipe);
@@ -2932,10 +2932,10 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
 	 * transcoder, and we actually should do this to not upset any PCH
 	 * transcoder that already use the clock when we share it.
 	 *
-	 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
-	 * unconditionally resets the pll - we need that to have the right LVDS
-	 * enable sequence. */
-	ironlake_enable_pch_pll(intel_crtc);
+	 * Note that enable_shared_dpll tries to do the right thing, but
+	 * get_shared_dpll unconditionally resets the pll - we need that to have
+	 * the right LVDS enable sequence. */
+	ironlake_enable_shared_dpll(intel_crtc);
 
 	if (HAS_PCH_CPT(dev)) {
 		u32 sel;
@@ -2956,7 +2956,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
 			sel = TRANSC_DPLLB_SEL;
 			break;
 		}
-		if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
+		if (intel_crtc->shared_dpll->pll_reg == _PCH_DPLL_B)
 			temp |= sel;
 		else
 			temp &= ~sel;
@@ -3025,9 +3025,9 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
 	lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
 }
 
-static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
+static void intel_put_shared_dpll(struct intel_crtc *intel_crtc)
 {
-	struct intel_pch_pll *pll = intel_crtc->pch_pll;
+	struct intel_shared_dpll *pll = intel_crtc->shared_dpll;
 
 	if (pll == NULL)
 		return;
@@ -3044,26 +3044,26 @@ static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
 		WARN_ON(pll->active);
 	}
 
-	intel_crtc->pch_pll = NULL;
+	intel_crtc->shared_dpll = NULL;
 }
 
-static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
+static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
 {
 	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
-	struct intel_pch_pll *pll;
+	struct intel_shared_dpll *pll;
 	int i;
 
-	pll = intel_crtc->pch_pll;
+	pll = intel_crtc->shared_dpll;
 	if (pll) {
 		DRM_DEBUG_KMS("CRTC:%d dropping existing PCH PLL %x\n",
 			      intel_crtc->base.base.id, pll->pll_reg);
-		intel_put_pch_pll(intel_crtc);
+		intel_put_shared_dpll(intel_crtc);
 	}
 
 	if (HAS_PCH_IBX(dev_priv->dev)) {
 		/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
 		i = intel_crtc->pipe;
-		pll = &dev_priv->pch_plls[i];
+		pll = &dev_priv->shared_dplls[i];
 
 		DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
 			      intel_crtc->base.base.id, pll->pll_reg);
@@ -3071,8 +3071,8 @@ static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u3
 		goto found;
 	}
 
-	for (i = 0; i < dev_priv->num_pch_pll; i++) {
-		pll = &dev_priv->pch_plls[i];
+	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
+		pll = &dev_priv->shared_dplls[i];
 
 		/* Only want to check enabled timings first */
 		if (pll->refcount == 0)
@@ -3089,8 +3089,8 @@ static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u3
 	}
 
 	/* Ok no matching timings, maybe there's a free one? */
-	for (i = 0; i < dev_priv->num_pch_pll; i++) {
-		pll = &dev_priv->pch_plls[i];
+	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
+		pll = &dev_priv->shared_dplls[i];
 		if (pll->refcount == 0) {
 			DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
 				      intel_crtc->base.base.id, pll->pll_reg);
@@ -3101,12 +3101,12 @@ static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u3
 	return NULL;
 
 found:
-	intel_crtc->pch_pll = pll;
+	intel_crtc->shared_dpll = pll;
 	DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
 	if (pll->active == 0) {
 		DRM_DEBUG_DRIVER("setting up pll %d\n", i);
 		WARN_ON(pll->on);
-		assert_pch_pll_disabled(dev_priv, pll, NULL);
+		assert_shared_dpll_disabled(dev_priv, pll, NULL);
 
 		/* Wait for the clocks to stabilize before rewriting the regs */
 		I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
@@ -3433,7 +3433,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
 		}
 
 		/* disable PCH DPLL */
-		intel_disable_pch_pll(intel_crtc);
+		intel_disable_shared_dpll(intel_crtc);
 
 		ironlake_fdi_pll_disable(intel_crtc);
 	}
@@ -3505,7 +3505,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
 static void ironlake_crtc_off(struct drm_crtc *crtc)
 {
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	intel_put_pch_pll(intel_crtc);
+	intel_put_shared_dpll(intel_crtc);
 }
 
 static void haswell_crtc_off(struct drm_crtc *crtc)
@@ -5705,7 +5705,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 
 	/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
 	if (intel_crtc->config.has_pch_encoder) {
-		struct intel_pch_pll *pll;
+		struct intel_shared_dpll *pll;
 
 		fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
 		if (has_reduced_clock)
@@ -5715,14 +5715,14 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 					     &fp, &reduced_clock,
 					     has_reduced_clock ? &fp2 : NULL);
 
-		pll = intel_get_pch_pll(intel_crtc, dpll, fp);
+		pll = intel_get_shared_dpll(intel_crtc, dpll, fp);
 		if (pll == NULL) {
 			DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
 					 pipe_name(pipe));
 			return -EINVAL;
 		}
 	} else
-		intel_put_pch_pll(intel_crtc);
+		intel_put_shared_dpll(intel_crtc);
 
 	if (intel_crtc->config.has_dp_encoder)
 		intel_dp_set_m_n(intel_crtc);
@@ -5731,11 +5731,11 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 		if (encoder->pre_pll_enable)
 			encoder->pre_pll_enable(encoder);
 
-	if (intel_crtc->pch_pll) {
-		I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
+	if (intel_crtc->shared_dpll) {
+		I915_WRITE(intel_crtc->shared_dpll->pll_reg, dpll);
 
 		/* Wait for the clocks to stabilize. */
-		POSTING_READ(intel_crtc->pch_pll->pll_reg);
+		POSTING_READ(intel_crtc->shared_dpll->pll_reg);
 		udelay(150);
 
 		/* The pixel multiplier can only be updated once the
@@ -5743,16 +5743,16 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 		 *
 		 * So write it again.
 		 */
-		I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
+		I915_WRITE(intel_crtc->shared_dpll->pll_reg, dpll);
 	}
 
 	intel_crtc->lowfreq_avail = false;
-	if (intel_crtc->pch_pll) {
+	if (intel_crtc->shared_dpll) {
 		if (is_lvds && has_reduced_clock && i915_powersave) {
-			I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
+			I915_WRITE(intel_crtc->shared_dpll->fp1_reg, fp2);
 			intel_crtc->lowfreq_avail = true;
 		} else {
-			I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
+			I915_WRITE(intel_crtc->shared_dpll->fp1_reg, fp);
 		}
 	}
 
@@ -8659,20 +8659,20 @@ static void intel_cpu_pll_init(struct drm_device *dev)
 		intel_ddi_pll_init(dev);
 }
 
-static void intel_pch_pll_init(struct drm_device *dev)
+static void intel_shared_dpll_init(struct drm_device *dev)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	int i;
 
-	if (dev_priv->num_pch_pll == 0) {
+	if (dev_priv->num_shared_dpll == 0) {
 		DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
 		return;
 	}
 
-	for (i = 0; i < dev_priv->num_pch_pll; i++) {
-		dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
-		dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
-		dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
+	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
+		dev_priv->shared_dplls[i].pll_reg = _PCH_DPLL(i);
+		dev_priv->shared_dplls[i].fp0_reg = _PCH_FP0(i);
+		dev_priv->shared_dplls[i].fp1_reg = _PCH_FP1(i);
 	}
 }
 
@@ -9364,7 +9364,7 @@ void intel_modeset_init(struct drm_device *dev)
 	}
 
 	intel_cpu_pll_init(dev);
-	intel_pch_pll_init(dev);
+	intel_shared_dpll_init(dev);
 
 	/* Just disable it once at startup */
 	i915_disable_vga(dev);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index eae3dbc..163bee9 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -306,7 +306,7 @@ struct intel_crtc {
 	struct intel_crtc_config config;
 
 	/* We can share PLLs across outputs if the timings match */
-	struct intel_pch_pll *pch_pll;
+	struct intel_shared_dpll *shared_dpll;
 	uint32_t ddi_pll_sel;
 
 	/* reset counter value when the last flip was submitted */
-- 
1.7.11.7

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* [PATCH 05/31] drm/i915: switch crtc->shared_dpll from a pointer to an enum
  2013-06-05 11:34 [PATCH 00/31] shared pch display pll rework Daniel Vetter
                   ` (3 preceding siblings ...)
  2013-06-05 11:34 ` [PATCH 04/31] drm/i915: s/pch_pll/shared_dpll/ Daniel Vetter
@ 2013-06-05 11:34 ` Daniel Vetter
  2013-06-07 16:48   ` Ville Syrjälä
  2013-06-05 11:34 ` [PATCH 06/31] drm/i915: move shared_dpll into the pipe config Daniel Vetter
                   ` (26 subsequent siblings)
  31 siblings, 1 reply; 84+ messages in thread
From: Daniel Vetter @ 2013-06-05 11:34 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

Dealing with discrete enum values is simpler for hw state readout and
pipe config computations than pointers - having neat names instead of
chasing pointers should look better in the code.

This isn't a that good reason for pch plls, but on haswell we actually
have 3 different types of plls: WRPLL, SPLL and the DP clocks. Having
explicit names should help there.

Since this also adds the intel_crtc_to_shared_dpll helper to further
abstract away the crtc -> dpll relationship this will also help to
make the next patch simpler, which moves the shared dpll into the pipe
configuration.

Also note that for uniformity we have two special dpll ids: NONE for
pipes which need a shared pll but don't have one (yet) and private for
when there's a non-shared pll (e.g. per-pipe or per-port pll).

I've thought whether we should also add a 2nd enum for the type of the
pll we want (for really generic pll selection code) but thrown that
idea out again - likely there's too much platform craziness going on
to be able to share the pll selection logic much.

Since this touched all the shared_pll functions a bit I've also done
an s/intel_crtc/crtc/ replacement on a few of them.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_drv.h      |  8 ++++
 drivers/gpu/drm/i915/intel_display.c | 92 ++++++++++++++++++++----------------
 drivers/gpu/drm/i915/intel_drv.h     |  2 +-
 3 files changed, 60 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f41f42f..ca3cb3b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -140,6 +140,14 @@ struct intel_shared_dpll {
 	int fp0_reg;
 	int fp1_reg;
 };
+
+enum intel_dpll_id {
+	DPLL_ID_NONE = -2, /* no dpll assigned/used */
+	DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
+	/* real shared dpll ids must be >= 0 */
+	DPLL_ID_PCH_PLL_A,
+	DPLL_ID_PCH_PLL_B,
+};
 #define I915_NUM_PLLS 2
 
 /* Used by dp and fdi links */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index daf12b5..d95d813 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -891,6 +891,17 @@ static void assert_pll(struct drm_i915_private *dev_priv,
 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 
+static struct intel_shared_dpll *
+intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
+{
+	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
+
+	if (crtc->shared_dpll < 0)
+		return NULL;
+
+	return &dev_priv->shared_dplls[crtc->shared_dpll];
+}
+
 /* For ILK+ */
 static void assert_shared_dpll(struct drm_i915_private *dev_priv,
 			       struct intel_shared_dpll *pll,
@@ -1374,16 +1385,15 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
  * The PCH PLL needs to be enabled before the PCH transcoder, since it
  * drives the transcoder clock.
  */
-static void ironlake_enable_shared_dpll(struct intel_crtc *intel_crtc)
+static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
 {
-	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
-	struct intel_shared_dpll *pll;
+	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
+	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
 	int reg;
 	u32 val;
 
 	/* PCH PLLs only available on ILK, SNB and IVB */
 	BUG_ON(dev_priv->info->gen < 5);
-	pll = intel_crtc->shared_dpll;
 	if (pll == NULL)
 		return;
 
@@ -1392,7 +1402,7 @@ static void ironlake_enable_shared_dpll(struct intel_crtc *intel_crtc)
 
 	DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
 		      pll->pll_reg, pll->active, pll->on,
-		      intel_crtc->base.base.id);
+		      crtc->base.base.id);
 
 	/* PCH refclock must be enabled first */
 	assert_pch_refclk_enabled(dev_priv);
@@ -1415,10 +1425,10 @@ static void ironlake_enable_shared_dpll(struct intel_crtc *intel_crtc)
 	pll->on = true;
 }
 
-static void intel_disable_shared_dpll(struct intel_crtc *intel_crtc)
+static void intel_disable_shared_dpll(struct intel_crtc *crtc)
 {
-	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
-	struct intel_shared_dpll *pll = intel_crtc->shared_dpll;
+	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
+	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
 	int reg;
 	u32 val;
 
@@ -1432,7 +1442,7 @@ static void intel_disable_shared_dpll(struct intel_crtc *intel_crtc)
 
 	DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
 		      pll->pll_reg, pll->active, pll->on,
-		      intel_crtc->base.base.id);
+		      crtc->base.base.id);
 
 	if (WARN_ON(pll->active == 0)) {
 		assert_shared_dpll_disabled(dev_priv, pll, NULL);
@@ -1447,7 +1457,7 @@ static void intel_disable_shared_dpll(struct intel_crtc *intel_crtc)
 	DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
 
 	/* Make sure transcoder isn't still depending on us */
-	assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe);
+	assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
 
 	reg = pll->pll_reg;
 	val = I915_READ(reg);
@@ -1464,6 +1474,7 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
 {
 	struct drm_device *dev = dev_priv->dev;
 	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	uint32_t reg, val, pipeconf_val;
 
 	/* PCH only available on ILK+ */
@@ -1471,8 +1482,8 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
 
 	/* Make sure PCH DPLL is enabled */
 	assert_shared_dpll_enabled(dev_priv,
-				   to_intel_crtc(crtc)->shared_dpll,
-				   to_intel_crtc(crtc));
+				   intel_crtc_to_shared_dpll(intel_crtc),
+				   intel_crtc);
 
 	/* FDI must be feeding us bits for PCH ports */
 	assert_fdi_tx_enabled(dev_priv, pipe);
@@ -2956,7 +2967,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
 			sel = TRANSC_DPLLB_SEL;
 			break;
 		}
-		if (intel_crtc->shared_dpll->pll_reg == _PCH_DPLL_B)
+		if (intel_crtc->shared_dpll == DPLL_ID_PCH_PLL_B)
 			temp |= sel;
 		else
 			temp &= ~sel;
@@ -3025,14 +3036,14 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
 	lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
 }
 
-static void intel_put_shared_dpll(struct intel_crtc *intel_crtc)
+static void intel_put_shared_dpll(struct intel_crtc *crtc)
 {
-	struct intel_shared_dpll *pll = intel_crtc->shared_dpll;
+	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
 
 	if (pll == NULL)
 		return;
 
-	WARN_ON(!intel_crtc->config.has_pch_encoder);
+	WARN_ON(!crtc->config.has_pch_encoder);
 
 	if (pll->refcount == 0) {
 		WARN(1, "bad PCH PLL refcount\n");
@@ -3044,29 +3055,28 @@ static void intel_put_shared_dpll(struct intel_crtc *intel_crtc)
 		WARN_ON(pll->active);
 	}
 
-	intel_crtc->shared_dpll = NULL;
+	crtc->shared_dpll = DPLL_ID_NONE;
 }
 
-static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
+static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, u32 dpll, u32 fp)
 {
-	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
-	struct intel_shared_dpll *pll;
-	int i;
+	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
+	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
+	enum intel_dpll_id i;
 
-	pll = intel_crtc->shared_dpll;
 	if (pll) {
 		DRM_DEBUG_KMS("CRTC:%d dropping existing PCH PLL %x\n",
-			      intel_crtc->base.base.id, pll->pll_reg);
-		intel_put_shared_dpll(intel_crtc);
+			      crtc->base.base.id, pll->pll_reg);
+		intel_put_shared_dpll(crtc);
 	}
 
 	if (HAS_PCH_IBX(dev_priv->dev)) {
 		/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
-		i = intel_crtc->pipe;
+		i = crtc->pipe;
 		pll = &dev_priv->shared_dplls[i];
 
 		DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
-			      intel_crtc->base.base.id, pll->pll_reg);
+			      crtc->base.base.id, pll->pll_reg);
 
 		goto found;
 	}
@@ -3081,7 +3091,7 @@ static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *intel_
 		if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
 		    fp == I915_READ(pll->fp0_reg)) {
 			DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
-				      intel_crtc->base.base.id,
+				      crtc->base.base.id,
 				      pll->pll_reg, pll->refcount, pll->active);
 
 			goto found;
@@ -3093,7 +3103,7 @@ static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *intel_
 		pll = &dev_priv->shared_dplls[i];
 		if (pll->refcount == 0) {
 			DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
-				      intel_crtc->base.base.id, pll->pll_reg);
+				      crtc->base.base.id, pll->pll_reg);
 			goto found;
 		}
 	}
@@ -3101,8 +3111,8 @@ static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *intel_
 	return NULL;
 
 found:
-	intel_crtc->shared_dpll = pll;
-	DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
+	crtc->shared_dpll = i;
+	DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(crtc->pipe));
 	if (pll->active == 0) {
 		DRM_DEBUG_DRIVER("setting up pll %d\n", i);
 		WARN_ON(pll->on);
@@ -5670,6 +5680,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 	bool ok, has_reduced_clock = false;
 	bool is_lvds = false;
 	struct intel_encoder *encoder;
+	struct intel_shared_dpll *pll;
 	int ret;
 
 	for_each_encoder_on_crtc(dev, crtc, encoder) {
@@ -5705,8 +5716,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 
 	/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
 	if (intel_crtc->config.has_pch_encoder) {
-		struct intel_shared_dpll *pll;
-
 		fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
 		if (has_reduced_clock)
 			fp2 = i9xx_dpll_compute_fp(&reduced_clock);
@@ -5731,11 +5740,15 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 		if (encoder->pre_pll_enable)
 			encoder->pre_pll_enable(encoder);
 
-	if (intel_crtc->shared_dpll) {
-		I915_WRITE(intel_crtc->shared_dpll->pll_reg, dpll);
+	intel_crtc->lowfreq_avail = false;
+
+	if (intel_crtc->config.has_pch_encoder) {
+		pll = intel_crtc_to_shared_dpll(intel_crtc);
+
+		I915_WRITE(pll->pll_reg, dpll);
 
 		/* Wait for the clocks to stabilize. */
-		POSTING_READ(intel_crtc->shared_dpll->pll_reg);
+		POSTING_READ(pll->pll_reg);
 		udelay(150);
 
 		/* The pixel multiplier can only be updated once the
@@ -5743,16 +5756,13 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 		 *
 		 * So write it again.
 		 */
-		I915_WRITE(intel_crtc->shared_dpll->pll_reg, dpll);
-	}
+		I915_WRITE(pll->pll_reg, dpll);
 
-	intel_crtc->lowfreq_avail = false;
-	if (intel_crtc->shared_dpll) {
 		if (is_lvds && has_reduced_clock && i915_powersave) {
-			I915_WRITE(intel_crtc->shared_dpll->fp1_reg, fp2);
+			I915_WRITE(pll->fp1_reg, fp2);
 			intel_crtc->lowfreq_avail = true;
 		} else {
-			I915_WRITE(intel_crtc->shared_dpll->fp1_reg, fp);
+			I915_WRITE(pll->fp1_reg, fp);
 		}
 	}
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 163bee9..422b2ad 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -306,7 +306,7 @@ struct intel_crtc {
 	struct intel_crtc_config config;
 
 	/* We can share PLLs across outputs if the timings match */
-	struct intel_shared_dpll *shared_dpll;
+	enum intel_dpll_id shared_dpll;
 	uint32_t ddi_pll_sel;
 
 	/* reset counter value when the last flip was submitted */
-- 
1.7.11.7

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* [PATCH 06/31] drm/i915: move shared_dpll into the pipe config
  2013-06-05 11:34 [PATCH 00/31] shared pch display pll rework Daniel Vetter
                   ` (4 preceding siblings ...)
  2013-06-05 11:34 ` [PATCH 05/31] drm/i915: switch crtc->shared_dpll from a pointer to an enum Daniel Vetter
@ 2013-06-05 11:34 ` Daniel Vetter
  2013-06-07 17:03   ` Ville Syrjälä
  2013-06-05 11:34 ` [PATCH 07/31] drm/i915: refactor PCH_DPLL_SEL #defines Daniel Vetter
                   ` (25 subsequent siblings)
  31 siblings, 1 reply; 84+ messages in thread
From: Daniel Vetter @ 2013-06-05 11:34 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

With the big sed-job prep work done this is now really simple.

v2: Kill the funny whitespace spotted by Chris.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 10 +++++-----
 drivers/gpu/drm/i915/intel_drv.h     |  5 +++--
 2 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d95d813..b09c9a2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -896,10 +896,10 @@ intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 
-	if (crtc->shared_dpll < 0)
+	if (crtc->config.shared_dpll < 0)
 		return NULL;
 
-	return &dev_priv->shared_dplls[crtc->shared_dpll];
+	return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 }
 
 /* For ILK+ */
@@ -2967,7 +2967,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
 			sel = TRANSC_DPLLB_SEL;
 			break;
 		}
-		if (intel_crtc->shared_dpll == DPLL_ID_PCH_PLL_B)
+		if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
 			temp |= sel;
 		else
 			temp &= ~sel;
@@ -3055,7 +3055,7 @@ static void intel_put_shared_dpll(struct intel_crtc *crtc)
 		WARN_ON(pll->active);
 	}
 
-	crtc->shared_dpll = DPLL_ID_NONE;
+	crtc->config.shared_dpll = DPLL_ID_NONE;
 }
 
 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, u32 dpll, u32 fp)
@@ -3111,7 +3111,7 @@ static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
 	return NULL;
 
 found:
-	crtc->shared_dpll = i;
+	crtc->config.shared_dpll = i;
 	DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(crtc->pipe));
 	if (pll->active == 0) {
 		DRM_DEBUG_DRIVER("setting up pll %d\n", i);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 422b2ad..e0e5d55 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -241,6 +241,9 @@ struct intel_crtc_config {
 	 * haswell. */
 	struct dpll dpll;
 
+	/* Selected dpll when shared or DPLL_ID_PRIVATE. */
+	enum intel_dpll_id shared_dpll;
+
 	int pipe_bpp;
 	struct intel_link_m_n dp_m_n;
 
@@ -305,8 +308,6 @@ struct intel_crtc {
 
 	struct intel_crtc_config config;
 
-	/* We can share PLLs across outputs if the timings match */
-	enum intel_dpll_id shared_dpll;
 	uint32_t ddi_pll_sel;
 
 	/* reset counter value when the last flip was submitted */
-- 
1.7.11.7

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* [PATCH 07/31] drm/i915: refactor PCH_DPLL_SEL #defines
  2013-06-05 11:34 [PATCH 00/31] shared pch display pll rework Daniel Vetter
                   ` (5 preceding siblings ...)
  2013-06-05 11:34 ` [PATCH 06/31] drm/i915: move shared_dpll into the pipe config Daniel Vetter
@ 2013-06-05 11:34 ` Daniel Vetter
  2013-06-05 11:34 ` [PATCH 08/31] drm/i915: hw state readout for shared pch plls Daniel Vetter
                   ` (24 subsequent siblings)
  31 siblings, 0 replies; 84+ messages in thread
From: Daniel Vetter @ 2013-06-05 11:34 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

The bits are evenly space, so we can cut down on two big switch
blocks. This also greatly simplifies the hw state readout which
follows in the next patch.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_reg.h      | 12 +++---------
 drivers/gpu/drm/i915/intel_display.c | 32 +++-----------------------------
 2 files changed, 6 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 47a9de0..68ea707 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3980,15 +3980,9 @@
 #define PCH_SSC4_AUX_PARMS      0xc6214
 
 #define PCH_DPLL_SEL		0xc7000
-#define  TRANSA_DPLL_ENABLE	(1<<3)
-#define	 TRANSA_DPLLB_SEL	(1<<0)
-#define	 TRANSA_DPLLA_SEL	0
-#define  TRANSB_DPLL_ENABLE	(1<<7)
-#define	 TRANSB_DPLLB_SEL	(1<<4)
-#define	 TRANSB_DPLLA_SEL	(0)
-#define  TRANSC_DPLL_ENABLE	(1<<11)
-#define	 TRANSC_DPLLB_SEL	(1<<8)
-#define	 TRANSC_DPLLA_SEL	(0)
+#define	 TRANS_DPLLB_SEL(pipe)		(1 << (pipe * 4))
+#define	 TRANS_DPLLA_SEL(pipe)		0
+#define  TRANS_DPLL_ENABLE(pipe)	(1 << (pipe * 4 + 3))
 
 /* transcoder */
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b09c9a2..a44c43c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2952,21 +2952,8 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
 		u32 sel;
 
 		temp = I915_READ(PCH_DPLL_SEL);
-		switch (pipe) {
-		default:
-		case 0:
-			temp |= TRANSA_DPLL_ENABLE;
-			sel = TRANSA_DPLLB_SEL;
-			break;
-		case 1:
-			temp |= TRANSB_DPLL_ENABLE;
-			sel = TRANSB_DPLLB_SEL;
-			break;
-		case 2:
-			temp |= TRANSC_DPLL_ENABLE;
-			sel = TRANSC_DPLLB_SEL;
-			break;
-		}
+		temp |= TRANS_DPLL_ENABLE(pipe);
+		sel = TRANS_DPLLB_SEL(pipe);
 		if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
 			temp |= sel;
 		else
@@ -3425,20 +3412,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
 
 			/* disable DPLL_SEL */
 			temp = I915_READ(PCH_DPLL_SEL);
-			switch (pipe) {
-			case 0:
-				temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
-				break;
-			case 1:
-				temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
-				break;
-			case 2:
-				/* C shares PLL A or B */
-				temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
-				break;
-			default:
-				BUG(); /* wtf */
-			}
+			temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
 			I915_WRITE(PCH_DPLL_SEL, temp);
 		}
 
-- 
1.7.11.7

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* [PATCH 08/31] drm/i915: hw state readout for shared pch plls
  2013-06-05 11:34 [PATCH 00/31] shared pch display pll rework Daniel Vetter
                   ` (6 preceding siblings ...)
  2013-06-05 11:34 ` [PATCH 07/31] drm/i915: refactor PCH_DPLL_SEL #defines Daniel Vetter
@ 2013-06-05 11:34 ` Daniel Vetter
  2013-06-07 17:23   ` Ville Syrjälä
  2013-06-05 11:34 ` [PATCH 09/31] drm/i915: consolidate ->num_shared_dplls assignement Daniel Vetter
                   ` (23 subsequent siblings)
  31 siblings, 1 reply; 84+ messages in thread
From: Daniel Vetter @ 2013-06-05 11:34 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

Well, the first step of a long road at least, it only reads out
the pipe -> shared dpll association thus far. Other state which needs
to follow:

- hw state of the dpll (on/off + dpll registers). Currently we just
  read that out from the hw state, but that doesn't work too well when
  the dpll is in use, but not yet fully enabled. We get away since
  most likely it already has been enabled and so the correct state is
  left behind in the registers. But that doesn't hold for atomic
  modesets when we want to enable all pipes at once.

- Refcount reconstruction for each dpll.

- Cross-checking of all the above. For that we need to keep the dpll
  register state both in the pipe and in the shared_dpll struct, so
  that we can check that every pipe is still connected to a correctly
  configured dpll.

Note that since the refcount resconstruction isn't done yet this will
spill a few WARNs at boot-up while trying to disable pch plls which
have bogus refcounts. But since there's still a pile of refactoring to
do I'd like to lock down the state handling as soon as possible hence
decided against reordering the patches to quiet these WARNs - after
all the issues they're complaining about have existed since forever,
as Jesse can testify by having pch pll states blow up consistently in
his fastboot patches ...

v2: We need to preserve the old shared_dpll since currently the
shared dpll refcount dropping/getting is done in ->mode_set. With
the usual pipe_config infrastructure the old dpll id is already lost
at that point, hence preserve it in the new config.

v3: Rebase on top of the ips patch from Paulo.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 34 ++++++++++++++++++++++++++++------
 1 file changed, 28 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a44c43c..20a933f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4020,12 +4020,11 @@ static void hsw_compute_ips_config(struct intel_crtc *crtc,
 				   pipe_config->pipe_bpp == 24;
 }
 
-static int intel_crtc_compute_config(struct drm_crtc *crtc,
+static int intel_crtc_compute_config(struct intel_crtc *crtc,
 				     struct intel_crtc_config *pipe_config)
 {
-	struct drm_device *dev = crtc->dev;
+	struct drm_device *dev = crtc->base.dev;
 	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 
 	if (HAS_PCH_SPLIT(dev)) {
 		/* FDI link clock is fixed at 2.7G */
@@ -4056,10 +4055,16 @@ static int intel_crtc_compute_config(struct drm_crtc *crtc,
 	}
 
 	if (IS_HASWELL(dev))
-		hsw_compute_ips_config(intel_crtc, pipe_config);
+		hsw_compute_ips_config(crtc, pipe_config);
+
+	/* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
+	 * clock survives for now. */
+	if (pipe_config->has_pch_encoder &&
+	    (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)))
+		pipe_config->shared_dpll = crtc->config.shared_dpll;
 
 	if (pipe_config->has_pch_encoder)
-		return ironlake_fdi_compute_config(intel_crtc, pipe_config);
+		return ironlake_fdi_compute_config(crtc, pipe_config);
 
 	return 0;
 }
@@ -4934,6 +4939,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
 	uint32_t tmp;
 
 	pipe_config->cpu_transcoder = crtc->pipe;
+	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
 
 	tmp = I915_READ(PIPECONF(crtc->pipe));
 	if (!(tmp & PIPECONF_ENABLE))
@@ -5810,6 +5816,7 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
 	uint32_t tmp;
 
 	pipe_config->cpu_transcoder = crtc->pipe;
+	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
 
 	tmp = I915_READ(PIPECONF(crtc->pipe));
 	if (!(tmp & PIPECONF_ENABLE))
@@ -5827,6 +5834,16 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
 		/* XXX: Can't properly read out the pch dpll pixel multiplier
 		 * since we don't have state tracking for pch clocks yet. */
 		pipe_config->pixel_multiplier = 1;
+
+		if (HAS_PCH_IBX(dev_priv->dev)) {
+			pipe_config->shared_dpll = crtc->pipe;
+		} else {
+			tmp = I915_READ(PCH_DPLL_SEL);
+			if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
+				pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
+			else
+				pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
+		}
 	} else {
 		pipe_config->pixel_multiplier = 1;
 	}
@@ -5907,6 +5924,8 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
 	uint32_t tmp;
 
 	pipe_config->cpu_transcoder = crtc->pipe;
+	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
+
 	tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
 	if (tmp & TRANS_DDI_FUNC_ENABLE) {
 		enum pipe trans_edp_pipe;
@@ -7768,6 +7787,7 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
 	drm_mode_copy(&pipe_config->adjusted_mode, mode);
 	drm_mode_copy(&pipe_config->requested_mode, mode);
 	pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
+	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
 
 	/* Compute a starting value for pipe_config->pipe_bpp taking the source
 	 * plane pixel format and any sink constraints into account. Returns the
@@ -7816,7 +7836,7 @@ encoder_retry:
 	if (!pipe_config->port_clock)
 		pipe_config->port_clock = pipe_config->adjusted_mode.clock;
 
-	ret = intel_crtc_compute_config(crtc, pipe_config);
+	ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
 	if (ret < 0) {
 		DRM_DEBUG_KMS("CRTC fixup failed\n");
 		goto fail;
@@ -8079,6 +8099,8 @@ intel_pipe_config_compare(struct drm_device *dev,
 
 	PIPE_CONF_CHECK_I(ips_enabled);
 
+	PIPE_CONF_CHECK_I(shared_dpll);
+
 #undef PIPE_CONF_CHECK_I
 #undef PIPE_CONF_CHECK_FLAGS
 
-- 
1.7.11.7

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* [PATCH 09/31] drm/i915: consolidate ->num_shared_dplls assignement
  2013-06-05 11:34 [PATCH 00/31] shared pch display pll rework Daniel Vetter
                   ` (7 preceding siblings ...)
  2013-06-05 11:34 ` [PATCH 08/31] drm/i915: hw state readout for shared pch plls Daniel Vetter
@ 2013-06-05 11:34 ` Daniel Vetter
  2013-06-05 11:34 ` [PATCH 10/31] drm/i915: metadata for shared dplls Daniel Vetter
                   ` (22 subsequent siblings)
  31 siblings, 0 replies; 84+ messages in thread
From: Daniel Vetter @ 2013-06-05 11:34 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

In the future this won't be just for pch plls, so move it into the
shared dpll init code.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_drv.c      |  7 -------
 drivers/gpu/drm/i915/intel_display.c | 21 ++++++++++++++++-----
 2 files changed, 16 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 0672f34..270feb6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -457,7 +457,6 @@ void intel_detect_pch(struct drm_device *dev)
 	 */
 	if (INTEL_INFO(dev)->num_pipes == 0) {
 		dev_priv->pch_type = PCH_NOP;
-		dev_priv->num_shared_dpll = 0;
 		return;
 	}
 
@@ -476,34 +475,28 @@ void intel_detect_pch(struct drm_device *dev)
 
 			if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_IBX;
-				dev_priv->num_shared_dpll = 2;
 				DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 				WARN_ON(!IS_GEN5(dev));
 			} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_CPT;
-				dev_priv->num_shared_dpll = 2;
 				DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 				WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 			} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 				/* PantherPoint is CPT compatible */
 				dev_priv->pch_type = PCH_CPT;
-				dev_priv->num_shared_dpll = 2;
 				DRM_DEBUG_KMS("Found PatherPoint PCH\n");
 				WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 			} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_LPT;
-				dev_priv->num_shared_dpll = 0;
 				DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 				WARN_ON(!IS_HASWELL(dev));
 				WARN_ON(IS_ULT(dev));
 			} else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_LPT;
-				dev_priv->num_shared_dpll = 0;
 				DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 				WARN_ON(!IS_HASWELL(dev));
 				WARN_ON(!IS_ULT(dev));
 			}
-			BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
 		}
 		pci_dev_put(pch);
 	}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 20a933f..829e75b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8665,15 +8665,12 @@ static void intel_cpu_pll_init(struct drm_device *dev)
 		intel_ddi_pll_init(dev);
 }
 
-static void intel_shared_dpll_init(struct drm_device *dev)
+static void ibx_pch_dpll_init(struct drm_device *dev)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	int i;
 
-	if (dev_priv->num_shared_dpll == 0) {
-		DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
-		return;
-	}
+	dev_priv->num_shared_dpll = 2;
 
 	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
 		dev_priv->shared_dplls[i].pll_reg = _PCH_DPLL(i);
@@ -8682,6 +8679,20 @@ static void intel_shared_dpll_init(struct drm_device *dev)
 	}
 }
 
+static void intel_shared_dpll_init(struct drm_device *dev)
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
+
+	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
+		ibx_pch_dpll_init(dev);
+	} else {
+		dev_priv->num_shared_dpll = 0;
+	}
+	BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
+	DRM_DEBUG_KMS("%i shared PLLs initialized\n",
+		      dev_priv->num_shared_dpll);
+}
+
 static void intel_crtc_init(struct drm_device *dev, int pipe)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
-- 
1.7.11.7

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* [PATCH 10/31] drm/i915: metadata for shared dplls
  2013-06-05 11:34 [PATCH 00/31] shared pch display pll rework Daniel Vetter
                   ` (8 preceding siblings ...)
  2013-06-05 11:34 ` [PATCH 09/31] drm/i915: consolidate ->num_shared_dplls assignement Daniel Vetter
@ 2013-06-05 11:34 ` Daniel Vetter
  2013-06-05 11:34 ` [PATCH 11/31] drm/i915: scrap register address storage Daniel Vetter
                   ` (21 subsequent siblings)
  31 siblings, 0 replies; 84+ messages in thread
From: Daniel Vetter @ 2013-06-05 11:34 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

An id to match the idx (useful for register access macros) and a name
fore neater debug output.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_drv.h      | 21 +++++++++-------
 drivers/gpu/drm/i915/intel_display.c | 48 +++++++++++++++++++++---------------
 2 files changed, 40 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ca3cb3b..f1a7f8c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -132,15 +132,6 @@ enum hpd_pin {
 	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
 		if ((intel_encoder)->base.crtc == (__crtc))
 
-struct intel_shared_dpll {
-	int refcount; /* count of number of CRTCs sharing this PLL */
-	int active; /* count of number of active CRTCs (i.e. DPMS on) */
-	bool on; /* is the PLL actually active? Disabled during modeset */
-	int pll_reg;
-	int fp0_reg;
-	int fp1_reg;
-};
-
 enum intel_dpll_id {
 	DPLL_ID_NONE = -2, /* no dpll assigned/used */
 	DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
@@ -150,6 +141,18 @@ enum intel_dpll_id {
 };
 #define I915_NUM_PLLS 2
 
+struct intel_shared_dpll {
+	int refcount; /* count of number of CRTCs sharing this PLL */
+	int active; /* count of number of active CRTCs (i.e. DPMS on) */
+	bool on; /* is the PLL actually active? Disabled during modeset */
+	const char *name;
+	/* should match the index in the dev_priv->shared_dplls array */
+	enum intel_dpll_id id;
+	int pll_reg;
+	int fp0_reg;
+	int fp1_reg;
+};
+
 /* Used by dp and fdi links */
 struct intel_link_m_n {
 	uint32_t	tu;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 829e75b..eecacd2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -917,14 +917,14 @@ static void assert_shared_dpll(struct drm_i915_private *dev_priv,
 	}
 
 	if (WARN (!pll,
-		  "asserting PCH PLL %s with no PLL\n", state_string(state)))
+		  "asserting DPLL %s with no DPLL\n", state_string(state)))
 		return;
 
 	val = I915_READ(pll->pll_reg);
 	cur_state = !!(val & DPLL_VCO_ENABLE);
 	WARN(cur_state != state,
-	     "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
-	     pll->pll_reg, state_string(state), state_string(cur_state), val);
+	     "%s assertion failure (expected %s, current %s), val=%08x\n",
+	     pll->name, state_string(state), state_string(cur_state), val);
 
 	/* Make sure the selected PLL is correctly attached to the transcoder */
 	if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
@@ -1400,8 +1400,8 @@ static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
 	if (WARN_ON(pll->refcount == 0))
 		return;
 
-	DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
-		      pll->pll_reg, pll->active, pll->on,
+	DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
+		      pll->name, pll->active, pll->on,
 		      crtc->base.base.id);
 
 	/* PCH refclock must be enabled first */
@@ -1413,7 +1413,7 @@ static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
 		return;
 	}
 
-	DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
+	DRM_DEBUG_KMS("enabling %s\n", pll->name);
 
 	reg = pll->pll_reg;
 	val = I915_READ(reg);
@@ -1440,8 +1440,8 @@ static void intel_disable_shared_dpll(struct intel_crtc *crtc)
 	if (WARN_ON(pll->refcount == 0))
 		return;
 
-	DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
-		      pll->pll_reg, pll->active, pll->on,
+	DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
+		      pll->name, pll->active, pll->on,
 		      crtc->base.base.id);
 
 	if (WARN_ON(pll->active == 0)) {
@@ -1454,7 +1454,7 @@ static void intel_disable_shared_dpll(struct intel_crtc *crtc)
 	if (--pll->active)
 		return;
 
-	DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
+	DRM_DEBUG_KMS("disabling %s\n", pll->name);
 
 	/* Make sure transcoder isn't still depending on us */
 	assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
@@ -3033,7 +3033,7 @@ static void intel_put_shared_dpll(struct intel_crtc *crtc)
 	WARN_ON(!crtc->config.has_pch_encoder);
 
 	if (pll->refcount == 0) {
-		WARN(1, "bad PCH PLL refcount\n");
+		WARN(1, "bad %s refcount\n", pll->name);
 		return;
 	}
 
@@ -3052,8 +3052,8 @@ static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
 	enum intel_dpll_id i;
 
 	if (pll) {
-		DRM_DEBUG_KMS("CRTC:%d dropping existing PCH PLL %x\n",
-			      crtc->base.base.id, pll->pll_reg);
+		DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
+			      crtc->base.base.id, pll->name);
 		intel_put_shared_dpll(crtc);
 	}
 
@@ -3062,8 +3062,8 @@ static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
 		i = crtc->pipe;
 		pll = &dev_priv->shared_dplls[i];
 
-		DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
-			      crtc->base.base.id, pll->pll_reg);
+		DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
+			      crtc->base.base.id, pll->name);
 
 		goto found;
 	}
@@ -3077,9 +3077,9 @@ static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
 
 		if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
 		    fp == I915_READ(pll->fp0_reg)) {
-			DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
+			DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
 				      crtc->base.base.id,
-				      pll->pll_reg, pll->refcount, pll->active);
+				      pll->name, pll->refcount, pll->active);
 
 			goto found;
 		}
@@ -3089,8 +3089,8 @@ static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
 	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
 		pll = &dev_priv->shared_dplls[i];
 		if (pll->refcount == 0) {
-			DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
-				      crtc->base.base.id, pll->pll_reg);
+			DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
+				      crtc->base.base.id, pll->name);
 			goto found;
 		}
 	}
@@ -3099,9 +3099,10 @@ static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
 
 found:
 	crtc->config.shared_dpll = i;
-	DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(crtc->pipe));
+	DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
+			 pipe_name(crtc->pipe));
 	if (pll->active == 0) {
-		DRM_DEBUG_DRIVER("setting up pll %d\n", i);
+		DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
 		WARN_ON(pll->on);
 		assert_shared_dpll_disabled(dev_priv, pll, NULL);
 
@@ -8665,6 +8666,11 @@ static void intel_cpu_pll_init(struct drm_device *dev)
 		intel_ddi_pll_init(dev);
 }
 
+static char *ibx_pch_dpll_names[] = {
+	"PCH DPLL A",
+	"PCH DPLL B",
+};
+
 static void ibx_pch_dpll_init(struct drm_device *dev)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
@@ -8673,6 +8679,8 @@ static void ibx_pch_dpll_init(struct drm_device *dev)
 	dev_priv->num_shared_dpll = 2;
 
 	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
+		dev_priv->shared_dplls[i].id = i;
+		dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
 		dev_priv->shared_dplls[i].pll_reg = _PCH_DPLL(i);
 		dev_priv->shared_dplls[i].fp0_reg = _PCH_FP0(i);
 		dev_priv->shared_dplls[i].fp1_reg = _PCH_FP1(i);
-- 
1.7.11.7

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* [PATCH 11/31] drm/i915: scrap register address storage
  2013-06-05 11:34 [PATCH 00/31] shared pch display pll rework Daniel Vetter
                   ` (9 preceding siblings ...)
  2013-06-05 11:34 ` [PATCH 10/31] drm/i915: metadata for shared dplls Daniel Vetter
@ 2013-06-05 11:34 ` Daniel Vetter
  2013-06-05 11:34 ` [PATCH 12/31] drm/i915: enable/disable hooks for shared dplls Daniel Vetter
                   ` (20 subsequent siblings)
  31 siblings, 0 replies; 84+ messages in thread
From: Daniel Vetter @ 2013-06-05 11:34 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

Using ids in register macros is much more common in our driver. Also
this way we can reduce the platform specific stuff a bit.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_drv.h      |  3 ---
 drivers/gpu/drm/i915/i915_reg.h      |  6 +++---
 drivers/gpu/drm/i915/i915_ums.c      |  2 +-
 drivers/gpu/drm/i915/intel_display.c | 35 ++++++++++++++++-------------------
 4 files changed, 20 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f1a7f8c..df3d0f3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -148,9 +148,6 @@ struct intel_shared_dpll {
 	const char *name;
 	/* should match the index in the dev_priv->shared_dplls array */
 	enum intel_dpll_id id;
-	int pll_reg;
-	int fp0_reg;
-	int fp1_reg;
 };
 
 /* Used by dp and fdi links */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 68ea707..c2d954e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3932,15 +3932,15 @@
 
 #define _PCH_DPLL_A              0xc6014
 #define _PCH_DPLL_B              0xc6018
-#define _PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
+#define PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
 
 #define _PCH_FPA0                0xc6040
 #define  FP_CB_TUNE		(0x3<<22)
 #define _PCH_FPA1                0xc6044
 #define _PCH_FPB0                0xc6048
 #define _PCH_FPB1                0xc604c
-#define _PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
-#define _PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
+#define PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
+#define PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
 
 #define PCH_DPLL_TEST           0xc606c
 
diff --git a/drivers/gpu/drm/i915/i915_ums.c b/drivers/gpu/drm/i915/i915_ums.c
index 5ef30b2..967da47 100644
--- a/drivers/gpu/drm/i915/i915_ums.c
+++ b/drivers/gpu/drm/i915/i915_ums.c
@@ -41,7 +41,7 @@ static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
 		return false;
 
 	if (HAS_PCH_SPLIT(dev))
-		dpll_reg = _PCH_DPLL(pipe);
+		dpll_reg = PCH_DPLL(pipe);
 	else
 		dpll_reg = (pipe == PIPE_A) ? _DPLL_A : _DPLL_B;
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index eecacd2..f2c0d79 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -920,7 +920,7 @@ static void assert_shared_dpll(struct drm_i915_private *dev_priv,
 		  "asserting DPLL %s with no DPLL\n", state_string(state)))
 		return;
 
-	val = I915_READ(pll->pll_reg);
+	val = I915_READ(PCH_DPLL(pll->id));
 	cur_state = !!(val & DPLL_VCO_ENABLE);
 	WARN(cur_state != state,
 	     "%s assertion failure (expected %s, current %s), val=%08x\n",
@@ -931,14 +931,14 @@ static void assert_shared_dpll(struct drm_i915_private *dev_priv,
 		u32 pch_dpll;
 
 		pch_dpll = I915_READ(PCH_DPLL_SEL);
-		cur_state = pll->pll_reg == _PCH_DPLL_B;
+		cur_state = pll->id == DPLL_ID_PCH_PLL_B;
 		if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
 			  "PLL[%d] not attached to this transcoder %c: %08x\n",
 			  cur_state, pipe_name(crtc->pipe), pch_dpll)) {
 			cur_state = !!(val >> (4*crtc->pipe + 3));
 			WARN(cur_state != state,
 			     "PLL[%d] not %s on this transcoder %c: %08x\n",
-			     pll->pll_reg == _PCH_DPLL_B,
+			     pll->id == DPLL_ID_PCH_PLL_B,
 			     state_string(state),
 			     pipe_name(crtc->pipe),
 			     val);
@@ -1415,7 +1415,7 @@ static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
 
 	DRM_DEBUG_KMS("enabling %s\n", pll->name);
 
-	reg = pll->pll_reg;
+	reg = PCH_DPLL(pll->id);
 	val = I915_READ(reg);
 	val |= DPLL_VCO_ENABLE;
 	I915_WRITE(reg, val);
@@ -1459,7 +1459,7 @@ static void intel_disable_shared_dpll(struct intel_crtc *crtc)
 	/* Make sure transcoder isn't still depending on us */
 	assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
 
-	reg = pll->pll_reg;
+	reg = PCH_DPLL(pll->id);
 	val = I915_READ(reg);
 	val &= ~DPLL_VCO_ENABLE;
 	I915_WRITE(reg, val);
@@ -3075,8 +3075,8 @@ static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
 		if (pll->refcount == 0)
 			continue;
 
-		if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
-		    fp == I915_READ(pll->fp0_reg)) {
+		if (dpll == (I915_READ(PCH_DPLL(pll->id)) & 0x7fffffff) &&
+		    fp == I915_READ(PCH_FP0(pll->id))) {
 			DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
 				      crtc->base.base.id,
 				      pll->name, pll->refcount, pll->active);
@@ -3107,12 +3107,12 @@ found:
 		assert_shared_dpll_disabled(dev_priv, pll, NULL);
 
 		/* Wait for the clocks to stabilize before rewriting the regs */
-		I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
-		POSTING_READ(pll->pll_reg);
+		I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
+		POSTING_READ(PCH_DPLL(pll->id));
 		udelay(150);
 
-		I915_WRITE(pll->fp0_reg, fp);
-		I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
+		I915_WRITE(PCH_FP0(pll->id), fp);
+		I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
 	}
 	pll->refcount++;
 
@@ -5726,10 +5726,10 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 	if (intel_crtc->config.has_pch_encoder) {
 		pll = intel_crtc_to_shared_dpll(intel_crtc);
 
-		I915_WRITE(pll->pll_reg, dpll);
+		I915_WRITE(PCH_DPLL(pll->id), dpll);
 
 		/* Wait for the clocks to stabilize. */
-		POSTING_READ(pll->pll_reg);
+		POSTING_READ(PCH_DPLL(pll->id));
 		udelay(150);
 
 		/* The pixel multiplier can only be updated once the
@@ -5737,13 +5737,13 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 		 *
 		 * So write it again.
 		 */
-		I915_WRITE(pll->pll_reg, dpll);
+		I915_WRITE(PCH_DPLL(pll->id), dpll);
 
 		if (is_lvds && has_reduced_clock && i915_powersave) {
-			I915_WRITE(pll->fp1_reg, fp2);
+			I915_WRITE(PCH_FP1(pll->id), fp2);
 			intel_crtc->lowfreq_avail = true;
 		} else {
-			I915_WRITE(pll->fp1_reg, fp);
+			I915_WRITE(PCH_FP1(pll->id), fp);
 		}
 	}
 
@@ -8681,9 +8681,6 @@ static void ibx_pch_dpll_init(struct drm_device *dev)
 	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
 		dev_priv->shared_dplls[i].id = i;
 		dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
-		dev_priv->shared_dplls[i].pll_reg = _PCH_DPLL(i);
-		dev_priv->shared_dplls[i].fp0_reg = _PCH_FP0(i);
-		dev_priv->shared_dplls[i].fp1_reg = _PCH_FP1(i);
 	}
 }
 
-- 
1.7.11.7

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* [PATCH 12/31] drm/i915: enable/disable hooks for shared dplls
  2013-06-05 11:34 [PATCH 00/31] shared pch display pll rework Daniel Vetter
                   ` (10 preceding siblings ...)
  2013-06-05 11:34 ` [PATCH 11/31] drm/i915: scrap register address storage Daniel Vetter
@ 2013-06-05 11:34 ` Daniel Vetter
  2013-06-05 11:34 ` [PATCH 13/31] drm/i915: drop crtc checking from assert_shared_dpll Daniel Vetter
                   ` (19 subsequent siblings)
  31 siblings, 0 replies; 84+ messages in thread
From: Daniel Vetter @ 2013-06-05 11:34 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

Looks at first like a bit of overkill, but
- Haswell actually wants different enable/disable functions for
  different plls.
- And once we have full dpll hw state tracking we can move the full
  register setup into the ->enable hook.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_drv.h      |  7 +++-
 drivers/gpu/drm/i915/intel_display.c | 71 ++++++++++++++++++++++--------------
 2 files changed, 49 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index df3d0f3..8e61128 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -132,6 +132,8 @@ enum hpd_pin {
 	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
 		if ((intel_encoder)->base.crtc == (__crtc))
 
+struct drm_i915_private;
+
 enum intel_dpll_id {
 	DPLL_ID_NONE = -2, /* no dpll assigned/used */
 	DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
@@ -148,6 +150,10 @@ struct intel_shared_dpll {
 	const char *name;
 	/* should match the index in the dev_priv->shared_dplls array */
 	enum intel_dpll_id id;
+	void (*enable)(struct drm_i915_private *dev_priv,
+		       struct intel_shared_dpll *pll);
+	void (*disable)(struct drm_i915_private *dev_priv,
+			struct intel_shared_dpll *pll);
 };
 
 /* Used by dp and fdi links */
@@ -203,7 +209,6 @@ struct opregion_header;
 struct opregion_acpi;
 struct opregion_swsci;
 struct opregion_asle;
-struct drm_i915_private;
 
 struct intel_opregion {
 	struct opregion_header __iomem *header;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f2c0d79..1c4aedd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1389,8 +1389,6 @@ static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
-	int reg;
-	u32 val;
 
 	/* PCH PLLs only available on ILK, SNB and IVB */
 	BUG_ON(dev_priv->info->gen < 5);
@@ -1404,9 +1402,6 @@ static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
 		      pll->name, pll->active, pll->on,
 		      crtc->base.base.id);
 
-	/* PCH refclock must be enabled first */
-	assert_pch_refclk_enabled(dev_priv);
-
 	if (pll->active++) {
 		WARN_ON(!pll->on);
 		assert_shared_dpll_enabled(dev_priv, pll, NULL);
@@ -1414,14 +1409,7 @@ static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
 	}
 
 	DRM_DEBUG_KMS("enabling %s\n", pll->name);
-
-	reg = PCH_DPLL(pll->id);
-	val = I915_READ(reg);
-	val |= DPLL_VCO_ENABLE;
-	I915_WRITE(reg, val);
-	POSTING_READ(reg);
-	udelay(200);
-
+	pll->enable(dev_priv, pll);
 	pll->on = true;
 }
 
@@ -1429,8 +1417,6 @@ static void intel_disable_shared_dpll(struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
-	int reg;
-	u32 val;
 
 	/* PCH only available on ILK+ */
 	BUG_ON(dev_priv->info->gen < 5);
@@ -1455,17 +1441,7 @@ static void intel_disable_shared_dpll(struct intel_crtc *crtc)
 		return;
 
 	DRM_DEBUG_KMS("disabling %s\n", pll->name);
-
-	/* Make sure transcoder isn't still depending on us */
-	assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
-
-	reg = PCH_DPLL(pll->id);
-	val = I915_READ(reg);
-	val &= ~DPLL_VCO_ENABLE;
-	I915_WRITE(reg, val);
-	POSTING_READ(reg);
-	udelay(200);
-
+	pll->disable(dev_priv, pll);
 	pll->on = false;
 }
 
@@ -8666,6 +8642,43 @@ static void intel_cpu_pll_init(struct drm_device *dev)
 		intel_ddi_pll_init(dev);
 }
 
+static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
+				struct intel_shared_dpll *pll)
+{
+	uint32_t reg, val;
+
+	/* PCH refclock must be enabled first */
+	assert_pch_refclk_enabled(dev_priv);
+
+	reg = PCH_DPLL(pll->id);
+	val = I915_READ(reg);
+	val |= DPLL_VCO_ENABLE;
+	I915_WRITE(reg, val);
+	POSTING_READ(reg);
+	udelay(200);
+}
+
+static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
+				 struct intel_shared_dpll *pll)
+{
+	struct drm_device *dev = dev_priv->dev;
+	struct intel_crtc *crtc;
+	uint32_t reg, val;
+
+	/* Make sure no transcoder isn't still depending on us. */
+	list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
+		if (intel_crtc_to_shared_dpll(crtc) == pll)
+			assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
+	}
+
+	reg = PCH_DPLL(pll->id);
+	val = I915_READ(reg);
+	val &= ~DPLL_VCO_ENABLE;
+	I915_WRITE(reg, val);
+	POSTING_READ(reg);
+	udelay(200);
+}
+
 static char *ibx_pch_dpll_names[] = {
 	"PCH DPLL A",
 	"PCH DPLL B",
@@ -8673,7 +8686,7 @@ static char *ibx_pch_dpll_names[] = {
 
 static void ibx_pch_dpll_init(struct drm_device *dev)
 {
-	drm_i915_private_t *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = dev->dev_private;
 	int i;
 
 	dev_priv->num_shared_dpll = 2;
@@ -8681,12 +8694,14 @@ static void ibx_pch_dpll_init(struct drm_device *dev)
 	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
 		dev_priv->shared_dplls[i].id = i;
 		dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
+		dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
+		dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
 	}
 }
 
 static void intel_shared_dpll_init(struct drm_device *dev)
 {
-	drm_i915_private_t *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = dev->dev_private;
 
 	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
 		ibx_pch_dpll_init(dev);
-- 
1.7.11.7

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* [PATCH 13/31] drm/i915: drop crtc checking from assert_shared_dpll
  2013-06-05 11:34 [PATCH 00/31] shared pch display pll rework Daniel Vetter
                   ` (11 preceding siblings ...)
  2013-06-05 11:34 ` [PATCH 12/31] drm/i915: enable/disable hooks for shared dplls Daniel Vetter
@ 2013-06-05 11:34 ` Daniel Vetter
  2013-06-05 11:34 ` [PATCH 14/31] drm/i915: display pll hw state readout and checking Daniel Vetter
                   ` (18 subsequent siblings)
  31 siblings, 0 replies; 84+ messages in thread
From: Daniel Vetter @ 2013-06-05 11:34 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

The hw state readout code for the pipe config will now check
this for us, so rip out this hand-rolled complexity.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 35 +++++++----------------------------
 1 file changed, 7 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1c4aedd..ea4b7a6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -905,7 +905,6 @@ intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 /* For ILK+ */
 static void assert_shared_dpll(struct drm_i915_private *dev_priv,
 			       struct intel_shared_dpll *pll,
-			       struct intel_crtc *crtc,
 			       bool state)
 {
 	u32 val;
@@ -925,28 +924,9 @@ static void assert_shared_dpll(struct drm_i915_private *dev_priv,
 	WARN(cur_state != state,
 	     "%s assertion failure (expected %s, current %s), val=%08x\n",
 	     pll->name, state_string(state), state_string(cur_state), val);
-
-	/* Make sure the selected PLL is correctly attached to the transcoder */
-	if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
-		u32 pch_dpll;
-
-		pch_dpll = I915_READ(PCH_DPLL_SEL);
-		cur_state = pll->id == DPLL_ID_PCH_PLL_B;
-		if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
-			  "PLL[%d] not attached to this transcoder %c: %08x\n",
-			  cur_state, pipe_name(crtc->pipe), pch_dpll)) {
-			cur_state = !!(val >> (4*crtc->pipe + 3));
-			WARN(cur_state != state,
-			     "PLL[%d] not %s on this transcoder %c: %08x\n",
-			     pll->id == DPLL_ID_PCH_PLL_B,
-			     state_string(state),
-			     pipe_name(crtc->pipe),
-			     val);
-		}
-	}
 }
-#define assert_shared_dpll_enabled(d, p, c) assert_shared_dpll(d, p, c, true)
-#define assert_shared_dpll_disabled(d, p, c) assert_shared_dpll(d, p, c, false)
+#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
+#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
 
 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 			  enum pipe pipe, bool state)
@@ -1404,7 +1384,7 @@ static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
 
 	if (pll->active++) {
 		WARN_ON(!pll->on);
-		assert_shared_dpll_enabled(dev_priv, pll, NULL);
+		assert_shared_dpll_enabled(dev_priv, pll);
 		return;
 	}
 
@@ -1431,11 +1411,11 @@ static void intel_disable_shared_dpll(struct intel_crtc *crtc)
 		      crtc->base.base.id);
 
 	if (WARN_ON(pll->active == 0)) {
-		assert_shared_dpll_disabled(dev_priv, pll, NULL);
+		assert_shared_dpll_disabled(dev_priv, pll);
 		return;
 	}
 
-	assert_shared_dpll_enabled(dev_priv, pll, NULL);
+	assert_shared_dpll_enabled(dev_priv, pll);
 	WARN_ON(!pll->on);
 	if (--pll->active)
 		return;
@@ -1458,8 +1438,7 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
 
 	/* Make sure PCH DPLL is enabled */
 	assert_shared_dpll_enabled(dev_priv,
-				   intel_crtc_to_shared_dpll(intel_crtc),
-				   intel_crtc);
+				   intel_crtc_to_shared_dpll(intel_crtc));
 
 	/* FDI must be feeding us bits for PCH ports */
 	assert_fdi_tx_enabled(dev_priv, pipe);
@@ -3080,7 +3059,7 @@ found:
 	if (pll->active == 0) {
 		DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
 		WARN_ON(pll->on);
-		assert_shared_dpll_disabled(dev_priv, pll, NULL);
+		assert_shared_dpll_disabled(dev_priv, pll);
 
 		/* Wait for the clocks to stabilize before rewriting the regs */
 		I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
-- 
1.7.11.7

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* [PATCH 14/31] drm/i915: display pll hw state readout and checking
  2013-06-05 11:34 [PATCH 00/31] shared pch display pll rework Daniel Vetter
                   ` (12 preceding siblings ...)
  2013-06-05 11:34 ` [PATCH 13/31] drm/i915: drop crtc checking from assert_shared_dpll Daniel Vetter
@ 2013-06-05 11:34 ` Daniel Vetter
  2013-06-12 13:31   ` Damien Lespiau
  2013-06-05 11:34 ` [PATCH 15/31] drm/i915: extract readout_hw_state from setup_hw_state Daniel Vetter
                   ` (17 subsequent siblings)
  31 siblings, 1 reply; 84+ messages in thread
From: Daniel Vetter @ 2013-06-05 11:34 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

Currently still with an empty register state, this will follow in a
next step. This one here just creates the new vfunc and uses it for
cross-checking, initial state takeover and the dpll assert function.

And add a FIXME for the ddi pll readout code, which still needs to be
converted over.

v2:
- Add some hw state readout debug output.
- Also cross check the enabled crtc counting.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_drv.h      |  7 ++++
 drivers/gpu/drm/i915/intel_display.c | 77 +++++++++++++++++++++++++++++++++---
 2 files changed, 79 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8e61128..f23b033 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -143,6 +143,9 @@ enum intel_dpll_id {
 };
 #define I915_NUM_PLLS 2
 
+struct intel_dpll_hw_state {
+};
+
 struct intel_shared_dpll {
 	int refcount; /* count of number of CRTCs sharing this PLL */
 	int active; /* count of number of active CRTCs (i.e. DPMS on) */
@@ -150,10 +153,14 @@ struct intel_shared_dpll {
 	const char *name;
 	/* should match the index in the dev_priv->shared_dplls array */
 	enum intel_dpll_id id;
+	struct intel_dpll_hw_state hw_state;
 	void (*enable)(struct drm_i915_private *dev_priv,
 		       struct intel_shared_dpll *pll);
 	void (*disable)(struct drm_i915_private *dev_priv,
 			struct intel_shared_dpll *pll);
+	bool (*get_hw_state)(struct drm_i915_private *dev_priv,
+			     struct intel_shared_dpll *pll,
+			     struct intel_dpll_hw_state *hw_state);
 };
 
 /* Used by dp and fdi links */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ea4b7a6..998ba5c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -907,8 +907,8 @@ static void assert_shared_dpll(struct drm_i915_private *dev_priv,
 			       struct intel_shared_dpll *pll,
 			       bool state)
 {
-	u32 val;
 	bool cur_state;
+	struct intel_dpll_hw_state hw_state;
 
 	if (HAS_PCH_LPT(dev_priv->dev)) {
 		DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
@@ -919,11 +919,10 @@ static void assert_shared_dpll(struct drm_i915_private *dev_priv,
 		  "asserting DPLL %s with no DPLL\n", state_string(state)))
 		return;
 
-	val = I915_READ(PCH_DPLL(pll->id));
-	cur_state = !!(val & DPLL_VCO_ENABLE);
+	cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 	WARN(cur_state != state,
-	     "%s assertion failure (expected %s, current %s), val=%08x\n",
-	     pll->name, state_string(state), state_string(cur_state), val);
+	     "%s assertion failure (expected %s, current %s)\n",
+	     pll->name, state_string(state), state_string(cur_state));
 }
 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
@@ -8071,6 +8070,8 @@ intel_modeset_check_state(struct drm_device *dev)
 	struct intel_encoder *encoder;
 	struct intel_connector *connector;
 	struct intel_crtc_config pipe_config;
+	struct intel_dpll_hw_state dpll_hw_state;
+	int i;
 
 	list_for_each_entry(connector, &dev->mode_config.connector_list,
 			    base.head) {
@@ -8183,6 +8184,41 @@ intel_modeset_check_state(struct drm_device *dev)
 					       "[sw state]");
 		}
 	}
+
+	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
+		struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
+		int enabled_crtcs = 0, active_crtcs = 0;
+		bool active;
+
+		memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
+
+		DRM_DEBUG_KMS("%s\n", pll->name);
+
+		active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
+
+		WARN(pll->active > pll->refcount,
+		     "more active pll users than references: %i vs %i\n",
+		     pll->active, pll->refcount);
+		WARN(pll->active && !pll->on,
+		     "pll in active use but not on in sw tracking\n");
+		WARN(pll->on != active,
+		     "pll on state mismatch (expected %i, found %i)\n",
+		     pll->on, active);
+
+		list_for_each_entry(crtc, &dev->mode_config.crtc_list,
+				    base.head) {
+			if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
+				enabled_crtcs++;
+			if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
+				active_crtcs++;
+		}
+		WARN(pll->active != active_crtcs,
+		     "pll active crtcs mismatch (expected %i, found %i)\n",
+		     pll->active, active_crtcs);
+		WARN(pll->refcount != enabled_crtcs,
+		     "pll enabled crtcs mismatch (expected %i, found %i)\n",
+		     pll->refcount, enabled_crtcs);
+	}
 }
 
 static int __intel_set_mode(struct drm_crtc *crtc,
@@ -8621,6 +8657,17 @@ static void intel_cpu_pll_init(struct drm_device *dev)
 		intel_ddi_pll_init(dev);
 }
 
+static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
+				      struct intel_shared_dpll *pll,
+				      struct intel_dpll_hw_state *hw_state)
+{
+	uint32_t val;
+
+	val = I915_READ(PCH_DPLL(pll->id));
+
+	return val & DPLL_VCO_ENABLE;
+}
+
 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
 				struct intel_shared_dpll *pll)
 {
@@ -8675,6 +8722,8 @@ static void ibx_pch_dpll_init(struct drm_device *dev)
 		dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
 		dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
 		dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
+		dev_priv->shared_dplls[i].get_hw_state =
+			ibx_pch_dpll_get_hw_state;
 	}
 }
 
@@ -9592,6 +9641,7 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
 	struct intel_crtc *crtc;
 	struct intel_encoder *encoder;
 	struct intel_connector *connector;
+	int i;
 
 	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
 			    base.head) {
@@ -9607,9 +9657,26 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
 			      crtc->active ? "enabled" : "disabled");
 	}
 
+	/* FIXME: Smash this into the new shared dpll infrastructure. */
 	if (HAS_DDI(dev))
 		intel_ddi_setup_hw_pll_state(dev);
 
+	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
+		struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
+
+		pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
+		pll->active = 0;
+		list_for_each_entry(crtc, &dev->mode_config.crtc_list,
+				    base.head) {
+			if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
+				pll->active++;
+		}
+		pll->refcount = pll->active;
+
+		DRM_DEBUG_KMS("%s hw state readout: refcount %i\n",
+			      pll->name, pll->refcount);
+	}
+
 	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
 			    base.head) {
 		pipe = 0;
-- 
1.7.11.7

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* [PATCH 15/31] drm/i915: extract readout_hw_state from setup_hw_state
  2013-06-05 11:34 [PATCH 00/31] shared pch display pll rework Daniel Vetter
                   ` (13 preceding siblings ...)
  2013-06-05 11:34 ` [PATCH 14/31] drm/i915: display pll hw state readout and checking Daniel Vetter
@ 2013-06-05 11:34 ` Daniel Vetter
  2013-06-12 13:32   ` Damien Lespiau
  2013-06-12 14:26   ` Daniel Vetter
  2013-06-05 11:34 ` [PATCH 16/31] drm/i915: split up intel_modeset_check_state Daniel Vetter
                   ` (16 subsequent siblings)
  31 siblings, 2 replies; 84+ messages in thread
From: Daniel Vetter @ 2013-06-05 11:34 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

Simply grew too big. This also makes the fixup and restore logic in
setup_hw_state stand out a bit more clearly.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 20 +++++++++++++++-----
 1 file changed, 15 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 998ba5c..95ed27b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9630,14 +9630,10 @@ void i915_redisable_vga(struct drm_device *dev)
 	}
 }
 
-/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
- * and i915 state tracking structures. */
-void intel_modeset_setup_hw_state(struct drm_device *dev,
-				  bool force_restore)
+static void intel_modeset_readout_hw_state(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	enum pipe pipe;
-	struct drm_plane *plane;
 	struct intel_crtc *crtc;
 	struct intel_encoder *encoder;
 	struct intel_connector *connector;
@@ -9713,6 +9709,20 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
 			      drm_get_connector_name(&connector->base),
 			      connector->base.encoder ? "enabled" : "disabled");
 	}
+}
+
+/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
+ * and i915 state tracking structures. */
+void intel_modeset_setup_hw_state(struct drm_device *dev,
+				  bool force_restore)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	enum pipe pipe;
+	struct drm_plane *plane;
+	struct intel_crtc *crtc;
+	struct intel_encoder *encoder;
+
+	intel_modeset_readout_hw_state(dev);
 
 	/* HW state is read out, now we need to sanitize this mess. */
 	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
-- 
1.7.11.7

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* [PATCH 16/31] drm/i915: split up intel_modeset_check_state
  2013-06-05 11:34 [PATCH 00/31] shared pch display pll rework Daniel Vetter
                   ` (14 preceding siblings ...)
  2013-06-05 11:34 ` [PATCH 15/31] drm/i915: extract readout_hw_state from setup_hw_state Daniel Vetter
@ 2013-06-05 11:34 ` Daniel Vetter
  2013-06-12 13:33   ` Damien Lespiau
  2013-06-05 11:34 ` [PATCH 17/31] drm/i915: WARN on lack of shared dpll Daniel Vetter
                   ` (15 subsequent siblings)
  31 siblings, 1 reply; 84+ messages in thread
From: Daniel Vetter @ 2013-06-05 11:34 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

Simply grew too large and neede to be split up into parts.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 44 +++++++++++++++++++++++++++++-------
 1 file changed, 36 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 95ed27b..c42b87b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8062,16 +8062,10 @@ intel_pipe_config_compare(struct drm_device *dev,
 	return true;
 }
 
-void
-intel_modeset_check_state(struct drm_device *dev)
+static void
+check_connector_state(struct drm_device *dev)
 {
-	drm_i915_private_t *dev_priv = dev->dev_private;
-	struct intel_crtc *crtc;
-	struct intel_encoder *encoder;
 	struct intel_connector *connector;
-	struct intel_crtc_config pipe_config;
-	struct intel_dpll_hw_state dpll_hw_state;
-	int i;
 
 	list_for_each_entry(connector, &dev->mode_config.connector_list,
 			    base.head) {
@@ -8082,6 +8076,13 @@ intel_modeset_check_state(struct drm_device *dev)
 		WARN(&connector->new_encoder->base != connector->base.encoder,
 		     "connector's staged encoder doesn't match current encoder\n");
 	}
+}
+
+static void
+check_encoder_state(struct drm_device *dev)
+{
+	struct intel_encoder *encoder;
+	struct intel_connector *connector;
 
 	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
 			    base.head) {
@@ -8133,6 +8134,15 @@ intel_modeset_check_state(struct drm_device *dev)
 		     tracked_pipe, pipe);
 
 	}
+}
+
+static void
+check_crtc_state(struct drm_device *dev)
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	struct intel_crtc *crtc;
+	struct intel_encoder *encoder;
+	struct intel_crtc_config pipe_config;
 
 	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
 			    base.head) {
@@ -8184,6 +8194,15 @@ intel_modeset_check_state(struct drm_device *dev)
 					       "[sw state]");
 		}
 	}
+}
+
+static void
+check_shared_dpll_state(struct drm_device *dev)
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	struct intel_crtc *crtc;
+	struct intel_dpll_hw_state dpll_hw_state;
+	int i;
 
 	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
 		struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
@@ -8221,6 +8240,15 @@ intel_modeset_check_state(struct drm_device *dev)
 	}
 }
 
+void
+intel_modeset_check_state(struct drm_device *dev)
+{
+	check_connector_state(dev);
+	check_encoder_state(dev);
+	check_crtc_state(dev);
+	check_shared_dpll_state(dev);
+}
+
 static int __intel_set_mode(struct drm_crtc *crtc,
 			    struct drm_display_mode *mode,
 			    int x, int y, struct drm_framebuffer *fb)
-- 
1.7.11.7

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* [PATCH 17/31] drm/i915: WARN on lack of shared dpll
  2013-06-05 11:34 [PATCH 00/31] shared pch display pll rework Daniel Vetter
                   ` (15 preceding siblings ...)
  2013-06-05 11:34 ` [PATCH 16/31] drm/i915: split up intel_modeset_check_state Daniel Vetter
@ 2013-06-05 11:34 ` Daniel Vetter
  2013-06-12 13:38   ` Damien Lespiau
  2013-06-05 11:34 ` [PATCH 18/31] drm/i915: hw state readout and cross-checking for shared dplls Daniel Vetter
                   ` (14 subsequent siblings)
  31 siblings, 1 reply; 84+ messages in thread
From: Daniel Vetter @ 2013-06-05 11:34 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

Now that we have proper hw state reconstruction we should never have a
case where we don't have the software dpll state properly set up. So
add WARNs to the respective !pll cases in enable/disabel_shared_dpll.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c42b87b..388ac54 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1371,7 +1371,7 @@ static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
 
 	/* PCH PLLs only available on ILK, SNB and IVB */
 	BUG_ON(dev_priv->info->gen < 5);
-	if (pll == NULL)
+	if (WARN_ON(pll == NULL))
 		return;
 
 	if (WARN_ON(pll->refcount == 0))
@@ -1399,7 +1399,7 @@ static void intel_disable_shared_dpll(struct intel_crtc *crtc)
 
 	/* PCH only available on ILK+ */
 	BUG_ON(dev_priv->info->gen < 5);
-	if (pll == NULL)
+	if (WARN_ON(pll == NULL))
 	       return;
 
 	if (WARN_ON(pll->refcount == 0))
-- 
1.7.11.7

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* [PATCH 18/31] drm/i915: hw state readout and cross-checking for shared dplls
  2013-06-05 11:34 [PATCH 00/31] shared pch display pll rework Daniel Vetter
                   ` (16 preceding siblings ...)
  2013-06-05 11:34 ` [PATCH 17/31] drm/i915: WARN on lack of shared dpll Daniel Vetter
@ 2013-06-05 11:34 ` Daniel Vetter
  2013-06-12 15:04   ` Damien Lespiau
  2013-06-05 11:34 ` [PATCH 19/31] drm/i915: fix up pch pll enabling for pixel multipliers Daniel Vetter
                   ` (13 subsequent siblings)
  31 siblings, 1 reply; 84+ messages in thread
From: Daniel Vetter @ 2013-06-05 11:34 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

Just the plumbing, all the modeset and enable code has not yet been
switched over to use the new state. It seems to be decently broken
anyway, at least wrt to handling of the special pixel mutliplier
enabling sequence. Follow-up patches will clean up that mess.

Another missing piece is more careful handling (and fixup) of the fp1
alternate divisor state. The BIOS most likely doesn't bother to
program that one to what we expect. So we need to be more careful with
comparing that state, both for cross checking but also when checking
for dpll sharing when acquiring shared dpll. Otherwise fastboot will
deny a few shared dpll configurations which would otherwise work.

v2: We need to memcpy the pipe config dpll hw state into the pll, for
otherwise the cross-check code will get angry.

v3: Don't forget to read the pch pll state in the crtc get_pipe_config
function for ibx/ilk platforms.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_drv.h      |  3 +++
 drivers/gpu/drm/i915/intel_display.c | 38 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h     |  3 +++
 3 files changed, 44 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f23b033..4dc94ed 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -144,6 +144,9 @@ enum intel_dpll_id {
 #define I915_NUM_PLLS 2
 
 struct intel_dpll_hw_state {
+	uint32_t dpll;
+	uint32_t fp0;
+	uint32_t fp1;
 };
 
 struct intel_shared_dpll {
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 388ac54..a30e27a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3055,7 +3055,11 @@ found:
 	crtc->config.shared_dpll = i;
 	DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
 			 pipe_name(crtc->pipe));
+
 	if (pll->active == 0) {
+		memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
+		       sizeof(pll->hw_state));
+
 		DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
 		WARN_ON(pll->on);
 		assert_shared_dpll_disabled(dev_priv, pll);
@@ -5659,6 +5663,13 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 					     &fp, &reduced_clock,
 					     has_reduced_clock ? &fp2 : NULL);
 
+		intel_crtc->config.dpll_hw_state.dpll = dpll | DPLL_VCO_ENABLE;
+		intel_crtc->config.dpll_hw_state.fp0 = fp;
+		if (has_reduced_clock)
+			intel_crtc->config.dpll_hw_state.fp1 = fp2;
+		else
+			intel_crtc->config.dpll_hw_state.fp1 = fp;
+
 		pll = intel_get_shared_dpll(intel_crtc, dpll, fp);
 		if (pll == NULL) {
 			DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
@@ -5778,6 +5789,8 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
 		return false;
 
 	if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
+		struct intel_shared_dpll *pll;
+
 		pipe_config->has_pch_encoder = true;
 
 		tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
@@ -5799,6 +5812,11 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
 			else
 				pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
 		}
+
+		pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
+
+		WARN_ON(!pll->get_hw_state(dev_priv, pll,
+					   &pipe_config->dpll_hw_state));
 	} else {
 		pipe_config->pixel_multiplier = 1;
 	}
@@ -7987,6 +8005,15 @@ intel_pipe_config_compare(struct drm_device *dev,
 			  struct intel_crtc_config *current_config,
 			  struct intel_crtc_config *pipe_config)
 {
+#define PIPE_CONF_CHECK_X(name)	\
+	if (current_config->name != pipe_config->name) { \
+		DRM_ERROR("mismatch in " #name " " \
+			  "(expected 0x%08x, found 0x%08x)\n", \
+			  current_config->name, \
+			  pipe_config->name); \
+		return false; \
+	}
+
 #define PIPE_CONF_CHECK_I(name)	\
 	if (current_config->name != pipe_config->name) { \
 		DRM_ERROR("mismatch in " #name " " \
@@ -8055,7 +8082,11 @@ intel_pipe_config_compare(struct drm_device *dev,
 	PIPE_CONF_CHECK_I(ips_enabled);
 
 	PIPE_CONF_CHECK_I(shared_dpll);
+	PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
+	PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
+	PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
 
+#undef PIPE_CONF_CHECK_X
 #undef PIPE_CONF_CHECK_I
 #undef PIPE_CONF_CHECK_FLAGS
 
@@ -8237,6 +8268,10 @@ check_shared_dpll_state(struct drm_device *dev)
 		WARN(pll->refcount != enabled_crtcs,
 		     "pll enabled crtcs mismatch (expected %i, found %i)\n",
 		     pll->refcount, enabled_crtcs);
+
+		WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
+				       sizeof(dpll_hw_state)),
+		     "pll hw state mismatch\n");
 	}
 }
 
@@ -8692,6 +8727,9 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
 	uint32_t val;
 
 	val = I915_READ(PCH_DPLL(pll->id));
+	hw_state->dpll = val;
+	hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
+	hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
 
 	return val & DPLL_VCO_ENABLE;
 }
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index e0e5d55..6f28375 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -244,6 +244,9 @@ struct intel_crtc_config {
 	/* Selected dpll when shared or DPLL_ID_PRIVATE. */
 	enum intel_dpll_id shared_dpll;
 
+	/* Actual register state of the dpll, for shared dpll cross-checking. */
+	struct intel_dpll_hw_state dpll_hw_state;
+
 	int pipe_bpp;
 	struct intel_link_m_n dp_m_n;
 
-- 
1.7.11.7

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* [PATCH 19/31] drm/i915: fix up pch pll enabling for pixel multipliers
  2013-06-05 11:34 [PATCH 00/31] shared pch display pll rework Daniel Vetter
                   ` (17 preceding siblings ...)
  2013-06-05 11:34 ` [PATCH 18/31] drm/i915: hw state readout and cross-checking for shared dplls Daniel Vetter
@ 2013-06-05 11:34 ` Daniel Vetter
  2013-06-12 15:12   ` Damien Lespiau
  2013-06-05 11:34 ` [PATCH 20/31] drm/i915: simplify the reduced clock handling for pch plls Daniel Vetter
                   ` (12 subsequent siblings)
  31 siblings, 1 reply; 84+ messages in thread
From: Daniel Vetter @ 2013-06-05 11:34 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

We have a nice comment saying that the pixel multiplier only sticks
once the vco is on and stable. The only problem is that the enable bit
wasn't set at all. This patch fixes this and so brings the ilk+ pch
pll code in line with the i8xx/i9xx pll code. Or at least improves
matters a lot.

This should fix sdvo on ilk-ivb for low-res modes.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a30e27a..ecf0b1e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5601,7 +5601,7 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
 	else
 		dpll |= PLL_REF_INPUT_DREFCLK;
 
-	return dpll;
+	return dpll | DPLL_VCO_ENABLE;
 }
 
 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
@@ -5663,7 +5663,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 					     &fp, &reduced_clock,
 					     has_reduced_clock ? &fp2 : NULL);
 
-		intel_crtc->config.dpll_hw_state.dpll = dpll | DPLL_VCO_ENABLE;
+		intel_crtc->config.dpll_hw_state.dpll = dpll;
 		intel_crtc->config.dpll_hw_state.fp0 = fp;
 		if (has_reduced_clock)
 			intel_crtc->config.dpll_hw_state.fp1 = fp2;
-- 
1.7.11.7

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* [PATCH 20/31] drm/i915: simplify the reduced clock handling for pch plls
  2013-06-05 11:34 [PATCH 00/31] shared pch display pll rework Daniel Vetter
                   ` (18 preceding siblings ...)
  2013-06-05 11:34 ` [PATCH 19/31] drm/i915: fix up pch pll enabling for pixel multipliers Daniel Vetter
@ 2013-06-05 11:34 ` Daniel Vetter
  2013-06-13 11:26   ` Damien Lespiau
  2013-06-05 11:34 ` [PATCH 21/31] drm/i915: consolidate pch pll enable sequence Daniel Vetter
                   ` (11 subsequent siblings)
  31 siblings, 1 reply; 84+ messages in thread
From: Daniel Vetter @ 2013-06-05 11:34 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

Just move the lowfreq_avail logic out of the register writing as a
prep step for the next patch, which will coalesce all the pch pll
enabling into one spot.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ecf0b1e..fc1b5f7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5686,7 +5686,10 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 		if (encoder->pre_pll_enable)
 			encoder->pre_pll_enable(encoder);
 
-	intel_crtc->lowfreq_avail = false;
+	if (is_lvds && has_reduced_clock && i915_powersave)
+		intel_crtc->lowfreq_avail = true;
+	else
+		intel_crtc->lowfreq_avail = false;
 
 	if (intel_crtc->config.has_pch_encoder) {
 		pll = intel_crtc_to_shared_dpll(intel_crtc);
@@ -5704,12 +5707,10 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 		 */
 		I915_WRITE(PCH_DPLL(pll->id), dpll);
 
-		if (is_lvds && has_reduced_clock && i915_powersave) {
+		if (has_reduced_clock)
 			I915_WRITE(PCH_FP1(pll->id), fp2);
-			intel_crtc->lowfreq_avail = true;
-		} else {
+		else
 			I915_WRITE(PCH_FP1(pll->id), fp);
-		}
 	}
 
 	intel_set_pipe_timings(intel_crtc);
-- 
1.7.11.7

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* [PATCH 21/31] drm/i915: consolidate pch pll enable sequence
  2013-06-05 11:34 [PATCH 00/31] shared pch display pll rework Daniel Vetter
                   ` (19 preceding siblings ...)
  2013-06-05 11:34 ` [PATCH 20/31] drm/i915: simplify the reduced clock handling for pch plls Daniel Vetter
@ 2013-06-05 11:34 ` Daniel Vetter
  2013-06-24 14:30   ` Damien Lespiau
  2013-06-05 11:34 ` [PATCH 22/31] drm/i915: use sw tracked state to select shared dplls Daniel Vetter
                   ` (10 subsequent siblings)
  31 siblings, 1 reply; 84+ messages in thread
From: Daniel Vetter @ 2013-06-05 11:34 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

It's been splattered over 3 different places all doing random things.
Now we have (mostly) the same sequence as i8xx/i9xx, but all called
from the crtc_enable hook (through the pll->enable function):
- write new dividers
- enable vco and wait for stable clocks
- write again for the pixel mutliplier

I've left the seemingly random 200 usec delay in there, just in case.

Also move the encoder->pre_pll_enable hook into the crtc_enable
function, at the same spot we currently have a hack to enable the lvds
port. Since that hack is now redundant, kill it.

While doing this patch I've learned the hard way that we can only fire
up the LVDS port if both the pch dpll _and_ the fdi rc pll are not yet
enabled. Otherwise things go haywire, at least on cpt.

v2: It is paramount to write the FPx divisors before we enable the
the vco by writing to the DPLL registers, for otherwise the divisors
won't get updated. This is in line with the i8xx/i9xx dpll.

v3: To keep the nice abstraction add a ->mode_set callback to set the
divisors. Also streamline the enabling/disabling code a bit by
removing some cargo-cult duplication and clearing registers where
possible in the ->disable hook.

v4: Remove now unused local variable.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_drv.h      |  2 +
 drivers/gpu/drm/i915/intel_display.c | 75 +++++++++++++-----------------------
 2 files changed, 29 insertions(+), 48 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4dc94ed..9fc1ea4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -157,6 +157,8 @@ struct intel_shared_dpll {
 	/* should match the index in the dev_priv->shared_dplls array */
 	enum intel_dpll_id id;
 	struct intel_dpll_hw_state hw_state;
+	void (*mode_set)(struct drm_i915_private *dev_priv,
+			 struct intel_shared_dpll *pll);
 	void (*enable)(struct drm_i915_private *dev_priv,
 		       struct intel_shared_dpll *pll);
 	void (*disable)(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index fc1b5f7..334f86a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3064,13 +3064,7 @@ found:
 		WARN_ON(pll->on);
 		assert_shared_dpll_disabled(dev_priv, pll);
 
-		/* Wait for the clocks to stabilize before rewriting the regs */
-		I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
-		POSTING_READ(PCH_DPLL(pll->id));
-		udelay(150);
-
-		I915_WRITE(PCH_FP0(pll->id), fp);
-		I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
+		pll->mode_set(dev_priv, pll);
 	}
 	pll->refcount++;
 
@@ -3120,7 +3114,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
 	struct intel_encoder *encoder;
 	int pipe = intel_crtc->pipe;
 	int plane = intel_crtc->plane;
-	u32 temp;
 
 	WARN_ON(!crtc->enabled);
 
@@ -3134,12 +3127,9 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
 
 	intel_update_watermarks(dev);
 
-	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
-		temp = I915_READ(PCH_LVDS);
-		if ((temp & LVDS_PORT_EN) == 0)
-			I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
-	}
-
+	for_each_encoder_on_crtc(dev, crtc, encoder)
+		if (encoder->pre_pll_enable)
+			encoder->pre_pll_enable(encoder);
 
 	if (intel_crtc->config.has_pch_encoder) {
 		/* Note: FDI PLL enabling _must_ be done before we enable the
@@ -5682,10 +5672,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 	if (intel_crtc->config.has_dp_encoder)
 		intel_dp_set_m_n(intel_crtc);
 
-	for_each_encoder_on_crtc(dev, crtc, encoder)
-		if (encoder->pre_pll_enable)
-			encoder->pre_pll_enable(encoder);
-
 	if (is_lvds && has_reduced_clock && i915_powersave)
 		intel_crtc->lowfreq_avail = true;
 	else
@@ -5694,23 +5680,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 	if (intel_crtc->config.has_pch_encoder) {
 		pll = intel_crtc_to_shared_dpll(intel_crtc);
 
-		I915_WRITE(PCH_DPLL(pll->id), dpll);
-
-		/* Wait for the clocks to stabilize. */
-		POSTING_READ(PCH_DPLL(pll->id));
-		udelay(150);
-
-		/* The pixel multiplier can only be updated once the
-		 * DPLL is enabled and the clocks are stable.
-		 *
-		 * So write it again.
-		 */
-		I915_WRITE(PCH_DPLL(pll->id), dpll);
-
-		if (has_reduced_clock)
-			I915_WRITE(PCH_FP1(pll->id), fp2);
-		else
-			I915_WRITE(PCH_FP1(pll->id), fp);
 	}
 
 	intel_set_pipe_timings(intel_crtc);
@@ -8735,19 +8704,32 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
 	return val & DPLL_VCO_ENABLE;
 }
 
+static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
+				  struct intel_shared_dpll *pll)
+{
+	I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
+	I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
+}
+
 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
 				struct intel_shared_dpll *pll)
 {
-	uint32_t reg, val;
-
 	/* PCH refclock must be enabled first */
 	assert_pch_refclk_enabled(dev_priv);
 
-	reg = PCH_DPLL(pll->id);
-	val = I915_READ(reg);
-	val |= DPLL_VCO_ENABLE;
-	I915_WRITE(reg, val);
-	POSTING_READ(reg);
+	I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
+
+	/* Wait for the clocks to stabilize. */
+	POSTING_READ(PCH_DPLL(pll->id));
+	udelay(150);
+
+	/* The pixel multiplier can only be updated once the
+	 * DPLL is enabled and the clocks are stable.
+	 *
+	 * So write it again.
+	 */
+	I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
+	POSTING_READ(PCH_DPLL(pll->id));
 	udelay(200);
 }
 
@@ -8756,7 +8738,6 @@ static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
 {
 	struct drm_device *dev = dev_priv->dev;
 	struct intel_crtc *crtc;
-	uint32_t reg, val;
 
 	/* Make sure no transcoder isn't still depending on us. */
 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
@@ -8764,11 +8745,8 @@ static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
 			assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
 	}
 
-	reg = PCH_DPLL(pll->id);
-	val = I915_READ(reg);
-	val &= ~DPLL_VCO_ENABLE;
-	I915_WRITE(reg, val);
-	POSTING_READ(reg);
+	I915_WRITE(PCH_DPLL(pll->id), 0);
+	POSTING_READ(PCH_DPLL(pll->id));
 	udelay(200);
 }
 
@@ -8787,6 +8765,7 @@ static void ibx_pch_dpll_init(struct drm_device *dev)
 	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
 		dev_priv->shared_dplls[i].id = i;
 		dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
+		dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
 		dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
 		dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
 		dev_priv->shared_dplls[i].get_hw_state =
-- 
1.7.11.7

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* [PATCH 22/31] drm/i915: use sw tracked state to select shared dplls
  2013-06-05 11:34 [PATCH 00/31] shared pch display pll rework Daniel Vetter
                   ` (20 preceding siblings ...)
  2013-06-05 11:34 ` [PATCH 21/31] drm/i915: consolidate pch pll enable sequence Daniel Vetter
@ 2013-06-05 11:34 ` Daniel Vetter
  2013-06-12 15:20   ` Damien Lespiau
  2013-06-05 11:34 ` [PATCH 23/31] drm/i915: duplicate intel_enable_pll into i9xx and vlv versions Daniel Vetter
                   ` (9 subsequent siblings)
  31 siblings, 1 reply; 84+ messages in thread
From: Daniel Vetter @ 2013-06-05 11:34 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

Just yet another prep step to be able to do all this up-front, before
we've set up any of the shared dplls in the new state. This will
eventually be useful for atomic modesetting.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 334f86a..4d2284e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2999,7 +2999,7 @@ static void intel_put_shared_dpll(struct intel_crtc *crtc)
 	crtc->config.shared_dpll = DPLL_ID_NONE;
 }
 
-static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, u32 dpll, u32 fp)
+static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
@@ -3029,8 +3029,8 @@ static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
 		if (pll->refcount == 0)
 			continue;
 
-		if (dpll == (I915_READ(PCH_DPLL(pll->id)) & 0x7fffffff) &&
-		    fp == I915_READ(PCH_FP0(pll->id))) {
+		if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
+			   sizeof(pll->hw_state)) == 0) {
 			DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
 				      crtc->base.base.id,
 				      pll->name, pll->refcount, pll->active);
@@ -5660,7 +5660,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 		else
 			intel_crtc->config.dpll_hw_state.fp1 = fp;
 
-		pll = intel_get_shared_dpll(intel_crtc, dpll, fp);
+		pll = intel_get_shared_dpll(intel_crtc);
 		if (pll == NULL) {
 			DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
 					 pipe_name(pipe));
-- 
1.7.11.7

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* [PATCH 23/31] drm/i915: duplicate intel_enable_pll into i9xx and vlv versions
  2013-06-05 11:34 [PATCH 00/31] shared pch display pll rework Daniel Vetter
                   ` (21 preceding siblings ...)
  2013-06-05 11:34 ` [PATCH 22/31] drm/i915: use sw tracked state to select shared dplls Daniel Vetter
@ 2013-06-05 11:34 ` Daniel Vetter
  2013-06-05 15:12   ` Jani Nikula
  2013-06-05 11:34 ` [PATCH 24/31] drm/i915: asserts for lvds pre_enable Daniel Vetter
                   ` (8 subsequent siblings)
  31 siblings, 1 reply; 84+ messages in thread
From: Daniel Vetter @ 2013-06-05 11:34 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

Mostly since I _really_ don't want to touch the vlv hell.

No code change, just duplication. Also kill a now seriously outdated
code comment - the remark about the dvo encoder is now handled with
the pipe A quirk.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 49 ++++++++++++++++++++++++------------
 1 file changed, 33 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4d2284e..5d84fea 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1271,20 +1271,37 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
 	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
 }
 
-/**
- * intel_enable_pll - enable a PLL
- * @dev_priv: i915 private structure
- * @pipe: pipe PLL to enable
- *
- * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
- * make sure the PLL reg is writable first though, since the panel write
- * protect mechanism may be enabled.
- *
- * Note!  This is for pre-ILK only.
- *
- * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
- */
-static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
+static void vlv_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
+{
+	int reg;
+	u32 val;
+
+	assert_pipe_disabled(dev_priv, pipe);
+
+	/* No really, not for ILK+ */
+	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
+
+	/* PLL is protected by panel, make sure we can write it */
+	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
+		assert_panel_unlocked(dev_priv, pipe);
+
+	reg = DPLL(pipe);
+	val = I915_READ(reg);
+	val |= DPLL_VCO_ENABLE;
+
+	/* We do this three times for luck */
+	I915_WRITE(reg, val);
+	POSTING_READ(reg);
+	udelay(150); /* wait for warmup */
+	I915_WRITE(reg, val);
+	POSTING_READ(reg);
+	udelay(150); /* wait for warmup */
+	I915_WRITE(reg, val);
+	POSTING_READ(reg);
+	udelay(150); /* wait for warmup */
+}
+
+static void i9xx_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
 {
 	int reg;
 	u32 val;
@@ -3535,7 +3552,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
 		if (encoder->pre_pll_enable)
 			encoder->pre_pll_enable(encoder);
 
-	intel_enable_pll(dev_priv, pipe);
+	vlv_enable_pll(dev_priv, pipe);
 
 	for_each_encoder_on_crtc(dev, crtc, encoder)
 		if (encoder->pre_enable)
@@ -3578,7 +3595,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
 	intel_crtc->active = true;
 	intel_update_watermarks(dev);
 
-	intel_enable_pll(dev_priv, pipe);
+	i9xx_enable_pll(dev_priv, pipe);
 
 	for_each_encoder_on_crtc(dev, crtc, encoder)
 		if (encoder->pre_enable)
-- 
1.7.11.7

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* [PATCH 24/31] drm/i915: asserts for lvds pre_enable
  2013-06-05 11:34 [PATCH 00/31] shared pch display pll rework Daniel Vetter
                   ` (22 preceding siblings ...)
  2013-06-05 11:34 ` [PATCH 23/31] drm/i915: duplicate intel_enable_pll into i9xx and vlv versions Daniel Vetter
@ 2013-06-05 11:34 ` Daniel Vetter
  2013-06-13 20:26   ` Imre Deak
  2013-06-05 11:34 ` [PATCH 25/31] drm/i915: move encoder pre enable hooks togther on ilk+ Daniel Vetter
                   ` (7 subsequent siblings)
  31 siblings, 1 reply; 84+ messages in thread
From: Daniel Vetter @ 2013-06-05 11:34 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

Lots of bangin my head against the wall^UExperiments have shown that
we really need to enable the lvds port before we enable plls. Strangely
that seems to include the fdi rx pll on the pch.

Anyway, encode this new evidence with a few nice WARNs.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 23 ++++++++++-------------
 drivers/gpu/drm/i915/intel_drv.h     | 16 ++++++++++++++++
 drivers/gpu/drm/i915/intel_lvds.c    | 17 ++++++++++++-----
 3 files changed, 38 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5d84fea..7b34a92 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -874,8 +874,8 @@ static const char *state_string(bool enabled)
 }
 
 /* Only for pre-ILK configs */
-static void assert_pll(struct drm_i915_private *dev_priv,
-		       enum pipe pipe, bool state)
+void assert_pll(struct drm_i915_private *dev_priv,
+		enum pipe pipe, bool state)
 {
 	int reg;
 	u32 val;
@@ -888,10 +888,8 @@ static void assert_pll(struct drm_i915_private *dev_priv,
 	     "PLL state assertion failure (expected %s, current %s)\n",
 	     state_string(state), state_string(cur_state));
 }
-#define assert_pll_enabled(d, p) assert_pll(d, p, true)
-#define assert_pll_disabled(d, p) assert_pll(d, p, false)
 
-static struct intel_shared_dpll *
+struct intel_shared_dpll *
 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
@@ -903,9 +901,9 @@ intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 }
 
 /* For ILK+ */
-static void assert_shared_dpll(struct drm_i915_private *dev_priv,
-			       struct intel_shared_dpll *pll,
-			       bool state)
+void assert_shared_dpll(struct drm_i915_private *dev_priv,
+			struct intel_shared_dpll *pll,
+			bool state)
 {
 	bool cur_state;
 	struct intel_dpll_hw_state hw_state;
@@ -924,8 +922,6 @@ static void assert_shared_dpll(struct drm_i915_private *dev_priv,
 	     "%s assertion failure (expected %s, current %s)\n",
 	     pll->name, state_string(state), state_string(cur_state));
 }
-#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
-#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
 
 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 			  enum pipe pipe, bool state)
@@ -989,15 +985,16 @@ static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 	WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
 }
 
-static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
-				      enum pipe pipe)
+void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
+		       enum pipe pipe, bool state)
 {
 	int reg;
 	u32 val;
 
 	reg = FDI_RX_CTL(pipe);
 	val = I915_READ(reg);
-	WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
+	WARN(!!(val & FDI_RX_PLL_ENABLE) != state,
+	     "FDI RX PLL assertion failure, should be active but is disabled\n");
 }
 
 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 6f28375..ea8aa5e 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -732,6 +732,22 @@ extern int intel_overlay_attrs(struct drm_device *dev, void *data,
 extern void intel_fb_output_poll_changed(struct drm_device *dev);
 extern void intel_fb_restore_mode(struct drm_device *dev);
 
+struct intel_shared_dpll *
+intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
+
+void assert_shared_dpll(struct drm_i915_private *dev_priv,
+			struct intel_shared_dpll *pll,
+			bool state);
+#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
+#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
+void assert_pll(struct drm_i915_private *dev_priv,
+		enum pipe pipe, bool state);
+#define assert_pll_enabled(d, p) assert_pll(d, p, true)
+#define assert_pll_disabled(d, p) assert_pll(d, p, false)
+void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
+		       enum pipe pipe, bool state);
+#define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
+#define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
 extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
 			bool state);
 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 159aa9f..36f8901 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -120,12 +120,20 @@ static void intel_pre_pll_enable_lvds(struct intel_encoder *encoder)
 	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 	struct drm_device *dev = encoder->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 	struct drm_display_mode *fixed_mode =
 		lvds_encoder->attached_connector->base.panel.fixed_mode;
-	int pipe = intel_crtc->pipe;
+	int pipe = crtc->pipe;
 	u32 temp;
 
+	if (HAS_PCH_SPLIT(dev)) {
+		assert_fdi_rx_pll_disabled(dev_priv, pipe);
+		assert_shared_dpll_disabled(dev_priv,
+					    intel_crtc_to_shared_dpll(crtc));
+	} else {
+		assert_pll_disabled(dev_priv, pipe);
+	}
+
 	temp = I915_READ(lvds_encoder->reg);
 	temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
 
@@ -142,7 +150,7 @@ static void intel_pre_pll_enable_lvds(struct intel_encoder *encoder)
 
 	/* set the corresponsding LVDS_BORDER bit */
 	temp &= ~LVDS_BORDER_ENABLE;
-	temp |= intel_crtc->config.gmch_pfit.lvds_border_bits;
+	temp |= crtc->config.gmch_pfit.lvds_border_bits;
 	/* Set the B0-B3 data pairs corresponding to whether we're going to
 	 * set the DPLLs for dual-channel mode or not.
 	 */
@@ -162,8 +170,7 @@ static void intel_pre_pll_enable_lvds(struct intel_encoder *encoder)
 	if (INTEL_INFO(dev)->gen == 4) {
 		/* Bspec wording suggests that LVDS port dithering only exists
 		 * for 18bpp panels. */
-		if (intel_crtc->config.dither &&
-		    intel_crtc->config.pipe_bpp == 18)
+		if (crtc->config.dither && crtc->config.pipe_bpp == 18)
 			temp |= LVDS_ENABLE_DITHER;
 		else
 			temp &= ~LVDS_ENABLE_DITHER;
-- 
1.7.11.7

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* [PATCH 25/31] drm/i915: move encoder pre enable hooks togther on ilk+
  2013-06-05 11:34 [PATCH 00/31] shared pch display pll rework Daniel Vetter
                   ` (23 preceding siblings ...)
  2013-06-05 11:34 ` [PATCH 24/31] drm/i915: asserts for lvds pre_enable Daniel Vetter
@ 2013-06-05 11:34 ` Daniel Vetter
  2013-06-05 11:34 ` [PATCH 26/31] drm/i915: hw state readout for i9xx dplls Daniel Vetter
                   ` (6 subsequent siblings)
  31 siblings, 0 replies; 84+ messages in thread
From: Daniel Vetter @ 2013-06-05 11:34 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

The ->pre_enable hook is only used for the cpu edp port on ilk-ivb, so
we can safely move it up across the fdi pll enabling.

Unfortunately we can't (yet) merge in the pre_pll enable hook despite
that only lvds uses it on ilk-ivb: Since the same lvds hook is also
need on i9xx platforms we need to fix up the pll enabling sequence
there, too.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7b34a92..b092160 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3141,9 +3141,12 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
 
 	intel_update_watermarks(dev);
 
-	for_each_encoder_on_crtc(dev, crtc, encoder)
+	for_each_encoder_on_crtc(dev, crtc, encoder) {
 		if (encoder->pre_pll_enable)
 			encoder->pre_pll_enable(encoder);
+		if (encoder->pre_enable)
+			encoder->pre_enable(encoder);
+	}
 
 	if (intel_crtc->config.has_pch_encoder) {
 		/* Note: FDI PLL enabling _must_ be done before we enable the
@@ -3155,10 +3158,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
 		assert_fdi_rx_disabled(dev_priv, pipe);
 	}
 
-	for_each_encoder_on_crtc(dev, crtc, encoder)
-		if (encoder->pre_enable)
-			encoder->pre_enable(encoder);
-
 	/* Enable panel fitting for LVDS */
 	ironlake_pfit_enable(intel_crtc);
 
-- 
1.7.11.7

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* [PATCH 26/31] drm/i915: hw state readout for i9xx dplls
  2013-06-05 11:34 [PATCH 00/31] shared pch display pll rework Daniel Vetter
                   ` (24 preceding siblings ...)
  2013-06-05 11:34 ` [PATCH 25/31] drm/i915: move encoder pre enable hooks togther on ilk+ Daniel Vetter
@ 2013-06-05 11:34 ` Daniel Vetter
  2013-06-05 11:34 ` [PATCH 27/31] drm/i915: move i9xx dpll enabling into crtc enable function Daniel Vetter
                   ` (5 subsequent siblings)
  31 siblings, 0 replies; 84+ messages in thread
From: Daniel Vetter @ 2013-06-05 11:34 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

In addition to existing stuff we also need to track DPLL_MD on gen4
and vlv. This is prep work so that we can move the dpll enable
sequence out from the ->mode_set callback into the crtc enabling
functions.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_drv.h      |  1 +
 drivers/gpu/drm/i915/intel_display.c | 20 ++++++++++++++++++++
 2 files changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9fc1ea4..e2ce27a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -145,6 +145,7 @@ enum intel_dpll_id {
 
 struct intel_dpll_hw_state {
 	uint32_t dpll;
+	uint32_t dpll_md;
 	uint32_t fp0;
 	uint32_t fp1;
 };
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b092160..b9be047 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4214,14 +4214,17 @@ static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
 	}
 
 	I915_WRITE(FP0(pipe), fp);
+	crtc->config.dpll_hw_state.fp0 = fp;
 
 	crtc->lowfreq_avail = false;
 	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
 	    reduced_clock && i915_powersave) {
 		I915_WRITE(FP1(pipe), fp2);
+		crtc->config.dpll_hw_state.fp1 = fp2;
 		crtc->lowfreq_avail = true;
 	} else {
 		I915_WRITE(FP1(pipe), fp);
+		crtc->config.dpll_hw_state.fp1 = fp;
 	}
 }
 
@@ -4398,6 +4401,8 @@ static void vlv_update_pll(struct intel_crtc *crtc)
 		dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
 
 	dpll |= DPLL_VCO_ENABLE;
+	crtc->config.dpll_hw_state.dpll = dpll;
+
 	I915_WRITE(DPLL(pipe), dpll);
 	POSTING_READ(DPLL(pipe));
 	udelay(150);
@@ -4407,6 +4412,8 @@ static void vlv_update_pll(struct intel_crtc *crtc)
 
 	dpll_md = (crtc->config.pixel_multiplier - 1)
 		<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
+	crtc->config.dpll_hw_state.dpll_md = dpll_md;
+
 	I915_WRITE(DPLL_MD(pipe), dpll_md);
 	POSTING_READ(DPLL_MD(pipe));
 
@@ -4485,6 +4492,8 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
 		dpll |= PLL_REF_INPUT_DREFCLK;
 
 	dpll |= DPLL_VCO_ENABLE;
+	crtc->config.dpll_hw_state.dpll = dpll;
+
 	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
 	POSTING_READ(DPLL(pipe));
 	udelay(150);
@@ -4505,6 +4514,8 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
 	if (INTEL_INFO(dev)->gen >= 4) {
 		u32 dpll_md = (crtc->config.pixel_multiplier - 1)
 			<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
+		crtc->config.dpll_hw_state.dpll_md = dpll_md;
+
 		I915_WRITE(DPLL_MD(pipe), dpll_md);
 	} else {
 		/* The pixel multiplier can only be updated once the
@@ -4549,6 +4560,8 @@ static void i8xx_update_pll(struct intel_crtc *crtc,
 		dpll |= PLL_REF_INPUT_DREFCLK;
 
 	dpll |= DPLL_VCO_ENABLE;
+	crtc->config.dpll_hw_state.dpll = dpll;
+
 	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
 	POSTING_READ(DPLL(pipe));
 	udelay(150);
@@ -4916,6 +4929,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
 		pipe_config->pixel_multiplier =
 			((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
 			 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
+		pipe_config->dpll_hw_state.dpll_md = tmp;
 	} else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
 		tmp = I915_READ(DPLL(crtc->pipe));
 		pipe_config->pixel_multiplier =
@@ -4927,6 +4941,11 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
 		 * function. */
 		pipe_config->pixel_multiplier = 1;
 	}
+	pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
+	if (!IS_VALLEYVIEW(dev)) {
+		pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
+		pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
+	}
 
 	return true;
 }
@@ -8066,6 +8085,7 @@ intel_pipe_config_compare(struct drm_device *dev,
 
 	PIPE_CONF_CHECK_I(shared_dpll);
 	PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
+	PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
 	PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
 	PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
 
-- 
1.7.11.7

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* [PATCH 27/31] drm/i915: move i9xx dpll enabling into crtc enable function
  2013-06-05 11:34 [PATCH 00/31] shared pch display pll rework Daniel Vetter
                   ` (25 preceding siblings ...)
  2013-06-05 11:34 ` [PATCH 26/31] drm/i915: hw state readout for i9xx dplls Daniel Vetter
@ 2013-06-05 11:34 ` Daniel Vetter
  2013-06-05 15:13   ` Jani Nikula
  2013-06-14 16:02   ` [PATCH 27/31] " Imre Deak
  2013-06-05 11:34 ` [PATCH 28/31] drm/i915: s/pre_pll/pre/ on the lvds port " Daniel Vetter
                   ` (4 subsequent siblings)
  31 siblings, 2 replies; 84+ messages in thread
From: Daniel Vetter @ 2013-06-05 11:34 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

Now that we have the proper pipe config to track this, we don't need
to write any registers any more.

v2: Drop a few now unnecessary local variables and switch the enable
function to take a struct intel_crtc * to simply arguments.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 102 +++++++++++++----------------------
 1 file changed, 37 insertions(+), 65 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b9be047..b6f5e48 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1298,32 +1298,48 @@ static void vlv_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
 	udelay(150); /* wait for warmup */
 }
 
-static void i9xx_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
+static void i9xx_enable_pll(struct intel_crtc *crtc)
 {
-	int reg;
-	u32 val;
+	struct drm_device *dev = crtc->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int reg = DPLL(crtc->pipe);
+	u32 dpll = crtc->config.dpll_hw_state.dpll;
 
-	assert_pipe_disabled(dev_priv, pipe);
+	assert_pipe_disabled(dev_priv, crtc->pipe);
 
 	/* No really, not for ILK+ */
-	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
+	BUG_ON(!IS_VALLEYVIEW(dev) && dev_priv->info->gen >= 5);
 
 	/* PLL is protected by panel, make sure we can write it */
-	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
-		assert_panel_unlocked(dev_priv, pipe);
+	if (IS_MOBILE(dev) && !IS_I830(dev))
+		assert_panel_unlocked(dev_priv, crtc->pipe);
 
-	reg = DPLL(pipe);
-	val = I915_READ(reg);
-	val |= DPLL_VCO_ENABLE;
+	I915_WRITE(reg, dpll);
+
+	/* Wait for the clocks to stabilize. */
+	POSTING_READ(reg);
+	udelay(150);
+
+	if (INTEL_INFO(dev)->gen >= 4) {
+		I915_WRITE(DPLL_MD(crtc->pipe),
+			   crtc->config.dpll_hw_state.dpll_md);
+	} else {
+		/* The pixel multiplier can only be updated once the
+		 * DPLL is enabled and the clocks are stable.
+		 *
+		 * So write it again.
+		 */
+		I915_WRITE(reg, dpll);
+	}
 
 	/* We do this three times for luck */
-	I915_WRITE(reg, val);
+	I915_WRITE(reg, dpll);
 	POSTING_READ(reg);
 	udelay(150); /* wait for warmup */
-	I915_WRITE(reg, val);
+	I915_WRITE(reg, dpll);
 	POSTING_READ(reg);
 	udelay(150); /* wait for warmup */
-	I915_WRITE(reg, val);
+	I915_WRITE(reg, dpll);
 	POSTING_READ(reg);
 	udelay(150); /* wait for warmup */
 }
@@ -3591,7 +3607,11 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
 	intel_crtc->active = true;
 	intel_update_watermarks(dev);
 
-	i9xx_enable_pll(dev_priv, pipe);
+	for_each_encoder_on_crtc(dev, crtc, encoder)
+		if (encoder->pre_pll_enable)
+			encoder->pre_pll_enable(encoder);
+
+	i9xx_enable_pll(intel_crtc);
 
 	for_each_encoder_on_crtc(dev, crtc, encoder)
 		if (encoder->pre_enable)
@@ -4429,8 +4449,6 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
 {
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_encoder *encoder;
-	int pipe = crtc->pipe;
 	u32 dpll;
 	bool is_sdvo;
 	struct dpll *clock = &crtc->config.dpll;
@@ -4494,37 +4512,14 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
 	dpll |= DPLL_VCO_ENABLE;
 	crtc->config.dpll_hw_state.dpll = dpll;
 
-	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
-	POSTING_READ(DPLL(pipe));
-	udelay(150);
-
-	for_each_encoder_on_crtc(dev, &crtc->base, encoder)
-		if (encoder->pre_pll_enable)
-			encoder->pre_pll_enable(encoder);
-
-	if (crtc->config.has_dp_encoder)
-		intel_dp_set_m_n(crtc);
-
-	I915_WRITE(DPLL(pipe), dpll);
-
-	/* Wait for the clocks to stabilize. */
-	POSTING_READ(DPLL(pipe));
-	udelay(150);
-
 	if (INTEL_INFO(dev)->gen >= 4) {
 		u32 dpll_md = (crtc->config.pixel_multiplier - 1)
 			<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
 		crtc->config.dpll_hw_state.dpll_md = dpll_md;
-
-		I915_WRITE(DPLL_MD(pipe), dpll_md);
-	} else {
-		/* The pixel multiplier can only be updated once the
-		 * DPLL is enabled and the clocks are stable.
-		 *
-		 * So write it again.
-		 */
-		I915_WRITE(DPLL(pipe), dpll);
 	}
+
+	if (crtc->config.has_dp_encoder)
+		intel_dp_set_m_n(crtc);
 }
 
 static void i8xx_update_pll(struct intel_crtc *crtc,
@@ -4533,8 +4528,6 @@ static void i8xx_update_pll(struct intel_crtc *crtc,
 {
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_encoder *encoder;
-	int pipe = crtc->pipe;
 	u32 dpll;
 	struct dpll *clock = &crtc->config.dpll;
 
@@ -4561,27 +4554,6 @@ static void i8xx_update_pll(struct intel_crtc *crtc,
 
 	dpll |= DPLL_VCO_ENABLE;
 	crtc->config.dpll_hw_state.dpll = dpll;
-
-	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
-	POSTING_READ(DPLL(pipe));
-	udelay(150);
-
-	for_each_encoder_on_crtc(dev, &crtc->base, encoder)
-		if (encoder->pre_pll_enable)
-			encoder->pre_pll_enable(encoder);
-
-	I915_WRITE(DPLL(pipe), dpll);
-
-	/* Wait for the clocks to stabilize. */
-	POSTING_READ(DPLL(pipe));
-	udelay(150);
-
-	/* The pixel multiplier can only be updated once the
-	 * DPLL is enabled and the clocks are stable.
-	 *
-	 * So write it again.
-	 */
-	I915_WRITE(DPLL(pipe), dpll);
 }
 
 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
-- 
1.7.11.7

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* [PATCH 28/31] drm/i915: s/pre_pll/pre/ on the lvds port enable function
  2013-06-05 11:34 [PATCH 00/31] shared pch display pll rework Daniel Vetter
                   ` (26 preceding siblings ...)
  2013-06-05 11:34 ` [PATCH 27/31] drm/i915: move i9xx dpll enabling into crtc enable function Daniel Vetter
@ 2013-06-05 11:34 ` Daniel Vetter
  2013-06-15  8:32   ` Imre Deak
  2013-06-05 11:34 ` [PATCH 29/31] drm/i915: clean up vlv ->pre_pll_enable and pll enable sequence Daniel Vetter
                   ` (3 subsequent siblings)
  31 siblings, 1 reply; 84+ messages in thread
From: Daniel Vetter @ 2013-06-05 11:34 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

i9xx doesn't use pre_enable at all, so we can fold this in now.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 13 +++----------
 drivers/gpu/drm/i915/intel_lvds.c    |  4 ++--
 2 files changed, 5 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b6f5e48..2e30f45 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3157,12 +3157,9 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
 
 	intel_update_watermarks(dev);
 
-	for_each_encoder_on_crtc(dev, crtc, encoder) {
-		if (encoder->pre_pll_enable)
-			encoder->pre_pll_enable(encoder);
+	for_each_encoder_on_crtc(dev, crtc, encoder)
 		if (encoder->pre_enable)
 			encoder->pre_enable(encoder);
-	}
 
 	if (intel_crtc->config.has_pch_encoder) {
 		/* Note: FDI PLL enabling _must_ be done before we enable the
@@ -3608,15 +3605,11 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
 	intel_update_watermarks(dev);
 
 	for_each_encoder_on_crtc(dev, crtc, encoder)
-		if (encoder->pre_pll_enable)
-			encoder->pre_pll_enable(encoder);
-
-	i9xx_enable_pll(intel_crtc);
-
-	for_each_encoder_on_crtc(dev, crtc, encoder)
 		if (encoder->pre_enable)
 			encoder->pre_enable(encoder);
 
+	i9xx_enable_pll(intel_crtc);
+
 	/* Enable panel fitting for LVDS */
 	i9xx_pfit_enable(intel_crtc);
 
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 36f8901..b2a4894 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -115,7 +115,7 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
  * This is an exception to the general rule that mode_set doesn't turn
  * things on.
  */
-static void intel_pre_pll_enable_lvds(struct intel_encoder *encoder)
+static void intel_pre_enable_lvds(struct intel_encoder *encoder)
 {
 	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 	struct drm_device *dev = encoder->base.dev;
@@ -946,7 +946,7 @@ bool intel_lvds_init(struct drm_device *dev)
 			 DRM_MODE_ENCODER_LVDS);
 
 	intel_encoder->enable = intel_enable_lvds;
-	intel_encoder->pre_pll_enable = intel_pre_pll_enable_lvds;
+	intel_encoder->pre_enable = intel_pre_enable_lvds;
 	intel_encoder->compute_config = intel_lvds_compute_config;
 	intel_encoder->disable = intel_disable_lvds;
 	intel_encoder->get_hw_state = intel_lvds_get_hw_state;
-- 
1.7.11.7

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* [PATCH 29/31] drm/i915: clean up vlv ->pre_pll_enable and pll enable sequence
  2013-06-05 11:34 [PATCH 00/31] shared pch display pll rework Daniel Vetter
                   ` (27 preceding siblings ...)
  2013-06-05 11:34 ` [PATCH 28/31] drm/i915: s/pre_pll/pre/ on the lvds port " Daniel Vetter
@ 2013-06-05 11:34 ` Daniel Vetter
  2013-06-06  8:22   ` [PATCH] " Daniel Vetter
  2013-06-05 11:34 ` [PATCH 30/31] drm/i915: Fix up cpt pixel multiplier " Daniel Vetter
                   ` (2 subsequent siblings)
  31 siblings, 1 reply; 84+ messages in thread
From: Daniel Vetter @ 2013-06-05 11:34 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Jani Nikula, Daniel Vetter

No need to call the ->pre_pll_enable hook twice if we don't enable the
dpll too early. This should make Jani a bit less grumpy.

Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 47 +++++++++++++++---------------------
 1 file changed, 19 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2e30f45..0917fb1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1268,32 +1268,38 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
 	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
 }
 
-static void vlv_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
+static void vlv_enable_pll(struct intel_crtc *crtc)
 {
-	int reg;
-	u32 val;
+	struct drm_device *dev = crtc->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int reg = DPLL(crtc->pipe);
+	u32 dpll = crtc->config.dpll_hw_state.dpll;
 
-	assert_pipe_disabled(dev_priv, pipe);
+	assert_pipe_disabled(dev_priv, crtc->pipe);
 
 	/* No really, not for ILK+ */
-	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
+	BUG_ON(!IS_VALLEYVIEW(dev) && dev_priv->info->gen >= 5);
 
 	/* PLL is protected by panel, make sure we can write it */
 	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
-		assert_panel_unlocked(dev_priv, pipe);
+		assert_panel_unlocked(dev_priv, crtc->pipe);
+
+	I915_WRITE(reg, dpll);
+	POSTING_READ(reg);
+	udelay(150);
+
+	if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
+		DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
 
-	reg = DPLL(pipe);
-	val = I915_READ(reg);
-	val |= DPLL_VCO_ENABLE;
 
 	/* We do this three times for luck */
-	I915_WRITE(reg, val);
+	I915_WRITE(reg, dpll);
 	POSTING_READ(reg);
 	udelay(150); /* wait for warmup */
-	I915_WRITE(reg, val);
+	I915_WRITE(reg, dpll);
 	POSTING_READ(reg);
 	udelay(150); /* wait for warmup */
-	I915_WRITE(reg, val);
+	I915_WRITE(reg, dpll);
 	POSTING_READ(reg);
 	udelay(150); /* wait for warmup */
 }
@@ -3561,7 +3567,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
 		if (encoder->pre_pll_enable)
 			encoder->pre_pll_enable(encoder);
 
-	vlv_enable_pll(dev_priv, pipe);
+	vlv_enable_pll(intel_crtc);
 
 	for_each_encoder_on_crtc(dev, crtc, encoder)
 		if (encoder->pre_enable)
@@ -4315,7 +4321,6 @@ static void vlv_update_pll(struct intel_crtc *crtc)
 {
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_encoder *encoder;
 	int pipe = crtc->pipe;
 	u32 dpll, mdiv;
 	u32 bestn, bestm1, bestm2, bestp1, bestp2;
@@ -4403,10 +4408,6 @@ static void vlv_update_pll(struct intel_crtc *crtc)
 
 	vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
 
-	for_each_encoder_on_crtc(dev, &crtc->base, encoder)
-		if (encoder->pre_pll_enable)
-			encoder->pre_pll_enable(encoder);
-
 	/* Enable DPIO clock input */
 	dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
 		DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
@@ -4416,20 +4417,10 @@ static void vlv_update_pll(struct intel_crtc *crtc)
 	dpll |= DPLL_VCO_ENABLE;
 	crtc->config.dpll_hw_state.dpll = dpll;
 
-	I915_WRITE(DPLL(pipe), dpll);
-	POSTING_READ(DPLL(pipe));
-	udelay(150);
-
-	if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
-		DRM_ERROR("DPLL %d failed to lock\n", pipe);
-
 	dpll_md = (crtc->config.pixel_multiplier - 1)
 		<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
 	crtc->config.dpll_hw_state.dpll_md = dpll_md;
 
-	I915_WRITE(DPLL_MD(pipe), dpll_md);
-	POSTING_READ(DPLL_MD(pipe));
-
 	if (crtc->config.has_dp_encoder)
 		intel_dp_set_m_n(crtc);
 
-- 
1.7.11.7

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* [PATCH 30/31] drm/i915: Fix up cpt pixel multiplier enable sequence
  2013-06-05 11:34 [PATCH 00/31] shared pch display pll rework Daniel Vetter
                   ` (28 preceding siblings ...)
  2013-06-05 11:34 ` [PATCH 29/31] drm/i915: clean up vlv ->pre_pll_enable and pll enable sequence Daniel Vetter
@ 2013-06-05 11:34 ` Daniel Vetter
  2013-06-05 11:34 ` [PATCH 31/31] drm/i915: clear DPLL reg when disabling i9xx dplls Daniel Vetter
  2013-06-07 17:46 ` [PATCH 00/31] shared pch display pll rework Ville Syrjälä
  31 siblings, 0 replies; 84+ messages in thread
From: Daniel Vetter @ 2013-06-05 11:34 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

Bspec for the "DPLL HDMI multiplier" field says:

"Restriction : The DPLL must be enabled and stable before setting these bits.
These bits must be programmed after DPLL_SEL is programmed."

There is apparently no restriction on programming the DPLL_SEL
register wrt the DPLL. So let's just move that up before we enable the
pch dpll.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 20 +++++++++++---------
 1 file changed, 11 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0917fb1..9f1247f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2929,15 +2929,8 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
 	/* For PCH output, training FDI link */
 	dev_priv->display.fdi_link_train(crtc);
 
-	/* XXX: pch pll's can be enabled any time before we enable the PCH
-	 * transcoder, and we actually should do this to not upset any PCH
-	 * transcoder that already use the clock when we share it.
-	 *
-	 * Note that enable_shared_dpll tries to do the right thing, but
-	 * get_shared_dpll unconditionally resets the pll - we need that to have
-	 * the right LVDS enable sequence. */
-	ironlake_enable_shared_dpll(intel_crtc);
-
+	/* We need to program the right clock selection before writing the pixel
+	 * mutliplier into the DPLL. */
 	if (HAS_PCH_CPT(dev)) {
 		u32 sel;
 
@@ -2951,6 +2944,15 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
 		I915_WRITE(PCH_DPLL_SEL, temp);
 	}
 
+	/* XXX: pch pll's can be enabled any time before we enable the PCH
+	 * transcoder, and we actually should do this to not upset any PCH
+	 * transcoder that already use the clock when we share it.
+	 *
+	 * Note that enable_shared_dpll tries to do the right thing, but
+	 * get_shared_dpll unconditionally resets the pll - we need that to have
+	 * the right LVDS enable sequence. */
+	ironlake_enable_shared_dpll(intel_crtc);
+
 	/* set transcoder timing, panel must allow it */
 	assert_panel_unlocked(dev_priv, pipe);
 	ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
-- 
1.7.11.7

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* [PATCH 31/31] drm/i915: clear DPLL reg when disabling i9xx dplls
  2013-06-05 11:34 [PATCH 00/31] shared pch display pll rework Daniel Vetter
                   ` (29 preceding siblings ...)
  2013-06-05 11:34 ` [PATCH 30/31] drm/i915: Fix up cpt pixel multiplier " Daniel Vetter
@ 2013-06-05 11:34 ` Daniel Vetter
  2013-06-07 17:46 ` [PATCH 00/31] shared pch display pll rework Ville Syrjälä
  31 siblings, 0 replies; 84+ messages in thread
From: Daniel Vetter @ 2013-06-05 11:34 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

Toghether with the hw state readout this should catch cases where we
don't properly updated the pll state (either in sw or hw). At least
for the shared dpll code the equivalent tricke helped a lot in
catching bugs.

Also rename the function prefix, it's not a generic piece of
infrastructure.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 16 +++++-----------
 1 file changed, 5 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9f1247f..a02e047 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1351,7 +1351,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
 }
 
 /**
- * intel_disable_pll - disable a PLL
+ * i9xx_disable_pll - disable a PLL
  * @dev_priv: i915 private structure
  * @pipe: pipe PLL to disable
  *
@@ -1359,11 +1359,8 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
  *
  * Note!  This is for pre-ILK only.
  */
-static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
+static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
 {
-	int reg;
-	u32 val;
-
 	/* Don't disable pipe A or pipe A PLLs if needed */
 	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
 		return;
@@ -1371,11 +1368,8 @@ static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
 	/* Make sure the pipe isn't still relying on us */
 	assert_pipe_disabled(dev_priv, pipe);
 
-	reg = DPLL(pipe);
-	val = I915_READ(reg);
-	val &= ~DPLL_VCO_ENABLE;
-	I915_WRITE(reg, val);
-	POSTING_READ(reg);
+	I915_WRITE(DPLL(pipe), 0);
+	POSTING_READ(DPLL(pipe));
 }
 
 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
@@ -3685,7 +3679,7 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
 		if (encoder->post_disable)
 			encoder->post_disable(encoder);
 
-	intel_disable_pll(dev_priv, pipe);
+	i9xx_disable_pll(dev_priv, pipe);
 
 	intel_crtc->active = false;
 	intel_update_fbc(dev);
-- 
1.7.11.7

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* Re: [PATCH 23/31] drm/i915: duplicate intel_enable_pll into i9xx and vlv versions
  2013-06-05 11:34 ` [PATCH 23/31] drm/i915: duplicate intel_enable_pll into i9xx and vlv versions Daniel Vetter
@ 2013-06-05 15:12   ` Jani Nikula
  2013-06-05 22:52     ` [PATCH] " Daniel Vetter
  0 siblings, 1 reply; 84+ messages in thread
From: Jani Nikula @ 2013-06-05 15:12 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

On Wed, 05 Jun 2013, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> Mostly since I _really_ don't want to touch the vlv hell.
>
> No code change, just duplication. Also kill a now seriously outdated
> code comment - the remark about the dvo encoder is now handled with
> the pipe A quirk.
>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 49 ++++++++++++++++++++++++------------
>  1 file changed, 33 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 4d2284e..5d84fea 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1271,20 +1271,37 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
>  	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
>  }
>  
> -/**
> - * intel_enable_pll - enable a PLL
> - * @dev_priv: i915 private structure
> - * @pipe: pipe PLL to enable
> - *
> - * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
> - * make sure the PLL reg is writable first though, since the panel write
> - * protect mechanism may be enabled.
> - *
> - * Note!  This is for pre-ILK only.
> - *
> - * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
> - */
> -static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
> +static void vlv_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
> +{
> +	int reg;
> +	u32 val;
> +
> +	assert_pipe_disabled(dev_priv, pipe);
> +
> +	/* No really, not for ILK+ */
> +	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);

Could be made BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));

Jani.

> +
> +	/* PLL is protected by panel, make sure we can write it */
> +	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
> +		assert_panel_unlocked(dev_priv, pipe);
> +
> +	reg = DPLL(pipe);
> +	val = I915_READ(reg);
> +	val |= DPLL_VCO_ENABLE;
> +
> +	/* We do this three times for luck */
> +	I915_WRITE(reg, val);
> +	POSTING_READ(reg);
> +	udelay(150); /* wait for warmup */
> +	I915_WRITE(reg, val);
> +	POSTING_READ(reg);
> +	udelay(150); /* wait for warmup */
> +	I915_WRITE(reg, val);
> +	POSTING_READ(reg);
> +	udelay(150); /* wait for warmup */
> +}
> +
> +static void i9xx_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
>  {
>  	int reg;
>  	u32 val;
> @@ -3535,7 +3552,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
>  		if (encoder->pre_pll_enable)
>  			encoder->pre_pll_enable(encoder);
>  
> -	intel_enable_pll(dev_priv, pipe);
> +	vlv_enable_pll(dev_priv, pipe);
>  
>  	for_each_encoder_on_crtc(dev, crtc, encoder)
>  		if (encoder->pre_enable)
> @@ -3578,7 +3595,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
>  	intel_crtc->active = true;
>  	intel_update_watermarks(dev);
>  
> -	intel_enable_pll(dev_priv, pipe);
> +	i9xx_enable_pll(dev_priv, pipe);
>  
>  	for_each_encoder_on_crtc(dev, crtc, encoder)
>  		if (encoder->pre_enable)
> -- 
> 1.7.11.7
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 84+ messages in thread

* Re: [PATCH 27/31] drm/i915: move i9xx dpll enabling into crtc enable function
  2013-06-05 11:34 ` [PATCH 27/31] drm/i915: move i9xx dpll enabling into crtc enable function Daniel Vetter
@ 2013-06-05 15:13   ` Jani Nikula
  2013-06-06  8:20     ` [PATCH] " Daniel Vetter
  2013-06-14 16:02   ` [PATCH 27/31] " Imre Deak
  1 sibling, 1 reply; 84+ messages in thread
From: Jani Nikula @ 2013-06-05 15:13 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

On Wed, 05 Jun 2013, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> Now that we have the proper pipe config to track this, we don't need
> to write any registers any more.
>
> v2: Drop a few now unnecessary local variables and switch the enable
> function to take a struct intel_crtc * to simply arguments.
>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 102 +++++++++++++----------------------
>  1 file changed, 37 insertions(+), 65 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b9be047..b6f5e48 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1298,32 +1298,48 @@ static void vlv_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
>  	udelay(150); /* wait for warmup */
>  }
>  
> -static void i9xx_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
> +static void i9xx_enable_pll(struct intel_crtc *crtc)
>  {
> -	int reg;
> -	u32 val;
> +	struct drm_device *dev = crtc->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	int reg = DPLL(crtc->pipe);
> +	u32 dpll = crtc->config.dpll_hw_state.dpll;
>  
> -	assert_pipe_disabled(dev_priv, pipe);
> +	assert_pipe_disabled(dev_priv, crtc->pipe);
>  
>  	/* No really, not for ILK+ */
> -	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
> +	BUG_ON(!IS_VALLEYVIEW(dev) && dev_priv->info->gen >= 5);

Could be made BUG_ON(dev_priv->info->gen >= 5);

Jani.

>  
>  	/* PLL is protected by panel, make sure we can write it */
> -	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
> -		assert_panel_unlocked(dev_priv, pipe);
> +	if (IS_MOBILE(dev) && !IS_I830(dev))
> +		assert_panel_unlocked(dev_priv, crtc->pipe);
>  
> -	reg = DPLL(pipe);
> -	val = I915_READ(reg);
> -	val |= DPLL_VCO_ENABLE;
> +	I915_WRITE(reg, dpll);
> +
> +	/* Wait for the clocks to stabilize. */
> +	POSTING_READ(reg);
> +	udelay(150);
> +
> +	if (INTEL_INFO(dev)->gen >= 4) {
> +		I915_WRITE(DPLL_MD(crtc->pipe),
> +			   crtc->config.dpll_hw_state.dpll_md);
> +	} else {
> +		/* The pixel multiplier can only be updated once the
> +		 * DPLL is enabled and the clocks are stable.
> +		 *
> +		 * So write it again.
> +		 */
> +		I915_WRITE(reg, dpll);
> +	}
>  
>  	/* We do this three times for luck */
> -	I915_WRITE(reg, val);
> +	I915_WRITE(reg, dpll);
>  	POSTING_READ(reg);
>  	udelay(150); /* wait for warmup */
> -	I915_WRITE(reg, val);
> +	I915_WRITE(reg, dpll);
>  	POSTING_READ(reg);
>  	udelay(150); /* wait for warmup */
> -	I915_WRITE(reg, val);
> +	I915_WRITE(reg, dpll);
>  	POSTING_READ(reg);
>  	udelay(150); /* wait for warmup */
>  }
> @@ -3591,7 +3607,11 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
>  	intel_crtc->active = true;
>  	intel_update_watermarks(dev);
>  
> -	i9xx_enable_pll(dev_priv, pipe);
> +	for_each_encoder_on_crtc(dev, crtc, encoder)
> +		if (encoder->pre_pll_enable)
> +			encoder->pre_pll_enable(encoder);
> +
> +	i9xx_enable_pll(intel_crtc);
>  
>  	for_each_encoder_on_crtc(dev, crtc, encoder)
>  		if (encoder->pre_enable)
> @@ -4429,8 +4449,6 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
>  {
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_encoder *encoder;
> -	int pipe = crtc->pipe;
>  	u32 dpll;
>  	bool is_sdvo;
>  	struct dpll *clock = &crtc->config.dpll;
> @@ -4494,37 +4512,14 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
>  	dpll |= DPLL_VCO_ENABLE;
>  	crtc->config.dpll_hw_state.dpll = dpll;
>  
> -	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
> -	POSTING_READ(DPLL(pipe));
> -	udelay(150);
> -
> -	for_each_encoder_on_crtc(dev, &crtc->base, encoder)
> -		if (encoder->pre_pll_enable)
> -			encoder->pre_pll_enable(encoder);
> -
> -	if (crtc->config.has_dp_encoder)
> -		intel_dp_set_m_n(crtc);
> -
> -	I915_WRITE(DPLL(pipe), dpll);
> -
> -	/* Wait for the clocks to stabilize. */
> -	POSTING_READ(DPLL(pipe));
> -	udelay(150);
> -
>  	if (INTEL_INFO(dev)->gen >= 4) {
>  		u32 dpll_md = (crtc->config.pixel_multiplier - 1)
>  			<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
>  		crtc->config.dpll_hw_state.dpll_md = dpll_md;
> -
> -		I915_WRITE(DPLL_MD(pipe), dpll_md);
> -	} else {
> -		/* The pixel multiplier can only be updated once the
> -		 * DPLL is enabled and the clocks are stable.
> -		 *
> -		 * So write it again.
> -		 */
> -		I915_WRITE(DPLL(pipe), dpll);
>  	}
> +
> +	if (crtc->config.has_dp_encoder)
> +		intel_dp_set_m_n(crtc);
>  }
>  
>  static void i8xx_update_pll(struct intel_crtc *crtc,
> @@ -4533,8 +4528,6 @@ static void i8xx_update_pll(struct intel_crtc *crtc,
>  {
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_encoder *encoder;
> -	int pipe = crtc->pipe;
>  	u32 dpll;
>  	struct dpll *clock = &crtc->config.dpll;
>  
> @@ -4561,27 +4554,6 @@ static void i8xx_update_pll(struct intel_crtc *crtc,
>  
>  	dpll |= DPLL_VCO_ENABLE;
>  	crtc->config.dpll_hw_state.dpll = dpll;
> -
> -	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
> -	POSTING_READ(DPLL(pipe));
> -	udelay(150);
> -
> -	for_each_encoder_on_crtc(dev, &crtc->base, encoder)
> -		if (encoder->pre_pll_enable)
> -			encoder->pre_pll_enable(encoder);
> -
> -	I915_WRITE(DPLL(pipe), dpll);
> -
> -	/* Wait for the clocks to stabilize. */
> -	POSTING_READ(DPLL(pipe));
> -	udelay(150);
> -
> -	/* The pixel multiplier can only be updated once the
> -	 * DPLL is enabled and the clocks are stable.
> -	 *
> -	 * So write it again.
> -	 */
> -	I915_WRITE(DPLL(pipe), dpll);
>  }
>  
>  static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
> -- 
> 1.7.11.7
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 84+ messages in thread

* [PATCH] drm/i915: duplicate intel_enable_pll into i9xx and vlv versions
  2013-06-05 15:12   ` Jani Nikula
@ 2013-06-05 22:52     ` Daniel Vetter
  0 siblings, 0 replies; 84+ messages in thread
From: Daniel Vetter @ 2013-06-05 22:52 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

Mostly since I _really_ don't want to touch the vlv hell.

No code change, just duplication. Also kill a now seriously outdated
code comment - the remark about the dvo encoder is now handled with
the pipe A quirk.

v2: Update the BUG_ONs as suggested by Jani (both in vlv_ and i9xx_
functions, since the split happens here).

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 51 ++++++++++++++++++++++++------------
 1 file changed, 34 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4d2284e..4b4bd61 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1271,20 +1271,37 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
 	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
 }
 
-/**
- * intel_enable_pll - enable a PLL
- * @dev_priv: i915 private structure
- * @pipe: pipe PLL to enable
- *
- * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
- * make sure the PLL reg is writable first though, since the panel write
- * protect mechanism may be enabled.
- *
- * Note!  This is for pre-ILK only.
- *
- * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
- */
-static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
+static void vlv_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
+{
+	int reg;
+	u32 val;
+
+	assert_pipe_disabled(dev_priv, pipe);
+
+	/* No really, not for ILK+ */
+	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
+
+	/* PLL is protected by panel, make sure we can write it */
+	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
+		assert_panel_unlocked(dev_priv, pipe);
+
+	reg = DPLL(pipe);
+	val = I915_READ(reg);
+	val |= DPLL_VCO_ENABLE;
+
+	/* We do this three times for luck */
+	I915_WRITE(reg, val);
+	POSTING_READ(reg);
+	udelay(150); /* wait for warmup */
+	I915_WRITE(reg, val);
+	POSTING_READ(reg);
+	udelay(150); /* wait for warmup */
+	I915_WRITE(reg, val);
+	POSTING_READ(reg);
+	udelay(150); /* wait for warmup */
+}
+
+static void i9xx_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
 {
 	int reg;
 	u32 val;
@@ -1292,7 +1309,7 @@ static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
 	assert_pipe_disabled(dev_priv, pipe);
 
 	/* No really, not for ILK+ */
-	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
+	BUG_ON(dev_priv->info->gen >= 5);
 
 	/* PLL is protected by panel, make sure we can write it */
 	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
@@ -3535,7 +3552,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
 		if (encoder->pre_pll_enable)
 			encoder->pre_pll_enable(encoder);
 
-	intel_enable_pll(dev_priv, pipe);
+	vlv_enable_pll(dev_priv, pipe);
 
 	for_each_encoder_on_crtc(dev, crtc, encoder)
 		if (encoder->pre_enable)
@@ -3578,7 +3595,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
 	intel_crtc->active = true;
 	intel_update_watermarks(dev);
 
-	intel_enable_pll(dev_priv, pipe);
+	i9xx_enable_pll(dev_priv, pipe);
 
 	for_each_encoder_on_crtc(dev, crtc, encoder)
 		if (encoder->pre_enable)
-- 
1.7.11.7

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* [PATCH] drm/i915: move i9xx dpll enabling into crtc enable function
  2013-06-05 15:13   ` Jani Nikula
@ 2013-06-06  8:20     ` Daniel Vetter
  0 siblings, 0 replies; 84+ messages in thread
From: Daniel Vetter @ 2013-06-06  8:20 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

Now that we have the proper pipe config to track this, we don't need
to write any registers any more.

v2: Drop a few now unnecessary local variables and switch the enable
function to take a struct intel_crtc * to simply arguments.

v3: Rebase on top of the newly-colored BUG_ON.

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 100 +++++++++++++----------------------
 1 file changed, 36 insertions(+), 64 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a516e78..b78f800 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1298,32 +1298,48 @@ static void vlv_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
 	udelay(150); /* wait for warmup */
 }
 
-static void i9xx_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
+static void i9xx_enable_pll(struct intel_crtc *crtc)
 {
-	int reg;
-	u32 val;
+	struct drm_device *dev = crtc->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int reg = DPLL(crtc->pipe);
+	u32 dpll = crtc->config.dpll_hw_state.dpll;
 
-	assert_pipe_disabled(dev_priv, pipe);
+	assert_pipe_disabled(dev_priv, crtc->pipe);
 
 	/* No really, not for ILK+ */
 	BUG_ON(dev_priv->info->gen >= 5);
 
 	/* PLL is protected by panel, make sure we can write it */
-	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
-		assert_panel_unlocked(dev_priv, pipe);
+	if (IS_MOBILE(dev) && !IS_I830(dev))
+		assert_panel_unlocked(dev_priv, crtc->pipe);
 
-	reg = DPLL(pipe);
-	val = I915_READ(reg);
-	val |= DPLL_VCO_ENABLE;
+	I915_WRITE(reg, dpll);
+
+	/* Wait for the clocks to stabilize. */
+	POSTING_READ(reg);
+	udelay(150);
+
+	if (INTEL_INFO(dev)->gen >= 4) {
+		I915_WRITE(DPLL_MD(crtc->pipe),
+			   crtc->config.dpll_hw_state.dpll_md);
+	} else {
+		/* The pixel multiplier can only be updated once the
+		 * DPLL is enabled and the clocks are stable.
+		 *
+		 * So write it again.
+		 */
+		I915_WRITE(reg, dpll);
+	}
 
 	/* We do this three times for luck */
-	I915_WRITE(reg, val);
+	I915_WRITE(reg, dpll);
 	POSTING_READ(reg);
 	udelay(150); /* wait for warmup */
-	I915_WRITE(reg, val);
+	I915_WRITE(reg, dpll);
 	POSTING_READ(reg);
 	udelay(150); /* wait for warmup */
-	I915_WRITE(reg, val);
+	I915_WRITE(reg, dpll);
 	POSTING_READ(reg);
 	udelay(150); /* wait for warmup */
 }
@@ -3591,7 +3607,11 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
 	intel_crtc->active = true;
 	intel_update_watermarks(dev);
 
-	i9xx_enable_pll(dev_priv, pipe);
+	for_each_encoder_on_crtc(dev, crtc, encoder)
+		if (encoder->pre_pll_enable)
+			encoder->pre_pll_enable(encoder);
+
+	i9xx_enable_pll(intel_crtc);
 
 	for_each_encoder_on_crtc(dev, crtc, encoder)
 		if (encoder->pre_enable)
@@ -4429,8 +4449,6 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
 {
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_encoder *encoder;
-	int pipe = crtc->pipe;
 	u32 dpll;
 	bool is_sdvo;
 	struct dpll *clock = &crtc->config.dpll;
@@ -4494,37 +4512,14 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
 	dpll |= DPLL_VCO_ENABLE;
 	crtc->config.dpll_hw_state.dpll = dpll;
 
-	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
-	POSTING_READ(DPLL(pipe));
-	udelay(150);
-
-	for_each_encoder_on_crtc(dev, &crtc->base, encoder)
-		if (encoder->pre_pll_enable)
-			encoder->pre_pll_enable(encoder);
-
-	if (crtc->config.has_dp_encoder)
-		intel_dp_set_m_n(crtc);
-
-	I915_WRITE(DPLL(pipe), dpll);
-
-	/* Wait for the clocks to stabilize. */
-	POSTING_READ(DPLL(pipe));
-	udelay(150);
-
 	if (INTEL_INFO(dev)->gen >= 4) {
 		u32 dpll_md = (crtc->config.pixel_multiplier - 1)
 			<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
 		crtc->config.dpll_hw_state.dpll_md = dpll_md;
-
-		I915_WRITE(DPLL_MD(pipe), dpll_md);
-	} else {
-		/* The pixel multiplier can only be updated once the
-		 * DPLL is enabled and the clocks are stable.
-		 *
-		 * So write it again.
-		 */
-		I915_WRITE(DPLL(pipe), dpll);
 	}
+
+	if (crtc->config.has_dp_encoder)
+		intel_dp_set_m_n(crtc);
 }
 
 static void i8xx_update_pll(struct intel_crtc *crtc,
@@ -4533,8 +4528,6 @@ static void i8xx_update_pll(struct intel_crtc *crtc,
 {
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_encoder *encoder;
-	int pipe = crtc->pipe;
 	u32 dpll;
 	struct dpll *clock = &crtc->config.dpll;
 
@@ -4561,27 +4554,6 @@ static void i8xx_update_pll(struct intel_crtc *crtc,
 
 	dpll |= DPLL_VCO_ENABLE;
 	crtc->config.dpll_hw_state.dpll = dpll;
-
-	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
-	POSTING_READ(DPLL(pipe));
-	udelay(150);
-
-	for_each_encoder_on_crtc(dev, &crtc->base, encoder)
-		if (encoder->pre_pll_enable)
-			encoder->pre_pll_enable(encoder);
-
-	I915_WRITE(DPLL(pipe), dpll);
-
-	/* Wait for the clocks to stabilize. */
-	POSTING_READ(DPLL(pipe));
-	udelay(150);
-
-	/* The pixel multiplier can only be updated once the
-	 * DPLL is enabled and the clocks are stable.
-	 *
-	 * So write it again.
-	 */
-	I915_WRITE(DPLL(pipe), dpll);
 }
 
 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
-- 
1.7.11.7

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* [PATCH] drm/i915: clean up vlv ->pre_pll_enable and pll enable sequence
  2013-06-05 11:34 ` [PATCH 29/31] drm/i915: clean up vlv ->pre_pll_enable and pll enable sequence Daniel Vetter
@ 2013-06-06  8:22   ` Daniel Vetter
  2013-07-11 14:11     ` Imre Deak
  0 siblings, 1 reply; 84+ messages in thread
From: Daniel Vetter @ 2013-06-06  8:22 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Jani Nikula, Daniel Vetter

No need to call the ->pre_pll_enable hook twice if we don't enable the
dpll too early. This should make Jani a bit less grumpy.

v2: Rebase on top of the newly-colored BUG_ONs.

Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 45 +++++++++++++++---------------------
 1 file changed, 18 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5e43b9a..6e4d666 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1268,32 +1268,38 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
 	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
 }
 
-static void vlv_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
+static void vlv_enable_pll(struct intel_crtc *crtc)
 {
-	int reg;
-	u32 val;
+	struct drm_device *dev = crtc->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int reg = DPLL(crtc->pipe);
+	u32 dpll = crtc->config.dpll_hw_state.dpll;
 
-	assert_pipe_disabled(dev_priv, pipe);
+	assert_pipe_disabled(dev_priv, crtc->pipe);
 
 	/* No really, not for ILK+ */
 	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
 
 	/* PLL is protected by panel, make sure we can write it */
 	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
-		assert_panel_unlocked(dev_priv, pipe);
+		assert_panel_unlocked(dev_priv, crtc->pipe);
+
+	I915_WRITE(reg, dpll);
+	POSTING_READ(reg);
+	udelay(150);
+
+	if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
+		DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
 
-	reg = DPLL(pipe);
-	val = I915_READ(reg);
-	val |= DPLL_VCO_ENABLE;
 
 	/* We do this three times for luck */
-	I915_WRITE(reg, val);
+	I915_WRITE(reg, dpll);
 	POSTING_READ(reg);
 	udelay(150); /* wait for warmup */
-	I915_WRITE(reg, val);
+	I915_WRITE(reg, dpll);
 	POSTING_READ(reg);
 	udelay(150); /* wait for warmup */
-	I915_WRITE(reg, val);
+	I915_WRITE(reg, dpll);
 	POSTING_READ(reg);
 	udelay(150); /* wait for warmup */
 }
@@ -3561,7 +3567,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
 		if (encoder->pre_pll_enable)
 			encoder->pre_pll_enable(encoder);
 
-	vlv_enable_pll(dev_priv, pipe);
+	vlv_enable_pll(intel_crtc);
 
 	for_each_encoder_on_crtc(dev, crtc, encoder)
 		if (encoder->pre_enable)
@@ -4315,7 +4321,6 @@ static void vlv_update_pll(struct intel_crtc *crtc)
 {
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_encoder *encoder;
 	int pipe = crtc->pipe;
 	u32 dpll, mdiv;
 	u32 bestn, bestm1, bestm2, bestp1, bestp2;
@@ -4403,10 +4408,6 @@ static void vlv_update_pll(struct intel_crtc *crtc)
 
 	vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
 
-	for_each_encoder_on_crtc(dev, &crtc->base, encoder)
-		if (encoder->pre_pll_enable)
-			encoder->pre_pll_enable(encoder);
-
 	/* Enable DPIO clock input */
 	dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
 		DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
@@ -4416,20 +4417,10 @@ static void vlv_update_pll(struct intel_crtc *crtc)
 	dpll |= DPLL_VCO_ENABLE;
 	crtc->config.dpll_hw_state.dpll = dpll;
 
-	I915_WRITE(DPLL(pipe), dpll);
-	POSTING_READ(DPLL(pipe));
-	udelay(150);
-
-	if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
-		DRM_ERROR("DPLL %d failed to lock\n", pipe);
-
 	dpll_md = (crtc->config.pixel_multiplier - 1)
 		<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
 	crtc->config.dpll_hw_state.dpll_md = dpll_md;
 
-	I915_WRITE(DPLL_MD(pipe), dpll_md);
-	POSTING_READ(DPLL_MD(pipe));
-
 	if (crtc->config.has_dp_encoder)
 		intel_dp_set_m_n(crtc);
 
-- 
1.7.11.7

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* Re: [PATCH 03/31] drm/i915: lock down pch pll accouting some more
  2013-06-05 11:34 ` [PATCH 03/31] drm/i915: lock down pch pll accouting some more Daniel Vetter
@ 2013-06-07 16:32   ` Ville Syrjälä
  2013-06-07 20:03     ` Daniel Vetter
  2013-06-07 21:09     ` Daniel Vetter
  0 siblings, 2 replies; 84+ messages in thread
From: Ville Syrjälä @ 2013-06-07 16:32 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: Intel Graphics Development

On Wed, Jun 05, 2013 at 01:34:05PM +0200, Daniel Vetter wrote:
> Before I start to make a complete mess out of this, crank up
> the paranoia level a bit.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 56fb6ed..39e977f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1440,6 +1440,7 @@ static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
>  	}
>  
>  	assert_pch_pll_enabled(dev_priv, pll, NULL);
> +	WARN_ON(!pll->on);
>  	if (--pll->active)
>  		return;

Maybe a WARN_ON(pll->on) near the end of ironlake_enable_pch_pll() too?

>  
> @@ -3031,12 +3032,18 @@ static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
>  	if (pll == NULL)
>  		return;
>  
> +	WARN_ON(!intel_crtc->config.has_pch_encoder);

Doesn't that trigger if we switch directly from PCH to CPU eDP?

> +
>  	if (pll->refcount == 0) {
>  		WARN(1, "bad PCH PLL refcount\n");
>  		return;
>  	}
>  
> -	--pll->refcount;
> +	if (--pll->refcount == 0) {
> +		WARN_ON(pll->on);
> +		WARN_ON(pll->active);
> +	}
> +
>  	intel_crtc->pch_pll = NULL;
>  }
>  
> -- 
> 1.7.11.7
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC

^ permalink raw reply	[flat|nested] 84+ messages in thread

* Re: [PATCH 05/31] drm/i915: switch crtc->shared_dpll from a pointer to an enum
  2013-06-05 11:34 ` [PATCH 05/31] drm/i915: switch crtc->shared_dpll from a pointer to an enum Daniel Vetter
@ 2013-06-07 16:48   ` Ville Syrjälä
  2013-06-07 21:10     ` [PATCH] " Daniel Vetter
  0 siblings, 1 reply; 84+ messages in thread
From: Ville Syrjälä @ 2013-06-07 16:48 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: Intel Graphics Development

On Wed, Jun 05, 2013 at 01:34:07PM +0200, Daniel Vetter wrote:
<snip>
> @@ -5731,11 +5740,15 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
>  		if (encoder->pre_pll_enable)
>  			encoder->pre_pll_enable(encoder);
>  
> -	if (intel_crtc->shared_dpll) {
> -		I915_WRITE(intel_crtc->shared_dpll->pll_reg, dpll);
> +	intel_crtc->lowfreq_avail = false;
> +
> +	if (intel_crtc->config.has_pch_encoder) {
> +		pll = intel_crtc_to_shared_dpll(intel_crtc);
> +
> +		I915_WRITE(pll->pll_reg, dpll);
>  
>  		/* Wait for the clocks to stabilize. */
> -		POSTING_READ(intel_crtc->shared_dpll->pll_reg);
> +		POSTING_READ(pll->pll_reg);
>  		udelay(150);
>  
>  		/* The pixel multiplier can only be updated once the
> @@ -5743,16 +5756,13 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
>  		 *
>  		 * So write it again.
>  		 */
> -		I915_WRITE(intel_crtc->shared_dpll->pll_reg, dpll);
> -	}
> +		I915_WRITE(pll->pll_reg, dpll);
>  
> -	intel_crtc->lowfreq_avail = false;
> -	if (intel_crtc->shared_dpll) {
>  		if (is_lvds && has_reduced_clock && i915_powersave) {
> -			I915_WRITE(intel_crtc->shared_dpll->fp1_reg, fp2);
> +			I915_WRITE(pll->fp1_reg, fp2);
>  			intel_crtc->lowfreq_avail = true;
>  		} else {
> -			I915_WRITE(intel_crtc->shared_dpll->fp1_reg, fp);
> +			I915_WRITE(pll->fp1_reg, fp);
>  		}

I was already a bit annoyed by the weird place of the the lowfreq_avail
assignment between two 'if (pch_pll)' blocks. Good to see it sorted out
:)

>  	}
>  
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 163bee9..422b2ad 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -306,7 +306,7 @@ struct intel_crtc {
>  	struct intel_crtc_config config;
>  
>  	/* We can share PLLs across outputs if the timings match */
> -	struct intel_shared_dpll *shared_dpll;
> +	enum intel_dpll_id shared_dpll;
>  	uint32_t ddi_pll_sel;
>  
>  	/* reset counter value when the last flip was submitted */
> -- 
> 1.7.11.7
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC

^ permalink raw reply	[flat|nested] 84+ messages in thread

* Re: [PATCH 06/31] drm/i915: move shared_dpll into the pipe config
  2013-06-05 11:34 ` [PATCH 06/31] drm/i915: move shared_dpll into the pipe config Daniel Vetter
@ 2013-06-07 17:03   ` Ville Syrjälä
  2013-06-07 21:10     ` [PATCH] " Daniel Vetter
  0 siblings, 1 reply; 84+ messages in thread
From: Ville Syrjälä @ 2013-06-07 17:03 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: Intel Graphics Development

On Wed, Jun 05, 2013 at 01:34:08PM +0200, Daniel Vetter wrote:
> With the big sed-job prep work done this is now really simple.

Since the pipe config is built up from scratch for modeset_pipes,
aren't we losing track of which PLL we were using previously?

We only unref the previous PLL for modeset_pipes in
ironlake_crtc_mode_set() by which time we've replace the pipe config
with the newly computed one.

For disable_pipes we en up in ironlake_crtc_off() which will do the
right thing since it still has the original pipe config to consult.

> 
> v2: Kill the funny whitespace spotted by Chris.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 10 +++++-----
>  drivers/gpu/drm/i915/intel_drv.h     |  5 +++--
>  2 files changed, 8 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index d95d813..b09c9a2 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -896,10 +896,10 @@ intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
>  {
>  	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
>  
> -	if (crtc->shared_dpll < 0)
> +	if (crtc->config.shared_dpll < 0)
>  		return NULL;
>  
> -	return &dev_priv->shared_dplls[crtc->shared_dpll];
> +	return &dev_priv->shared_dplls[crtc->config.shared_dpll];
>  }
>  
>  /* For ILK+ */
> @@ -2967,7 +2967,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
>  			sel = TRANSC_DPLLB_SEL;
>  			break;
>  		}
> -		if (intel_crtc->shared_dpll == DPLL_ID_PCH_PLL_B)
> +		if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
>  			temp |= sel;
>  		else
>  			temp &= ~sel;
> @@ -3055,7 +3055,7 @@ static void intel_put_shared_dpll(struct intel_crtc *crtc)
>  		WARN_ON(pll->active);
>  	}
>  
> -	crtc->shared_dpll = DPLL_ID_NONE;
> +	crtc->config.shared_dpll = DPLL_ID_NONE;
>  }
>  
>  static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, u32 dpll, u32 fp)
> @@ -3111,7 +3111,7 @@ static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
>  	return NULL;
>  
>  found:
> -	crtc->shared_dpll = i;
> +	crtc->config.shared_dpll = i;
>  	DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(crtc->pipe));
>  	if (pll->active == 0) {
>  		DRM_DEBUG_DRIVER("setting up pll %d\n", i);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 422b2ad..e0e5d55 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -241,6 +241,9 @@ struct intel_crtc_config {
>  	 * haswell. */
>  	struct dpll dpll;
>  
> +	/* Selected dpll when shared or DPLL_ID_PRIVATE. */
> +	enum intel_dpll_id shared_dpll;
> +
>  	int pipe_bpp;
>  	struct intel_link_m_n dp_m_n;
>  
> @@ -305,8 +308,6 @@ struct intel_crtc {
>  
>  	struct intel_crtc_config config;
>  
> -	/* We can share PLLs across outputs if the timings match */
> -	enum intel_dpll_id shared_dpll;
>  	uint32_t ddi_pll_sel;
>  
>  	/* reset counter value when the last flip was submitted */
> -- 
> 1.7.11.7
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC

^ permalink raw reply	[flat|nested] 84+ messages in thread

* Re: [PATCH 08/31] drm/i915: hw state readout for shared pch plls
  2013-06-05 11:34 ` [PATCH 08/31] drm/i915: hw state readout for shared pch plls Daniel Vetter
@ 2013-06-07 17:23   ` Ville Syrjälä
  2013-06-07 20:11     ` Daniel Vetter
  2013-06-07 21:11     ` [PATCH] " Daniel Vetter
  0 siblings, 2 replies; 84+ messages in thread
From: Ville Syrjälä @ 2013-06-07 17:23 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: Intel Graphics Development

On Wed, Jun 05, 2013 at 01:34:10PM +0200, Daniel Vetter wrote:
> Well, the first step of a long road at least, it only reads out
> the pipe -> shared dpll association thus far. Other state which needs
> to follow:
> 
> - hw state of the dpll (on/off + dpll registers). Currently we just
>   read that out from the hw state, but that doesn't work too well when
>   the dpll is in use, but not yet fully enabled. We get away since
>   most likely it already has been enabled and so the correct state is
>   left behind in the registers. But that doesn't hold for atomic
>   modesets when we want to enable all pipes at once.
> 
> - Refcount reconstruction for each dpll.
> 
> - Cross-checking of all the above. For that we need to keep the dpll
>   register state both in the pipe and in the shared_dpll struct, so
>   that we can check that every pipe is still connected to a correctly
>   configured dpll.
> 
> Note that since the refcount resconstruction isn't done yet this will
> spill a few WARNs at boot-up while trying to disable pch plls which
> have bogus refcounts. But since there's still a pile of refactoring to
> do I'd like to lock down the state handling as soon as possible hence
> decided against reordering the patches to quiet these WARNs - after
> all the issues they're complaining about have existed since forever,
> as Jesse can testify by having pch pll states blow up consistently in
> his fastboot patches ...
> 
> v2: We need to preserve the old shared_dpll since currently the
> shared dpll refcount dropping/getting is done in ->mode_set. With
> the usual pipe_config infrastructure the old dpll id is already lost
> at that point, hence preserve it in the new config.

Ah so here is the missing link. The correct place for this would appear
to be patch 6.

> v3: Rebase on top of the ips patch from Paulo.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 34 ++++++++++++++++++++++++++++------
>  1 file changed, 28 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a44c43c..20a933f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4020,12 +4020,11 @@ static void hsw_compute_ips_config(struct intel_crtc *crtc,
>  				   pipe_config->pipe_bpp == 24;
>  }
>  
> -static int intel_crtc_compute_config(struct drm_crtc *crtc,
> +static int intel_crtc_compute_config(struct intel_crtc *crtc,
>  				     struct intel_crtc_config *pipe_config)
>  {
> -	struct drm_device *dev = crtc->dev;
> +	struct drm_device *dev = crtc->base.dev;
>  	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
> -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  
>  	if (HAS_PCH_SPLIT(dev)) {
>  		/* FDI link clock is fixed at 2.7G */
> @@ -4056,10 +4055,16 @@ static int intel_crtc_compute_config(struct drm_crtc *crtc,
>  	}
>  
>  	if (IS_HASWELL(dev))
> -		hsw_compute_ips_config(intel_crtc, pipe_config);
> +		hsw_compute_ips_config(crtc, pipe_config);
> +
> +	/* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
> +	 * clock survives for now. */
> +	if (pipe_config->has_pch_encoder &&
> +	    (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)))
> +		pipe_config->shared_dpll = crtc->config.shared_dpll;
>  
>  	if (pipe_config->has_pch_encoder)
> -		return ironlake_fdi_compute_config(intel_crtc, pipe_config);
> +		return ironlake_fdi_compute_config(crtc, pipe_config);
>  
>  	return 0;
>  }
> @@ -4934,6 +4939,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>  	uint32_t tmp;
>  
>  	pipe_config->cpu_transcoder = crtc->pipe;
> +	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
>  
>  	tmp = I915_READ(PIPECONF(crtc->pipe));
>  	if (!(tmp & PIPECONF_ENABLE))
> @@ -5810,6 +5816,7 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
>  	uint32_t tmp;
>  
>  	pipe_config->cpu_transcoder = crtc->pipe;
> +	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
>  
>  	tmp = I915_READ(PIPECONF(crtc->pipe));
>  	if (!(tmp & PIPECONF_ENABLE))
> @@ -5827,6 +5834,16 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
>  		/* XXX: Can't properly read out the pch dpll pixel multiplier
>  		 * since we don't have state tracking for pch clocks yet. */
>  		pipe_config->pixel_multiplier = 1;
> +
> +		if (HAS_PCH_IBX(dev_priv->dev)) {
> +			pipe_config->shared_dpll = crtc->pipe;

Slightly magic, but all right.

> +		} else {
> +			tmp = I915_READ(PCH_DPLL_SEL);
> +			if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
> +				pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
> +			else
> +				pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
> +		}
>  	} else {
>  		pipe_config->pixel_multiplier = 1;
>  	}
> @@ -5907,6 +5924,8 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
>  	uint32_t tmp;
>  
>  	pipe_config->cpu_transcoder = crtc->pipe;
> +	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
> +
>  	tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
>  	if (tmp & TRANS_DDI_FUNC_ENABLE) {
>  		enum pipe trans_edp_pipe;
> @@ -7768,6 +7787,7 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
>  	drm_mode_copy(&pipe_config->adjusted_mode, mode);
>  	drm_mode_copy(&pipe_config->requested_mode, mode);
>  	pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
> +	pipe_config->shared_dpll = DPLL_ID_PRIVATE;

Do we want to put this here, or should we have some DPLL_ID_INVALID, so
that we'd always catch cases where we forgot to really think about which
PLL should be used?

>  
>  	/* Compute a starting value for pipe_config->pipe_bpp taking the source
>  	 * plane pixel format and any sink constraints into account. Returns the
> @@ -7816,7 +7836,7 @@ encoder_retry:
>  	if (!pipe_config->port_clock)
>  		pipe_config->port_clock = pipe_config->adjusted_mode.clock;
>  
> -	ret = intel_crtc_compute_config(crtc, pipe_config);
> +	ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
>  	if (ret < 0) {
>  		DRM_DEBUG_KMS("CRTC fixup failed\n");
>  		goto fail;
> @@ -8079,6 +8099,8 @@ intel_pipe_config_compare(struct drm_device *dev,
>  
>  	PIPE_CONF_CHECK_I(ips_enabled);
>  
> +	PIPE_CONF_CHECK_I(shared_dpll);
> +
>  #undef PIPE_CONF_CHECK_I
>  #undef PIPE_CONF_CHECK_FLAGS
>  
> -- 
> 1.7.11.7
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC

^ permalink raw reply	[flat|nested] 84+ messages in thread

* Re: [PATCH 00/31] shared pch display pll rework
  2013-06-05 11:34 [PATCH 00/31] shared pch display pll rework Daniel Vetter
                   ` (30 preceding siblings ...)
  2013-06-05 11:34 ` [PATCH 31/31] drm/i915: clear DPLL reg when disabling i9xx dplls Daniel Vetter
@ 2013-06-07 17:46 ` Ville Syrjälä
  2013-06-10 15:57   ` Ville Syrjälä
  31 siblings, 1 reply; 84+ messages in thread
From: Ville Syrjälä @ 2013-06-07 17:46 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: Intel Graphics Development

I've just gone over patches 01-13.

For patches 01,02,04,05,07,09-13
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

For patches 03,06,08 I replied with some concerns/ideas.

-- 
Ville Syrjälä
Intel OTC

^ permalink raw reply	[flat|nested] 84+ messages in thread

* Re: [PATCH 03/31] drm/i915: lock down pch pll accouting some more
  2013-06-07 16:32   ` Ville Syrjälä
@ 2013-06-07 20:03     ` Daniel Vetter
  2013-06-07 20:46       ` Ville Syrjälä
  2013-06-07 21:09     ` Daniel Vetter
  1 sibling, 1 reply; 84+ messages in thread
From: Daniel Vetter @ 2013-06-07 20:03 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: Daniel Vetter, Intel Graphics Development

On Fri, Jun 07, 2013 at 07:32:56PM +0300, Ville Syrjälä wrote:
> On Wed, Jun 05, 2013 at 01:34:05PM +0200, Daniel Vetter wrote:
> > Before I start to make a complete mess out of this, crank up
> > the paranoia level a bit.
> > 
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 9 ++++++++-
> >  1 file changed, 8 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 56fb6ed..39e977f 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -1440,6 +1440,7 @@ static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
> >  	}
> >  
> >  	assert_pch_pll_enabled(dev_priv, pll, NULL);
> > +	WARN_ON(!pll->on);
> >  	if (--pll->active)
> >  		return;
> 
> Maybe a WARN_ON(pll->on) near the end of ironlake_enable_pch_pll() too?

At the very end we set on = true, and the only non-error early return
(when the active refcount is > 0 to begin with) has alreay a
WARN_ON(!pll->on). Shouldn't that be good enough?

> 
> >  
> > @@ -3031,12 +3032,18 @@ static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
> >  	if (pll == NULL)
> >  		return;
> >  
> > +	WARN_ON(!intel_crtc->config.has_pch_encoder);
> 
> Doesn't that trigger if we switch directly from PCH to CPU eDP?

I've missed this case in testing somehow, and it's indeed broken. I don't
hit the WARN here, but that's just because I've broken the refcounting
somewhere.

At least I've got plenty of backtraces, so the level of paranoia seems to
be correct ;-)

I'll fix this up and resend.
-Daniel

> 
> > +
> >  	if (pll->refcount == 0) {
> >  		WARN(1, "bad PCH PLL refcount\n");
> >  		return;
> >  	}
> >  
> > -	--pll->refcount;
> > +	if (--pll->refcount == 0) {
> > +		WARN_ON(pll->on);
> > +		WARN_ON(pll->active);
> > +	}
> > +
> >  	intel_crtc->pch_pll = NULL;
> >  }
> >  
> > -- 
> > 1.7.11.7
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel OTC

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

^ permalink raw reply	[flat|nested] 84+ messages in thread

* Re: [PATCH 08/31] drm/i915: hw state readout for shared pch plls
  2013-06-07 17:23   ` Ville Syrjälä
@ 2013-06-07 20:11     ` Daniel Vetter
  2013-06-07 21:11     ` [PATCH] " Daniel Vetter
  1 sibling, 0 replies; 84+ messages in thread
From: Daniel Vetter @ 2013-06-07 20:11 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: Daniel Vetter, Intel Graphics Development

On Fri, Jun 07, 2013 at 08:23:33PM +0300, Ville Syrjälä wrote:
> On Wed, Jun 05, 2013 at 01:34:10PM +0200, Daniel Vetter wrote:
> > Well, the first step of a long road at least, it only reads out
> > the pipe -> shared dpll association thus far. Other state which needs
> > to follow:
> > 
> > - hw state of the dpll (on/off + dpll registers). Currently we just
> >   read that out from the hw state, but that doesn't work too well when
> >   the dpll is in use, but not yet fully enabled. We get away since
> >   most likely it already has been enabled and so the correct state is
> >   left behind in the registers. But that doesn't hold for atomic
> >   modesets when we want to enable all pipes at once.
> > 
> > - Refcount reconstruction for each dpll.
> > 
> > - Cross-checking of all the above. For that we need to keep the dpll
> >   register state both in the pipe and in the shared_dpll struct, so
> >   that we can check that every pipe is still connected to a correctly
> >   configured dpll.
> > 
> > Note that since the refcount resconstruction isn't done yet this will
> > spill a few WARNs at boot-up while trying to disable pch plls which
> > have bogus refcounts. But since there's still a pile of refactoring to
> > do I'd like to lock down the state handling as soon as possible hence
> > decided against reordering the patches to quiet these WARNs - after
> > all the issues they're complaining about have existed since forever,
> > as Jesse can testify by having pch pll states blow up consistently in
> > his fastboot patches ...
> > 
> > v2: We need to preserve the old shared_dpll since currently the
> > shared dpll refcount dropping/getting is done in ->mode_set. With
> > the usual pipe_config infrastructure the old dpll id is already lost
> > at that point, hence preserve it in the new config.
> 
> Ah so here is the missing link. The correct place for this would appear
> to be patch 6.

Yeah, I think you're right. I've botched this part a bit while developing
this series (those half-converted pipe config states are always a pain,
cpu_transcode was equally ugly) and squashed it into the wrong commit.

I'll fix this up.

> 
> > v3: Rebase on top of the ips patch from Paulo.
> > 
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 34 ++++++++++++++++++++++++++++------
> >  1 file changed, 28 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index a44c43c..20a933f 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -4020,12 +4020,11 @@ static void hsw_compute_ips_config(struct intel_crtc *crtc,
> >  				   pipe_config->pipe_bpp == 24;
> >  }
> >  
> > -static int intel_crtc_compute_config(struct drm_crtc *crtc,
> > +static int intel_crtc_compute_config(struct intel_crtc *crtc,
> >  				     struct intel_crtc_config *pipe_config)
> >  {
> > -	struct drm_device *dev = crtc->dev;
> > +	struct drm_device *dev = crtc->base.dev;
> >  	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
> > -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> >  
> >  	if (HAS_PCH_SPLIT(dev)) {
> >  		/* FDI link clock is fixed at 2.7G */
> > @@ -4056,10 +4055,16 @@ static int intel_crtc_compute_config(struct drm_crtc *crtc,
> >  	}
> >  
> >  	if (IS_HASWELL(dev))
> > -		hsw_compute_ips_config(intel_crtc, pipe_config);
> > +		hsw_compute_ips_config(crtc, pipe_config);
> > +
> > +	/* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
> > +	 * clock survives for now. */
> > +	if (pipe_config->has_pch_encoder &&
> > +	    (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)))
> > +		pipe_config->shared_dpll = crtc->config.shared_dpll;
> >  
> >  	if (pipe_config->has_pch_encoder)
> > -		return ironlake_fdi_compute_config(intel_crtc, pipe_config);
> > +		return ironlake_fdi_compute_config(crtc, pipe_config);
> >  
> >  	return 0;
> >  }
> > @@ -4934,6 +4939,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> >  	uint32_t tmp;
> >  
> >  	pipe_config->cpu_transcoder = crtc->pipe;
> > +	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
> >  
> >  	tmp = I915_READ(PIPECONF(crtc->pipe));
> >  	if (!(tmp & PIPECONF_ENABLE))
> > @@ -5810,6 +5816,7 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
> >  	uint32_t tmp;
> >  
> >  	pipe_config->cpu_transcoder = crtc->pipe;
> > +	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
> >  
> >  	tmp = I915_READ(PIPECONF(crtc->pipe));
> >  	if (!(tmp & PIPECONF_ENABLE))
> > @@ -5827,6 +5834,16 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
> >  		/* XXX: Can't properly read out the pch dpll pixel multiplier
> >  		 * since we don't have state tracking for pch clocks yet. */
> >  		pipe_config->pixel_multiplier = 1;
> > +
> > +		if (HAS_PCH_IBX(dev_priv->dev)) {
> > +			pipe_config->shared_dpll = crtc->pipe;
> 
> Slightly magic, but all right.

It's copied over from the get_shared_dpll code where we treat ilk like it
has a shared dpll, but it's fully fixed. Imo it's not worth it to change
that, the shared dpll code can cope with unshared dplls, too ;-)

I'll add a small comment here.

> 
> > +		} else {
> > +			tmp = I915_READ(PCH_DPLL_SEL);
> > +			if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
> > +				pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
> > +			else
> > +				pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
> > +		}
> >  	} else {
> >  		pipe_config->pixel_multiplier = 1;
> >  	}
> > @@ -5907,6 +5924,8 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
> >  	uint32_t tmp;
> >  
> >  	pipe_config->cpu_transcoder = crtc->pipe;
> > +	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
> > +
> >  	tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
> >  	if (tmp & TRANS_DDI_FUNC_ENABLE) {
> >  		enum pipe trans_edp_pipe;
> > @@ -7768,6 +7787,7 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
> >  	drm_mode_copy(&pipe_config->adjusted_mode, mode);
> >  	drm_mode_copy(&pipe_config->requested_mode, mode);
> >  	pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
> > +	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
> 
> Do we want to put this here, or should we have some DPLL_ID_INVALID, so
> that we'd always catch cases where we forgot to really think about which
> PLL should be used?

That's very much the idea behind INVALID, but with the currently still
crooked dpll selection in ->mode_set we can't do it. In the end I want the
sequence to be.

1. Set shared_dpll = DPLL_ID_INVALID for every pipe config we compute.
2. Let some platform code figure out which dpll we actually need (i.e.
PRIVATE, NONE or one of the platform specific shared dplls). This won't
yet do the get/put refcounting, since the modeset might still fail in the
compute config, so we shouldn't change state.
3. Wrap the get/put on shared dplls around the update_state code in the
middle of the modeset sequence. If we do the put still with the old pipe
config and the get after the new pipe config has been put into place it'll
all naturally work out.

Once that sequence is in place we can WARN_ON(shared_dpll == INVALID) and
also remove all the various hacks.
> 
> >  
> >  	/* Compute a starting value for pipe_config->pipe_bpp taking the source
> >  	 * plane pixel format and any sink constraints into account. Returns the
> > @@ -7816,7 +7836,7 @@ encoder_retry:
> >  	if (!pipe_config->port_clock)
> >  		pipe_config->port_clock = pipe_config->adjusted_mode.clock;
> >  
> > -	ret = intel_crtc_compute_config(crtc, pipe_config);
> > +	ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
> >  	if (ret < 0) {
> >  		DRM_DEBUG_KMS("CRTC fixup failed\n");
> >  		goto fail;
> > @@ -8079,6 +8099,8 @@ intel_pipe_config_compare(struct drm_device *dev,
> >  
> >  	PIPE_CONF_CHECK_I(ips_enabled);
> >  
> > +	PIPE_CONF_CHECK_I(shared_dpll);
> > +
> >  #undef PIPE_CONF_CHECK_I
> >  #undef PIPE_CONF_CHECK_FLAGS
> >  
> > -- 
> > 1.7.11.7
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel OTC

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

^ permalink raw reply	[flat|nested] 84+ messages in thread

* Re: [PATCH 03/31] drm/i915: lock down pch pll accouting some more
  2013-06-07 20:03     ` Daniel Vetter
@ 2013-06-07 20:46       ` Ville Syrjälä
  2013-06-07 21:13         ` Daniel Vetter
  0 siblings, 1 reply; 84+ messages in thread
From: Ville Syrjälä @ 2013-06-07 20:46 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: Daniel Vetter, Intel Graphics Development

On Fri, Jun 07, 2013 at 10:03:20PM +0200, Daniel Vetter wrote:
> On Fri, Jun 07, 2013 at 07:32:56PM +0300, Ville Syrjälä wrote:
> > On Wed, Jun 05, 2013 at 01:34:05PM +0200, Daniel Vetter wrote:
> > > Before I start to make a complete mess out of this, crank up
> > > the paranoia level a bit.
> > > 
> > > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> > > ---
> > >  drivers/gpu/drm/i915/intel_display.c | 9 ++++++++-
> > >  1 file changed, 8 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > > index 56fb6ed..39e977f 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -1440,6 +1440,7 @@ static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
> > >  	}
> > >  
> > >  	assert_pch_pll_enabled(dev_priv, pll, NULL);
> > > +	WARN_ON(!pll->on);
> > >  	if (--pll->active)
> > >  		return;
> > 
> > Maybe a WARN_ON(pll->on) near the end of ironlake_enable_pch_pll() too?
> 
> At the very end we set on = true, and the only non-error early return
> (when the active refcount is > 0 to begin with) has alreay a
> WARN_ON(!pll->on). Shouldn't that be good enough?

Well I was just thinking that since we have this dual bookeeping w/
active and on, maybe we want to warn if things go out of sync.

> 
> > 
> > >  
> > > @@ -3031,12 +3032,18 @@ static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
> > >  	if (pll == NULL)
> > >  		return;
> > >  
> > > +	WARN_ON(!intel_crtc->config.has_pch_encoder);
> > 
> > Doesn't that trigger if we switch directly from PCH to CPU eDP?
> 
> I've missed this case in testing somehow, and it's indeed broken. I don't
> hit the WARN here, but that's just because I've broken the refcounting
> somewhere.
> 
> At least I've got plenty of backtraces, so the level of paranoia seems to
> be correct ;-)
> 
> I'll fix this up and resend.
> -Daniel
> 
> > 
> > > +
> > >  	if (pll->refcount == 0) {
> > >  		WARN(1, "bad PCH PLL refcount\n");
> > >  		return;
> > >  	}
> > >  
> > > -	--pll->refcount;
> > > +	if (--pll->refcount == 0) {
> > > +		WARN_ON(pll->on);
> > > +		WARN_ON(pll->active);
> > > +	}
> > > +
> > >  	intel_crtc->pch_pll = NULL;
> > >  }
> > >  
> > > -- 
> > > 1.7.11.7
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> > -- 
> > Ville Syrjälä
> > Intel OTC
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch

-- 
Ville Syrjälä
Intel OTC

^ permalink raw reply	[flat|nested] 84+ messages in thread

* [PATCH] drm/i915: lock down pch pll accouting some more
  2013-06-07 16:32   ` Ville Syrjälä
  2013-06-07 20:03     ` Daniel Vetter
@ 2013-06-07 21:09     ` Daniel Vetter
  1 sibling, 0 replies; 84+ messages in thread
From: Daniel Vetter @ 2013-06-07 21:09 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

Before I start to make a complete mess out of this, crank up
the paranoia level a bit.

v2: Kill the has_pch_encoder check in put_shared_dpll - it's invalid
as spotted by Ville since we currently only put the dpll when we
already have the new pipe config. So a direct pch port -> cpu edp
transition will hit this.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8fbcf31..729c83d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1452,6 +1452,7 @@ static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
 	}
 
 	assert_pch_pll_enabled(dev_priv, pll, NULL);
+	WARN_ON(!pll->on);
 	if (--pll->active)
 		return;
 
@@ -3051,7 +3052,11 @@ static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
 		return;
 	}
 
-	--pll->refcount;
+	if (--pll->refcount == 0) {
+		WARN_ON(pll->on);
+		WARN_ON(pll->active);
+	}
+
 	intel_crtc->pch_pll = NULL;
 }
 
-- 
1.7.11.7

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* [PATCH] drm/i915: switch crtc->shared_dpll from a pointer to an enum
  2013-06-07 16:48   ` Ville Syrjälä
@ 2013-06-07 21:10     ` Daniel Vetter
  0 siblings, 0 replies; 84+ messages in thread
From: Daniel Vetter @ 2013-06-07 21:10 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

Dealing with discrete enum values is simpler for hw state readout and
pipe config computations than pointers - having neat names instead of
chasing pointers should look better in the code.

This isn't a that good reason for pch plls, but on haswell we actually
have 3 different types of plls: WRPLL, SPLL and the DP clocks. Having
explicit names should help there.

Since this also adds the intel_crtc_to_shared_dpll helper to further
abstract away the crtc -> dpll relationship this will also help to
make the next patch simpler, which moves the shared dpll into the pipe
configuration.

Also note that for uniformity we have two special dpll ids: NONE for
pipes which need a shared pll but don't have one (yet) and private for
when there's a non-shared pll (e.g. per-pipe or per-port pll).

I've thought whether we should also add a 2nd enum for the type of the
pll we want (for really generic pll selection code) but thrown that
idea out again - likely there's too much platform craziness going on
to be able to share the pll selection logic much.

Since this touched all the shared_pll functions a bit I've also done
an s/intel_crtc/crtc/ replacement on a few of them.

v2: Kill DPLL_ID_NONE. It's probably better to call it DPLL_ID_INVALID and use
it to check that the compute config stage assigns a dpll to every pipe.
But since that code isn't ready yet until we move the dpll selection out
of the ->mode_set callback, there's no use for it.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_drv.h      |  7 +++
 drivers/gpu/drm/i915/intel_display.c | 90 ++++++++++++++++++++----------------
 drivers/gpu/drm/i915/intel_drv.h     |  2 +-
 3 files changed, 58 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 812a5be..76e0287 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -140,6 +140,13 @@ struct intel_shared_dpll {
 	int fp0_reg;
 	int fp1_reg;
 };
+
+enum intel_dpll_id {
+	DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
+	/* real shared dpll ids must be >= 0 */
+	DPLL_ID_PCH_PLL_A,
+	DPLL_ID_PCH_PLL_B,
+};
 #define I915_NUM_PLLS 2
 
 /* Used by dp and fdi links */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1cc29e7..3926a80 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -891,6 +891,17 @@ static void assert_pll(struct drm_i915_private *dev_priv,
 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 
+static struct intel_shared_dpll *
+intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
+{
+	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
+
+	if (crtc->shared_dpll < 0)
+		return NULL;
+
+	return &dev_priv->shared_dplls[crtc->shared_dpll];
+}
+
 /* For ILK+ */
 static void assert_shared_dpll(struct drm_i915_private *dev_priv,
 			       struct intel_shared_dpll *pll,
@@ -1386,16 +1397,15 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
  * The PCH PLL needs to be enabled before the PCH transcoder, since it
  * drives the transcoder clock.
  */
-static void ironlake_enable_shared_dpll(struct intel_crtc *intel_crtc)
+static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
 {
-	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
-	struct intel_shared_dpll *pll;
+	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
+	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
 	int reg;
 	u32 val;
 
 	/* PCH PLLs only available on ILK, SNB and IVB */
 	BUG_ON(dev_priv->info->gen < 5);
-	pll = intel_crtc->shared_dpll;
 	if (pll == NULL)
 		return;
 
@@ -1404,7 +1414,7 @@ static void ironlake_enable_shared_dpll(struct intel_crtc *intel_crtc)
 
 	DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
 		      pll->pll_reg, pll->active, pll->on,
-		      intel_crtc->base.base.id);
+		      crtc->base.base.id);
 
 	/* PCH refclock must be enabled first */
 	assert_pch_refclk_enabled(dev_priv);
@@ -1427,10 +1437,10 @@ static void ironlake_enable_shared_dpll(struct intel_crtc *intel_crtc)
 	pll->on = true;
 }
 
-static void intel_disable_shared_dpll(struct intel_crtc *intel_crtc)
+static void intel_disable_shared_dpll(struct intel_crtc *crtc)
 {
-	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
-	struct intel_shared_dpll *pll = intel_crtc->shared_dpll;
+	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
+	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
 	int reg;
 	u32 val;
 
@@ -1444,7 +1454,7 @@ static void intel_disable_shared_dpll(struct intel_crtc *intel_crtc)
 
 	DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
 		      pll->pll_reg, pll->active, pll->on,
-		      intel_crtc->base.base.id);
+		      crtc->base.base.id);
 
 	if (WARN_ON(pll->active == 0)) {
 		assert_shared_dpll_disabled(dev_priv, pll, NULL);
@@ -1459,7 +1469,7 @@ static void intel_disable_shared_dpll(struct intel_crtc *intel_crtc)
 	DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
 
 	/* Make sure transcoder isn't still depending on us */
-	assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe);
+	assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
 
 	reg = pll->pll_reg;
 	val = I915_READ(reg);
@@ -1476,6 +1486,7 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
 {
 	struct drm_device *dev = dev_priv->dev;
 	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	uint32_t reg, val, pipeconf_val;
 
 	/* PCH only available on ILK+ */
@@ -1483,8 +1494,8 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
 
 	/* Make sure PCH DPLL is enabled */
 	assert_shared_dpll_enabled(dev_priv,
-				   to_intel_crtc(crtc)->shared_dpll,
-				   to_intel_crtc(crtc));
+				   intel_crtc_to_shared_dpll(intel_crtc),
+				   intel_crtc);
 
 	/* FDI must be feeding us bits for PCH ports */
 	assert_fdi_tx_enabled(dev_priv, pipe);
@@ -2971,7 +2982,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
 			sel = TRANSC_DPLLB_SEL;
 			break;
 		}
-		if (intel_crtc->shared_dpll->pll_reg == _PCH_DPLL_B)
+		if (intel_crtc->shared_dpll == DPLL_ID_PCH_PLL_B)
 			temp |= sel;
 		else
 			temp &= ~sel;
@@ -3040,9 +3051,9 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
 	lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
 }
 
-static void intel_put_shared_dpll(struct intel_crtc *intel_crtc)
+static void intel_put_shared_dpll(struct intel_crtc *crtc)
 {
-	struct intel_shared_dpll *pll = intel_crtc->shared_dpll;
+	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
 
 	if (pll == NULL)
 		return;
@@ -3057,29 +3068,28 @@ static void intel_put_shared_dpll(struct intel_crtc *intel_crtc)
 		WARN_ON(pll->active);
 	}
 
-	intel_crtc->shared_dpll = NULL;
+	crtc->shared_dpll = DPLL_ID_PRIVATE;
 }
 
-static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
+static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, u32 dpll, u32 fp)
 {
-	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
-	struct intel_shared_dpll *pll;
-	int i;
+	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
+	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
+	enum intel_dpll_id i;
 
-	pll = intel_crtc->shared_dpll;
 	if (pll) {
 		DRM_DEBUG_KMS("CRTC:%d dropping existing PCH PLL %x\n",
-			      intel_crtc->base.base.id, pll->pll_reg);
-		intel_put_shared_dpll(intel_crtc);
+			      crtc->base.base.id, pll->pll_reg);
+		intel_put_shared_dpll(crtc);
 	}
 
 	if (HAS_PCH_IBX(dev_priv->dev)) {
 		/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
-		i = intel_crtc->pipe;
+		i = crtc->pipe;
 		pll = &dev_priv->shared_dplls[i];
 
 		DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
-			      intel_crtc->base.base.id, pll->pll_reg);
+			      crtc->base.base.id, pll->pll_reg);
 
 		goto found;
 	}
@@ -3094,7 +3104,7 @@ static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *intel_
 		if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
 		    fp == I915_READ(pll->fp0_reg)) {
 			DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
-				      intel_crtc->base.base.id,
+				      crtc->base.base.id,
 				      pll->pll_reg, pll->refcount, pll->active);
 
 			goto found;
@@ -3106,7 +3116,7 @@ static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *intel_
 		pll = &dev_priv->shared_dplls[i];
 		if (pll->refcount == 0) {
 			DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
-				      intel_crtc->base.base.id, pll->pll_reg);
+				      crtc->base.base.id, pll->pll_reg);
 			goto found;
 		}
 	}
@@ -3114,8 +3124,8 @@ static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *intel_
 	return NULL;
 
 found:
-	intel_crtc->shared_dpll = pll;
-	DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
+	crtc->shared_dpll = i;
+	DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(crtc->pipe));
 	if (pll->active == 0) {
 		DRM_DEBUG_DRIVER("setting up pll %d\n", i);
 		WARN_ON(pll->on);
@@ -5711,6 +5721,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 	bool ok, has_reduced_clock = false;
 	bool is_lvds = false;
 	struct intel_encoder *encoder;
+	struct intel_shared_dpll *pll;
 	int ret;
 
 	for_each_encoder_on_crtc(dev, crtc, encoder) {
@@ -5746,8 +5757,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 
 	/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
 	if (intel_crtc->config.has_pch_encoder) {
-		struct intel_shared_dpll *pll;
-
 		fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
 		if (has_reduced_clock)
 			fp2 = i9xx_dpll_compute_fp(&reduced_clock);
@@ -5772,11 +5781,15 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 		if (encoder->pre_pll_enable)
 			encoder->pre_pll_enable(encoder);
 
-	if (intel_crtc->shared_dpll) {
-		I915_WRITE(intel_crtc->shared_dpll->pll_reg, dpll);
+	intel_crtc->lowfreq_avail = false;
+
+	if (intel_crtc->config.has_pch_encoder) {
+		pll = intel_crtc_to_shared_dpll(intel_crtc);
+
+		I915_WRITE(pll->pll_reg, dpll);
 
 		/* Wait for the clocks to stabilize. */
-		POSTING_READ(intel_crtc->shared_dpll->pll_reg);
+		POSTING_READ(pll->pll_reg);
 		udelay(150);
 
 		/* The pixel multiplier can only be updated once the
@@ -5784,16 +5797,13 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 		 *
 		 * So write it again.
 		 */
-		I915_WRITE(intel_crtc->shared_dpll->pll_reg, dpll);
-	}
+		I915_WRITE(pll->pll_reg, dpll);
 
-	intel_crtc->lowfreq_avail = false;
-	if (intel_crtc->shared_dpll) {
 		if (is_lvds && has_reduced_clock && i915_powersave) {
-			I915_WRITE(intel_crtc->shared_dpll->fp1_reg, fp2);
+			I915_WRITE(pll->fp1_reg, fp2);
 			intel_crtc->lowfreq_avail = true;
 		} else {
-			I915_WRITE(intel_crtc->shared_dpll->fp1_reg, fp);
+			I915_WRITE(pll->fp1_reg, fp);
 		}
 	}
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index b094260..1d4ec20 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -317,7 +317,7 @@ struct intel_crtc {
 	struct intel_crtc_config config;
 
 	/* We can share PLLs across outputs if the timings match */
-	struct intel_shared_dpll *shared_dpll;
+	enum intel_dpll_id shared_dpll;
 	uint32_t ddi_pll_sel;
 
 	/* reset counter value when the last flip was submitted */
-- 
1.7.11.7

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* [PATCH] drm/i915: move shared_dpll into the pipe config
  2013-06-07 17:03   ` Ville Syrjälä
@ 2013-06-07 21:10     ` Daniel Vetter
  0 siblings, 0 replies; 84+ messages in thread
From: Daniel Vetter @ 2013-06-07 21:10 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

With the big sed-job prep work done this is now really simple. With
the exception that we only assign the right shared dpll id in the
->mode_set callback but also depend upon the old one still being
around.

Until that mess is fixed up we need to jump through a few hoops to
keep the old value save.

v2: Kill the funny whitespace spotted by Chris.

v3: Move the shared_dpll pipe config fixup into this patch as noticed
by Ville. Also unconditionally set the shared_dpll with the current
one, since otherwise we won't handle direct pch port -> cpu edp
transitions correctly.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 26 +++++++++++++++-----------
 drivers/gpu/drm/i915/intel_drv.h     |  5 +++--
 2 files changed, 18 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3926a80..69240f7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -896,10 +896,10 @@ intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 
-	if (crtc->shared_dpll < 0)
+	if (crtc->config.shared_dpll < 0)
 		return NULL;
 
-	return &dev_priv->shared_dplls[crtc->shared_dpll];
+	return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 }
 
 /* For ILK+ */
@@ -2982,7 +2982,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
 			sel = TRANSC_DPLLB_SEL;
 			break;
 		}
-		if (intel_crtc->shared_dpll == DPLL_ID_PCH_PLL_B)
+		if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
 			temp |= sel;
 		else
 			temp &= ~sel;
@@ -3068,7 +3068,7 @@ static void intel_put_shared_dpll(struct intel_crtc *crtc)
 		WARN_ON(pll->active);
 	}
 
-	crtc->shared_dpll = DPLL_ID_PRIVATE;
+	crtc->config.shared_dpll = DPLL_ID_PRIVATE;
 }
 
 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, u32 dpll, u32 fp)
@@ -3124,7 +3124,7 @@ static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
 	return NULL;
 
 found:
-	crtc->shared_dpll = i;
+	crtc->config.shared_dpll = i;
 	DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(crtc->pipe));
 	if (pll->active == 0) {
 		DRM_DEBUG_DRIVER("setting up pll %d\n", i);
@@ -4087,12 +4087,11 @@ static void hsw_compute_ips_config(struct intel_crtc *crtc,
 				   pipe_config->pipe_bpp == 24;
 }
 
-static int intel_crtc_compute_config(struct drm_crtc *crtc,
+static int intel_crtc_compute_config(struct intel_crtc *crtc,
 				     struct intel_crtc_config *pipe_config)
 {
-	struct drm_device *dev = crtc->dev;
+	struct drm_device *dev = crtc->base.dev;
 	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 
 	if (HAS_PCH_SPLIT(dev)) {
 		/* FDI link clock is fixed at 2.7G */
@@ -4123,10 +4122,15 @@ static int intel_crtc_compute_config(struct drm_crtc *crtc,
 	}
 
 	if (IS_HASWELL(dev))
-		hsw_compute_ips_config(intel_crtc, pipe_config);
+		hsw_compute_ips_config(crtc, pipe_config);
+
+	/* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
+	 * clock survives for now. */
+	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
+		pipe_config->shared_dpll = crtc->config.shared_dpll;
 
 	if (pipe_config->has_pch_encoder)
-		return ironlake_fdi_compute_config(intel_crtc, pipe_config);
+		return ironlake_fdi_compute_config(crtc, pipe_config);
 
 	return 0;
 }
@@ -7891,7 +7895,7 @@ encoder_retry:
 	if (!pipe_config->port_clock)
 		pipe_config->port_clock = pipe_config->adjusted_mode.clock;
 
-	ret = intel_crtc_compute_config(crtc, pipe_config);
+	ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
 	if (ret < 0) {
 		DRM_DEBUG_KMS("CRTC fixup failed\n");
 		goto fail;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1d4ec20..b77df04 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -252,6 +252,9 @@ struct intel_crtc_config {
 	 * haswell. */
 	struct dpll dpll;
 
+	/* Selected dpll when shared or DPLL_ID_PRIVATE. */
+	enum intel_dpll_id shared_dpll;
+
 	int pipe_bpp;
 	struct intel_link_m_n dp_m_n;
 
@@ -316,8 +319,6 @@ struct intel_crtc {
 
 	struct intel_crtc_config config;
 
-	/* We can share PLLs across outputs if the timings match */
-	enum intel_dpll_id shared_dpll;
 	uint32_t ddi_pll_sel;
 
 	/* reset counter value when the last flip was submitted */
-- 
1.7.11.7

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* [PATCH] drm/i915: hw state readout for shared pch plls
  2013-06-07 17:23   ` Ville Syrjälä
  2013-06-07 20:11     ` Daniel Vetter
@ 2013-06-07 21:11     ` Daniel Vetter
  1 sibling, 0 replies; 84+ messages in thread
From: Daniel Vetter @ 2013-06-07 21:11 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

Well, the first step of a long road at least, it only reads out
the pipe -> shared dpll association thus far. Other state which needs
to follow:

- hw state of the dpll (on/off + dpll registers). Currently we just
  read that out from the hw state, but that doesn't work too well when
  the dpll is in use, but not yet fully enabled. We get away since
  most likely it already has been enabled and so the correct state is
  left behind in the registers. But that doesn't hold for atomic
  modesets when we want to enable all pipes at once.

- Refcount reconstruction for each dpll.

- Cross-checking of all the above. For that we need to keep the dpll
  register state both in the pipe and in the shared_dpll struct, so
  that we can check that every pipe is still connected to a correctly
  configured dpll.

Note that since the refcount resconstruction isn't done yet this will
spill a few WARNs at boot-up while trying to disable pch plls which
have bogus refcounts. But since there's still a pile of refactoring to
do I'd like to lock down the state handling as soon as possible hence
decided against reordering the patches to quiet these WARNs - after
all the issues they're complaining about have existed since forever,
as Jesse can testify by having pch pll states blow up consistently in
his fastboot patches ...

v2: We need to preserve the old shared_dpll since currently the
shared dpll refcount dropping/getting is done in ->mode_set. With
the usual pipe_config infrastructure the old dpll id is already lost
at that point, hence preserve it in the new config.

v3: Rebase on top of the ips patch from Paulo.

v4: We need to unconditionally take over the shared_dpll id from the
old pipe config when e.g. doing a direct pch port -> cpu edp
transition.

v5: Move the saving of the old shared_dpll id to an ealier patch.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2f242ae..e6d46ee 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4979,6 +4979,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
 	uint32_t tmp;
 
 	pipe_config->cpu_transcoder = crtc->pipe;
+	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
 
 	tmp = I915_READ(PIPECONF(crtc->pipe));
 	if (!(tmp & PIPECONF_ENABLE))
@@ -5855,6 +5856,7 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
 	uint32_t tmp;
 
 	pipe_config->cpu_transcoder = crtc->pipe;
+	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
 
 	tmp = I915_READ(PIPECONF(crtc->pipe));
 	if (!(tmp & PIPECONF_ENABLE))
@@ -5872,6 +5874,16 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
 		/* XXX: Can't properly read out the pch dpll pixel multiplier
 		 * since we don't have state tracking for pch clocks yet. */
 		pipe_config->pixel_multiplier = 1;
+
+		if (HAS_PCH_IBX(dev_priv->dev)) {
+			pipe_config->shared_dpll = crtc->pipe;
+		} else {
+			tmp = I915_READ(PCH_DPLL_SEL);
+			if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
+				pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
+			else
+				pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
+		}
 	} else {
 		pipe_config->pixel_multiplier = 1;
 	}
@@ -5952,6 +5964,8 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
 	uint32_t tmp;
 
 	pipe_config->cpu_transcoder = crtc->pipe;
+	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
+
 	tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
 	if (tmp & TRANS_DDI_FUNC_ENABLE) {
 		enum pipe trans_edp_pipe;
@@ -7821,6 +7835,7 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
 	drm_mode_copy(&pipe_config->adjusted_mode, mode);
 	drm_mode_copy(&pipe_config->requested_mode, mode);
 	pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
+	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
 
 	/* Compute a starting value for pipe_config->pipe_bpp taking the source
 	 * plane pixel format and any sink constraints into account. Returns the
@@ -8140,6 +8155,8 @@ intel_pipe_config_compare(struct drm_device *dev,
 
 	PIPE_CONF_CHECK_I(ips_enabled);
 
+	PIPE_CONF_CHECK_I(shared_dpll);
+
 #undef PIPE_CONF_CHECK_I
 #undef PIPE_CONF_CHECK_FLAGS
 #undef PIPE_CONF_QUIRK
-- 
1.7.11.7

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* Re: [PATCH 03/31] drm/i915: lock down pch pll accouting some more
  2013-06-07 20:46       ` Ville Syrjälä
@ 2013-06-07 21:13         ` Daniel Vetter
  2013-06-10 10:11           ` Ville Syrjälä
  0 siblings, 1 reply; 84+ messages in thread
From: Daniel Vetter @ 2013-06-07 21:13 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: Daniel Vetter, Intel Graphics Development

On Fri, Jun 07, 2013 at 11:46:08PM +0300, Ville Syrjälä wrote:
> On Fri, Jun 07, 2013 at 10:03:20PM +0200, Daniel Vetter wrote:
> > On Fri, Jun 07, 2013 at 07:32:56PM +0300, Ville Syrjälä wrote:
> > > On Wed, Jun 05, 2013 at 01:34:05PM +0200, Daniel Vetter wrote:
> > > > Before I start to make a complete mess out of this, crank up
> > > > the paranoia level a bit.
> > > > 
> > > > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> > > > ---
> > > >  drivers/gpu/drm/i915/intel_display.c | 9 ++++++++-
> > > >  1 file changed, 8 insertions(+), 1 deletion(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > > > index 56fb6ed..39e977f 100644
> > > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > > @@ -1440,6 +1440,7 @@ static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
> > > >  	}
> > > >  
> > > >  	assert_pch_pll_enabled(dev_priv, pll, NULL);
> > > > +	WARN_ON(!pll->on);
> > > >  	if (--pll->active)
> > > >  		return;
> > > 
> > > Maybe a WARN_ON(pll->on) near the end of ironlake_enable_pch_pll() too?
> > 
> > At the very end we set on = true, and the only non-error early return
> > (when the active refcount is > 0 to begin with) has alreay a
> > WARN_ON(!pll->on). Shouldn't that be good enough?
> 
> Well I was just thinking that since we have this dual bookeeping w/
> active and on, maybe we want to warn if things go out of sync.

Now I'm confused. I've tried to explain why I think we already have full
checking of pll->on in enable_shared_dpll ... Can you maybe show in a diff
where you'd want to add more?
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

^ permalink raw reply	[flat|nested] 84+ messages in thread

* Re: [PATCH 03/31] drm/i915: lock down pch pll accouting some more
  2013-06-07 21:13         ` Daniel Vetter
@ 2013-06-10 10:11           ` Ville Syrjälä
  2013-06-10 14:34             ` Daniel Vetter
  0 siblings, 1 reply; 84+ messages in thread
From: Ville Syrjälä @ 2013-06-10 10:11 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: Daniel Vetter, Intel Graphics Development

On Fri, Jun 07, 2013 at 11:13:32PM +0200, Daniel Vetter wrote:
> On Fri, Jun 07, 2013 at 11:46:08PM +0300, Ville Syrjälä wrote:
> > On Fri, Jun 07, 2013 at 10:03:20PM +0200, Daniel Vetter wrote:
> > > On Fri, Jun 07, 2013 at 07:32:56PM +0300, Ville Syrjälä wrote:
> > > > On Wed, Jun 05, 2013 at 01:34:05PM +0200, Daniel Vetter wrote:
> > > > > Before I start to make a complete mess out of this, crank up
> > > > > the paranoia level a bit.
> > > > > 
> > > > > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> > > > > ---
> > > > >  drivers/gpu/drm/i915/intel_display.c | 9 ++++++++-
> > > > >  1 file changed, 8 insertions(+), 1 deletion(-)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > > > > index 56fb6ed..39e977f 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > > > @@ -1440,6 +1440,7 @@ static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
> > > > >  	}
> > > > >  
> > > > >  	assert_pch_pll_enabled(dev_priv, pll, NULL);
> > > > > +	WARN_ON(!pll->on);
> > > > >  	if (--pll->active)
> > > > >  		return;
> > > > 
> > > > Maybe a WARN_ON(pll->on) near the end of ironlake_enable_pch_pll() too?
> > > 
> > > At the very end we set on = true, and the only non-error early return
> > > (when the active refcount is > 0 to begin with) has alreay a
> > > WARN_ON(!pll->on). Shouldn't that be good enough?
> > 
> > Well I was just thinking that since we have this dual bookeeping w/
> > active and on, maybe we want to warn if things go out of sync.
> 
> Now I'm confused. I've tried to explain why I think we already have full
> checking of pll->on in enable_shared_dpll ... Can you maybe show in a diff
> where you'd want to add more?

Something like this:

	if (pll->active++) {
		WARN_ON(!pll->on);
		assert_pch_pll_enabled(dev_priv, pll, NULL);
		return;
	}
+	WARN_ON(pll->on);

and maybe also:
+	assert_pch_pll_disabled(dev_priv, pll, NULL);


Or maybe just kill 'pll->on' as it seems totally redundant.

Also maybe we could move most of the asserts and WARNs to some
central location. Currently there are quite a few early return paths
from the pll enable/disable functions, and I don't think we perform the
same checks for all of the branches. So maybe we could just have one
function that would cross-check pll->on, pll->active and the real hardware
state. We could call said function just before and after
enable/disable_pch_pll().

-- 
Ville Syrjälä
Intel OTC

^ permalink raw reply	[flat|nested] 84+ messages in thread

* Re: [PATCH 03/31] drm/i915: lock down pch pll accouting some more
  2013-06-10 10:11           ` Ville Syrjälä
@ 2013-06-10 14:34             ` Daniel Vetter
  2013-06-10 14:47               ` Ville Syrjälä
  0 siblings, 1 reply; 84+ messages in thread
From: Daniel Vetter @ 2013-06-10 14:34 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: Intel Graphics Development

On Mon, Jun 10, 2013 at 12:11 PM, Ville Syrjälä
<ville.syrjala@linux.intel.com> wrote:
> On Fri, Jun 07, 2013 at 11:13:32PM +0200, Daniel Vetter wrote:
>> On Fri, Jun 07, 2013 at 11:46:08PM +0300, Ville Syrjälä wrote:
>> > On Fri, Jun 07, 2013 at 10:03:20PM +0200, Daniel Vetter wrote:
>> > > On Fri, Jun 07, 2013 at 07:32:56PM +0300, Ville Syrjälä wrote:
>> > > > On Wed, Jun 05, 2013 at 01:34:05PM +0200, Daniel Vetter wrote:
>> > > > > Before I start to make a complete mess out of this, crank up
>> > > > > the paranoia level a bit.
>> > > > >
>> > > > > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>> > > > > ---
>> > > > >  drivers/gpu/drm/i915/intel_display.c | 9 ++++++++-
>> > > > >  1 file changed, 8 insertions(+), 1 deletion(-)
>> > > > >
>> > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> > > > > index 56fb6ed..39e977f 100644
>> > > > > --- a/drivers/gpu/drm/i915/intel_display.c
>> > > > > +++ b/drivers/gpu/drm/i915/intel_display.c
>> > > > > @@ -1440,6 +1440,7 @@ static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
>> > > > >       }
>> > > > >
>> > > > >       assert_pch_pll_enabled(dev_priv, pll, NULL);
>> > > > > +     WARN_ON(!pll->on);
>> > > > >       if (--pll->active)
>> > > > >               return;
>> > > >
>> > > > Maybe a WARN_ON(pll->on) near the end of ironlake_enable_pch_pll() too?
>> > >
>> > > At the very end we set on = true, and the only non-error early return
>> > > (when the active refcount is > 0 to begin with) has alreay a
>> > > WARN_ON(!pll->on). Shouldn't that be good enough?
>> >
>> > Well I was just thinking that since we have this dual bookeeping w/
>> > active and on, maybe we want to warn if things go out of sync.
>>
>> Now I'm confused. I've tried to explain why I think we already have full
>> checking of pll->on in enable_shared_dpll ... Can you maybe show in a diff
>> where you'd want to add more?
>
> Something like this:
>
>         if (pll->active++) {
>                 WARN_ON(!pll->on);
>                 assert_pch_pll_enabled(dev_priv, pll, NULL);
>                 return;
>         }
> +       WARN_ON(pll->on);

That one's gonna misfire every time since we set pll->on = true only
at the end of the function in this case.

> and maybe also:
> +       assert_pch_pll_disabled(dev_priv, pll, NULL);

This one should already be in the platform-specific pll->enable hook.
It's added in "drm/i915: enable/disable hooks for shared dplls"

> Or maybe just kill 'pll->on' as it seems totally redundant.

Yeah, I've considered that but independently checking pll->on with the
hw state and pll->active with the number of crtc using it looked
neated. I guess we could rip out pll->on as a follow-up though.

> Also maybe we could move most of the asserts and WARNs to some
> central location. Currently there are quite a few early return paths
> from the pll enable/disable functions, and I don't think we perform the
> same checks for all of the branches. So maybe we could just have one
> function that would cross-check pll->on, pll->active and the real hardware
> state. We could call said function just before and after
> enable/disable_pch_pll().

The totally paranoid hw state cross checker does that at the very end
of each modeset. The checks in here are simply to assert a bunch of
edge transitions. And like I've said, I think I pretty much have it
all covered.

Cheers, Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

^ permalink raw reply	[flat|nested] 84+ messages in thread

* Re: [PATCH 03/31] drm/i915: lock down pch pll accouting some more
  2013-06-10 14:34             ` Daniel Vetter
@ 2013-06-10 14:47               ` Ville Syrjälä
  2013-06-10 15:28                 ` [PATCH] " Daniel Vetter
  0 siblings, 1 reply; 84+ messages in thread
From: Ville Syrjälä @ 2013-06-10 14:47 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: Intel Graphics Development

On Mon, Jun 10, 2013 at 04:34:05PM +0200, Daniel Vetter wrote:
> On Mon, Jun 10, 2013 at 12:11 PM, Ville Syrjälä
> <ville.syrjala@linux.intel.com> wrote:
> > On Fri, Jun 07, 2013 at 11:13:32PM +0200, Daniel Vetter wrote:
> >> On Fri, Jun 07, 2013 at 11:46:08PM +0300, Ville Syrjälä wrote:
> >> > On Fri, Jun 07, 2013 at 10:03:20PM +0200, Daniel Vetter wrote:
> >> > > On Fri, Jun 07, 2013 at 07:32:56PM +0300, Ville Syrjälä wrote:
> >> > > > On Wed, Jun 05, 2013 at 01:34:05PM +0200, Daniel Vetter wrote:
> >> > > > > Before I start to make a complete mess out of this, crank up
> >> > > > > the paranoia level a bit.
> >> > > > >
> >> > > > > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> >> > > > > ---
> >> > > > >  drivers/gpu/drm/i915/intel_display.c | 9 ++++++++-
> >> > > > >  1 file changed, 8 insertions(+), 1 deletion(-)
> >> > > > >
> >> > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> >> > > > > index 56fb6ed..39e977f 100644
> >> > > > > --- a/drivers/gpu/drm/i915/intel_display.c
> >> > > > > +++ b/drivers/gpu/drm/i915/intel_display.c
> >> > > > > @@ -1440,6 +1440,7 @@ static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
> >> > > > >       }
> >> > > > >
> >> > > > >       assert_pch_pll_enabled(dev_priv, pll, NULL);
> >> > > > > +     WARN_ON(!pll->on);
> >> > > > >       if (--pll->active)
> >> > > > >               return;
> >> > > >
> >> > > > Maybe a WARN_ON(pll->on) near the end of ironlake_enable_pch_pll() too?
> >> > >
> >> > > At the very end we set on = true, and the only non-error early return
> >> > > (when the active refcount is > 0 to begin with) has alreay a
> >> > > WARN_ON(!pll->on). Shouldn't that be good enough?
> >> >
> >> > Well I was just thinking that since we have this dual bookeeping w/
> >> > active and on, maybe we want to warn if things go out of sync.
> >>
> >> Now I'm confused. I've tried to explain why I think we already have full
> >> checking of pll->on in enable_shared_dpll ... Can you maybe show in a diff
> >> where you'd want to add more?
> >
> > Something like this:
> >
> >         if (pll->active++) {
> >                 WARN_ON(!pll->on);
> >                 assert_pch_pll_enabled(dev_priv, pll, NULL);
> >                 return;
> >         }
> > +       WARN_ON(pll->on);
> 
> That one's gonna misfire every time since we set pll->on = true only
> at the end of the function in this case.
> 
> > and maybe also:
> > +       assert_pch_pll_disabled(dev_priv, pll, NULL);
> 
> This one should already be in the platform-specific pll->enable hook.
> It's added in "drm/i915: enable/disable hooks for shared dplls"
> 
> > Or maybe just kill 'pll->on' as it seems totally redundant.
> 
> Yeah, I've considered that but independently checking pll->on with the
> hw state and pll->active with the number of crtc using it looked
> neated. I guess we could rip out pll->on as a follow-up though.
> 
> > Also maybe we could move most of the asserts and WARNs to some
> > central location. Currently there are quite a few early return paths
> > from the pll enable/disable functions, and I don't think we perform the
> > same checks for all of the branches. So maybe we could just have one
> > function that would cross-check pll->on, pll->active and the real hardware
> > state. We could call said function just before and after
> > enable/disable_pch_pll().
> 
> The totally paranoid hw state cross checker does that at the very end
> of each modeset. The checks in here are simply to assert a bunch of
> edge transitions. And like I've said, I think I pretty much have it
> all covered.

Before we set pll->on to true, pll->on should be false, no?

-- 
Ville Syrjälä
Intel OTC

^ permalink raw reply	[flat|nested] 84+ messages in thread

* [PATCH] drm/i915: lock down pch pll accouting some more
  2013-06-10 14:47               ` Ville Syrjälä
@ 2013-06-10 15:28                 ` Daniel Vetter
  0 siblings, 0 replies; 84+ messages in thread
From: Daniel Vetter @ 2013-06-10 15:28 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

Before I start to make a complete mess out of this, crank up
the paranoia level a bit.

v2: Kill the has_pch_encoder check in put_shared_dpll - it's invalid
as spotted by Ville since we currently only put the dpll when we
already have the new pipe config. So a direct pch port -> cpu edp
transition will hit this.

v3: Now that I've lifted my blinders add the WARN_ON Ville requested.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8fbcf31..4d50b0a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1414,6 +1414,7 @@ static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
 		assert_pch_pll_enabled(dev_priv, pll, NULL);
 		return;
 	}
+	WARN_ON(pll->on);
 
 	DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
 
@@ -1452,6 +1453,7 @@ static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
 	}
 
 	assert_pch_pll_enabled(dev_priv, pll, NULL);
+	WARN_ON(!pll->on);
 	if (--pll->active)
 		return;
 
@@ -3051,7 +3053,11 @@ static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
 		return;
 	}
 
-	--pll->refcount;
+	if (--pll->refcount == 0) {
+		WARN_ON(pll->on);
+		WARN_ON(pll->active);
+	}
+
 	intel_crtc->pch_pll = NULL;
 }
 
-- 
1.7.11.7

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* Re: [PATCH 00/31] shared pch display pll rework
  2013-06-07 17:46 ` [PATCH 00/31] shared pch display pll rework Ville Syrjälä
@ 2013-06-10 15:57   ` Ville Syrjälä
  2013-06-10 18:16     ` Daniel Vetter
  0 siblings, 1 reply; 84+ messages in thread
From: Ville Syrjälä @ 2013-06-10 15:57 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: Intel Graphics Development

On Fri, Jun 07, 2013 at 08:46:45PM +0300, Ville Syrjälä wrote:
> I've just gone over patches 01-13.
> 
> For patches 01,02,04,05,07,09-13
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> For patches 03,06,08 I replied with some concerns/ideas.

You can slap my r-b onto those three as well.

-- 
Ville Syrjälä
Intel OTC

^ permalink raw reply	[flat|nested] 84+ messages in thread

* Re: [PATCH 00/31] shared pch display pll rework
  2013-06-10 15:57   ` Ville Syrjälä
@ 2013-06-10 18:16     ` Daniel Vetter
  0 siblings, 0 replies; 84+ messages in thread
From: Daniel Vetter @ 2013-06-10 18:16 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: Daniel Vetter, Intel Graphics Development

On Mon, Jun 10, 2013 at 06:57:23PM +0300, Ville Syrjälä wrote:
> On Fri, Jun 07, 2013 at 08:46:45PM +0300, Ville Syrjälä wrote:
> > I've just gone over patches 01-13.
> > 
> > For patches 01,02,04,05,07,09-13
> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > For patches 03,06,08 I replied with some concerns/ideas.
> 
> You can slap my r-b onto those three as well.

Thanks for the review, I've merged patches 1-13 to dinq now.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

^ permalink raw reply	[flat|nested] 84+ messages in thread

* Re: [PATCH 14/31] drm/i915: display pll hw state readout and checking
  2013-06-05 11:34 ` [PATCH 14/31] drm/i915: display pll hw state readout and checking Daniel Vetter
@ 2013-06-12 13:31   ` Damien Lespiau
  2013-06-12 13:39     ` Ville Syrjälä
  0 siblings, 1 reply; 84+ messages in thread
From: Damien Lespiau @ 2013-06-12 13:31 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: Intel Graphics Development

On Wed, Jun 05, 2013 at 01:34:16PM +0200, Daniel Vetter wrote:
> Currently still with an empty register state, this will follow in a
> next step. This one here just creates the new vfunc and uses it for
> cross-checking, initial state takeover and the dpll assert function.
> 
> And add a FIXME for the ddi pll readout code, which still needs to be
> converted over.
> 
> v2:
> - Add some hw state readout debug output.
> - Also cross check the enabled crtc counting.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/i915_drv.h      |  7 ++++
>  drivers/gpu/drm/i915/intel_display.c | 77 +++++++++++++++++++++++++++++++++---
>  2 files changed, 79 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8e61128..f23b033 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -143,6 +143,9 @@ enum intel_dpll_id {
>  };
>  #define I915_NUM_PLLS 2
>  
> +struct intel_dpll_hw_state {
> +};
> +
>  struct intel_shared_dpll {
>  	int refcount; /* count of number of CRTCs sharing this PLL */
>  	int active; /* count of number of active CRTCs (i.e. DPMS on) */
> @@ -150,10 +153,14 @@ struct intel_shared_dpll {
>  	const char *name;
>  	/* should match the index in the dev_priv->shared_dplls array */
>  	enum intel_dpll_id id;
> +	struct intel_dpll_hw_state hw_state;
>  	void (*enable)(struct drm_i915_private *dev_priv,
>  		       struct intel_shared_dpll *pll);
>  	void (*disable)(struct drm_i915_private *dev_priv,
>  			struct intel_shared_dpll *pll);
> +	bool (*get_hw_state)(struct drm_i915_private *dev_priv,
> +			     struct intel_shared_dpll *pll,
> +			     struct intel_dpll_hw_state *hw_state);
>  };
>  
>  /* Used by dp and fdi links */
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index ea4b7a6..998ba5c 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -907,8 +907,8 @@ static void assert_shared_dpll(struct drm_i915_private *dev_priv,
>  			       struct intel_shared_dpll *pll,
>  			       bool state)
>  {
> -	u32 val;
>  	bool cur_state;
> +	struct intel_dpll_hw_state hw_state;
>  
>  	if (HAS_PCH_LPT(dev_priv->dev)) {
>  		DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
> @@ -919,11 +919,10 @@ static void assert_shared_dpll(struct drm_i915_private *dev_priv,
>  		  "asserting DPLL %s with no DPLL\n", state_string(state)))
>  		return;
>  
> -	val = I915_READ(PCH_DPLL(pll->id));
> -	cur_state = !!(val & DPLL_VCO_ENABLE);
> +	cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
>  	WARN(cur_state != state,
> -	     "%s assertion failure (expected %s, current %s), val=%08x\n",
> -	     pll->name, state_string(state), state_string(cur_state), val);
> +	     "%s assertion failure (expected %s, current %s)\n",
> +	     pll->name, state_string(state), state_string(cur_state));
>  }
>  #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
>  #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
> @@ -8071,6 +8070,8 @@ intel_modeset_check_state(struct drm_device *dev)
>  	struct intel_encoder *encoder;
>  	struct intel_connector *connector;
>  	struct intel_crtc_config pipe_config;
> +	struct intel_dpll_hw_state dpll_hw_state;
> +	int i;
>  
>  	list_for_each_entry(connector, &dev->mode_config.connector_list,
>  			    base.head) {
> @@ -8183,6 +8184,41 @@ intel_modeset_check_state(struct drm_device *dev)
>  					       "[sw state]");
>  		}
>  	}
> +
> +	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
> +		struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
> +		int enabled_crtcs = 0, active_crtcs = 0;
> +		bool active;
> +
> +		memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
> +
> +		DRM_DEBUG_KMS("%s\n", pll->name);
> +
> +		active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
> +
> +		WARN(pll->active > pll->refcount,
> +		     "more active pll users than references: %i vs %i\n",
> +		     pll->active, pll->refcount);
> +		WARN(pll->active && !pll->on,
> +		     "pll in active use but not on in sw tracking\n");
> +		WARN(pll->on != active,
> +		     "pll on state mismatch (expected %i, found %i)\n",
> +		     pll->on, active);
> +
> +		list_for_each_entry(crtc, &dev->mode_config.crtc_list,
> +				    base.head) {
> +			if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
> +				enabled_crtcs++;
> +			if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
> +				active_crtcs++;
> +		}
> +		WARN(pll->active != active_crtcs,
> +		     "pll active crtcs mismatch (expected %i, found %i)\n",
> +		     pll->active, active_crtcs);
> +		WARN(pll->refcount != enabled_crtcs,
> +		     "pll enabled crtcs mismatch (expected %i, found %i)\n",
> +		     pll->refcount, enabled_crtcs);
> +	}
>  }
>  
>  static int __intel_set_mode(struct drm_crtc *crtc,
> @@ -8621,6 +8657,17 @@ static void intel_cpu_pll_init(struct drm_device *dev)
>  		intel_ddi_pll_init(dev);
>  }
>  
> +static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
> +				      struct intel_shared_dpll *pll,
> +				      struct intel_dpll_hw_state *hw_state)
> +{
> +	uint32_t val;
> +
> +	val = I915_READ(PCH_DPLL(pll->id));
> +
> +	return val & DPLL_VCO_ENABLE;
> +}
> +

Don't we want !!(val & DPLL_VCO_ENABLE) here? we're comparing this to 0
and 1.

>  static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
>  				struct intel_shared_dpll *pll)
>  {
> @@ -8675,6 +8722,8 @@ static void ibx_pch_dpll_init(struct drm_device *dev)
>  		dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
>  		dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
>  		dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
> +		dev_priv->shared_dplls[i].get_hw_state =
> +			ibx_pch_dpll_get_hw_state;
>  	}
>  }
>  
> @@ -9592,6 +9641,7 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
>  	struct intel_crtc *crtc;
>  	struct intel_encoder *encoder;
>  	struct intel_connector *connector;
> +	int i;
>  
>  	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
>  			    base.head) {
> @@ -9607,9 +9657,26 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
>  			      crtc->active ? "enabled" : "disabled");
>  	}
>  
> +	/* FIXME: Smash this into the new shared dpll infrastructure. */
>  	if (HAS_DDI(dev))
>  		intel_ddi_setup_hw_pll_state(dev);
>  
> +	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
> +		struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
> +
> +		pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
> +		pll->active = 0;
> +		list_for_each_entry(crtc, &dev->mode_config.crtc_list,
> +				    base.head) {
> +			if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
> +				pll->active++;
> +		}
> +		pll->refcount = pll->active;
> +
> +		DRM_DEBUG_KMS("%s hw state readout: refcount %i\n",
> +			      pll->name, pll->refcount);
> +	}
> +
>  	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
>  			    base.head) {
>  		pipe = 0;
> -- 
> 1.7.11.7
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 84+ messages in thread

* Re: [PATCH 15/31] drm/i915: extract readout_hw_state from setup_hw_state
  2013-06-05 11:34 ` [PATCH 15/31] drm/i915: extract readout_hw_state from setup_hw_state Daniel Vetter
@ 2013-06-12 13:32   ` Damien Lespiau
  2013-06-12 14:26   ` Daniel Vetter
  1 sibling, 0 replies; 84+ messages in thread
From: Damien Lespiau @ 2013-06-12 13:32 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: Intel Graphics Development

On Wed, Jun 05, 2013 at 01:34:17PM +0200, Daniel Vetter wrote:
> Simply grew too big. This also makes the fixup and restore logic in
> setup_hw_state stand out a bit more clearly.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

> ---
>  drivers/gpu/drm/i915/intel_display.c | 20 +++++++++++++++-----
>  1 file changed, 15 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 998ba5c..95ed27b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9630,14 +9630,10 @@ void i915_redisable_vga(struct drm_device *dev)
>  	}
>  }
>  
> -/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
> - * and i915 state tracking structures. */
> -void intel_modeset_setup_hw_state(struct drm_device *dev,
> -				  bool force_restore)
> +static void intel_modeset_readout_hw_state(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	enum pipe pipe;
> -	struct drm_plane *plane;
>  	struct intel_crtc *crtc;
>  	struct intel_encoder *encoder;
>  	struct intel_connector *connector;
> @@ -9713,6 +9709,20 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
>  			      drm_get_connector_name(&connector->base),
>  			      connector->base.encoder ? "enabled" : "disabled");
>  	}
> +}
> +
> +/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
> + * and i915 state tracking structures. */
> +void intel_modeset_setup_hw_state(struct drm_device *dev,
> +				  bool force_restore)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	enum pipe pipe;
> +	struct drm_plane *plane;
> +	struct intel_crtc *crtc;
> +	struct intel_encoder *encoder;
> +
> +	intel_modeset_readout_hw_state(dev);
>  
>  	/* HW state is read out, now we need to sanitize this mess. */
>  	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
> -- 
> 1.7.11.7
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 84+ messages in thread

* Re: [PATCH 16/31] drm/i915: split up intel_modeset_check_state
  2013-06-05 11:34 ` [PATCH 16/31] drm/i915: split up intel_modeset_check_state Daniel Vetter
@ 2013-06-12 13:33   ` Damien Lespiau
  0 siblings, 0 replies; 84+ messages in thread
From: Damien Lespiau @ 2013-06-12 13:33 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: Intel Graphics Development

On Wed, Jun 05, 2013 at 01:34:18PM +0200, Daniel Vetter wrote:
> Simply grew too large and neede to be split up into parts.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

> ---
>  drivers/gpu/drm/i915/intel_display.c | 44 +++++++++++++++++++++++++++++-------
>  1 file changed, 36 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 95ed27b..c42b87b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8062,16 +8062,10 @@ intel_pipe_config_compare(struct drm_device *dev,
>  	return true;
>  }
>  
> -void
> -intel_modeset_check_state(struct drm_device *dev)
> +static void
> +check_connector_state(struct drm_device *dev)
>  {
> -	drm_i915_private_t *dev_priv = dev->dev_private;
> -	struct intel_crtc *crtc;
> -	struct intel_encoder *encoder;
>  	struct intel_connector *connector;
> -	struct intel_crtc_config pipe_config;
> -	struct intel_dpll_hw_state dpll_hw_state;
> -	int i;
>  
>  	list_for_each_entry(connector, &dev->mode_config.connector_list,
>  			    base.head) {
> @@ -8082,6 +8076,13 @@ intel_modeset_check_state(struct drm_device *dev)
>  		WARN(&connector->new_encoder->base != connector->base.encoder,
>  		     "connector's staged encoder doesn't match current encoder\n");
>  	}
> +}
> +
> +static void
> +check_encoder_state(struct drm_device *dev)
> +{
> +	struct intel_encoder *encoder;
> +	struct intel_connector *connector;
>  
>  	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
>  			    base.head) {
> @@ -8133,6 +8134,15 @@ intel_modeset_check_state(struct drm_device *dev)
>  		     tracked_pipe, pipe);
>  
>  	}
> +}
> +
> +static void
> +check_crtc_state(struct drm_device *dev)
> +{
> +	drm_i915_private_t *dev_priv = dev->dev_private;
> +	struct intel_crtc *crtc;
> +	struct intel_encoder *encoder;
> +	struct intel_crtc_config pipe_config;
>  
>  	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
>  			    base.head) {
> @@ -8184,6 +8194,15 @@ intel_modeset_check_state(struct drm_device *dev)
>  					       "[sw state]");
>  		}
>  	}
> +}
> +
> +static void
> +check_shared_dpll_state(struct drm_device *dev)
> +{
> +	drm_i915_private_t *dev_priv = dev->dev_private;
> +	struct intel_crtc *crtc;
> +	struct intel_dpll_hw_state dpll_hw_state;
> +	int i;
>  
>  	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
>  		struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
> @@ -8221,6 +8240,15 @@ intel_modeset_check_state(struct drm_device *dev)
>  	}
>  }
>  
> +void
> +intel_modeset_check_state(struct drm_device *dev)
> +{
> +	check_connector_state(dev);
> +	check_encoder_state(dev);
> +	check_crtc_state(dev);
> +	check_shared_dpll_state(dev);
> +}
> +
>  static int __intel_set_mode(struct drm_crtc *crtc,
>  			    struct drm_display_mode *mode,
>  			    int x, int y, struct drm_framebuffer *fb)
> -- 
> 1.7.11.7
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 84+ messages in thread

* Re: [PATCH 17/31] drm/i915: WARN on lack of shared dpll
  2013-06-05 11:34 ` [PATCH 17/31] drm/i915: WARN on lack of shared dpll Daniel Vetter
@ 2013-06-12 13:38   ` Damien Lespiau
  0 siblings, 0 replies; 84+ messages in thread
From: Damien Lespiau @ 2013-06-12 13:38 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: Intel Graphics Development

On Wed, Jun 05, 2013 at 01:34:19PM +0200, Daniel Vetter wrote:
> Now that we have proper hw state reconstruction we should never have a
> case where we don't have the software dpll state properly set up. So
> add WARNs to the respective !pll cases in enable/disabel_shared_dpll.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

> ---
>  drivers/gpu/drm/i915/intel_display.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index c42b87b..388ac54 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1371,7 +1371,7 @@ static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
>  
>  	/* PCH PLLs only available on ILK, SNB and IVB */
>  	BUG_ON(dev_priv->info->gen < 5);
> -	if (pll == NULL)
> +	if (WARN_ON(pll == NULL))
>  		return;
>  
>  	if (WARN_ON(pll->refcount == 0))
> @@ -1399,7 +1399,7 @@ static void intel_disable_shared_dpll(struct intel_crtc *crtc)
>  
>  	/* PCH only available on ILK+ */
>  	BUG_ON(dev_priv->info->gen < 5);
> -	if (pll == NULL)
> +	if (WARN_ON(pll == NULL))
>  	       return;
>  
>  	if (WARN_ON(pll->refcount == 0))
> -- 
> 1.7.11.7
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 84+ messages in thread

* Re: [PATCH 14/31] drm/i915: display pll hw state readout and checking
  2013-06-12 13:31   ` Damien Lespiau
@ 2013-06-12 13:39     ` Ville Syrjälä
  2013-06-12 13:49       ` Damien Lespiau
  0 siblings, 1 reply; 84+ messages in thread
From: Ville Syrjälä @ 2013-06-12 13:39 UTC (permalink / raw)
  To: Damien Lespiau; +Cc: Daniel Vetter, Intel Graphics Development

On Wed, Jun 12, 2013 at 02:31:23PM +0100, Damien Lespiau wrote:
> On Wed, Jun 05, 2013 at 01:34:16PM +0200, Daniel Vetter wrote:
> > @@ -8621,6 +8657,17 @@ static void intel_cpu_pll_init(struct drm_device *dev)
> >  		intel_ddi_pll_init(dev);
> >  }
> >  
> > +static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
> > +				      struct intel_shared_dpll *pll,
> > +				      struct intel_dpll_hw_state *hw_state)
> > +{
> > +	uint32_t val;
> > +
> > +	val = I915_READ(PCH_DPLL(pll->id));
> > +
> > +	return val & DPLL_VCO_ENABLE;
> > +}
> > +
> 
> Don't we want !!(val & DPLL_VCO_ENABLE) here? we're comparing this to 0
> and 1.

bool is always 0 or 1.

-- 
Ville Syrjälä
Intel OTC

^ permalink raw reply	[flat|nested] 84+ messages in thread

* Re: [PATCH 14/31] drm/i915: display pll hw state readout and checking
  2013-06-12 13:39     ` Ville Syrjälä
@ 2013-06-12 13:49       ` Damien Lespiau
  0 siblings, 0 replies; 84+ messages in thread
From: Damien Lespiau @ 2013-06-12 13:49 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: Daniel Vetter, Intel Graphics Development

On Wed, Jun 12, 2013 at 04:39:14PM +0300, Ville Syrjälä wrote:
> On Wed, Jun 12, 2013 at 02:31:23PM +0100, Damien Lespiau wrote:
> > On Wed, Jun 05, 2013 at 01:34:16PM +0200, Daniel Vetter wrote:
> > > @@ -8621,6 +8657,17 @@ static void intel_cpu_pll_init(struct drm_device *dev)
> > >  		intel_ddi_pll_init(dev);
> > >  }
> > >  
> > > +static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
> > > +				      struct intel_shared_dpll *pll,
> > > +				      struct intel_dpll_hw_state *hw_state)
> > > +{
> > > +	uint32_t val;
> > > +
> > > +	val = I915_READ(PCH_DPLL(pll->id));
> > > +
> > > +	return val & DPLL_VCO_ENABLE;
> > > +}
> > > +
> > 
> > Don't we want !!(val & DPLL_VCO_ENABLE) here? we're comparing this to 0
> > and 1.
> 
> bool is always 0 or 1.

Oh, of course!

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

then.

-- 
Damien

^ permalink raw reply	[flat|nested] 84+ messages in thread

* Re: [PATCH 15/31] drm/i915: extract readout_hw_state from setup_hw_state
  2013-06-05 11:34 ` [PATCH 15/31] drm/i915: extract readout_hw_state from setup_hw_state Daniel Vetter
  2013-06-12 13:32   ` Damien Lespiau
@ 2013-06-12 14:26   ` Daniel Vetter
  1 sibling, 0 replies; 84+ messages in thread
From: Daniel Vetter @ 2013-06-12 14:26 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

On Wed, Jun 05, 2013 at 01:34:17PM +0200, Daniel Vetter wrote:
> Simply grew too big. This also makes the fixup and restore logic in
> setup_hw_state stand out a bit more clearly.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

So I've managed to massively botch up patch ordering here, due to the lack
of refcount rescostruction but the fact that we already have hw state
readout for the pll selection we hit a bunch of WARNs in the crtc disable
path.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=65673

Damien, can you please take a good hard look at just this patch so that we
can shut up the WARNs?

Thanks, Daniel

> ---
>  drivers/gpu/drm/i915/intel_display.c | 20 +++++++++++++++-----
>  1 file changed, 15 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 998ba5c..95ed27b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9630,14 +9630,10 @@ void i915_redisable_vga(struct drm_device *dev)
>  	}
>  }
>  
> -/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
> - * and i915 state tracking structures. */
> -void intel_modeset_setup_hw_state(struct drm_device *dev,
> -				  bool force_restore)
> +static void intel_modeset_readout_hw_state(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	enum pipe pipe;
> -	struct drm_plane *plane;
>  	struct intel_crtc *crtc;
>  	struct intel_encoder *encoder;
>  	struct intel_connector *connector;
> @@ -9713,6 +9709,20 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
>  			      drm_get_connector_name(&connector->base),
>  			      connector->base.encoder ? "enabled" : "disabled");
>  	}
> +}
> +
> +/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
> + * and i915 state tracking structures. */
> +void intel_modeset_setup_hw_state(struct drm_device *dev,
> +				  bool force_restore)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	enum pipe pipe;
> +	struct drm_plane *plane;
> +	struct intel_crtc *crtc;
> +	struct intel_encoder *encoder;
> +
> +	intel_modeset_readout_hw_state(dev);
>  
>  	/* HW state is read out, now we need to sanitize this mess. */
>  	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
> -- 
> 1.7.11.7
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

^ permalink raw reply	[flat|nested] 84+ messages in thread

* Re: [PATCH 18/31] drm/i915: hw state readout and cross-checking for shared dplls
  2013-06-05 11:34 ` [PATCH 18/31] drm/i915: hw state readout and cross-checking for shared dplls Daniel Vetter
@ 2013-06-12 15:04   ` Damien Lespiau
  0 siblings, 0 replies; 84+ messages in thread
From: Damien Lespiau @ 2013-06-12 15:04 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: Intel Graphics Development

On Wed, Jun 05, 2013 at 01:34:20PM +0200, Daniel Vetter wrote:
> Just the plumbing, all the modeset and enable code has not yet been
> switched over to use the new state. It seems to be decently broken
> anyway, at least wrt to handling of the special pixel mutliplier
> enabling sequence. Follow-up patches will clean up that mess.
> 
> Another missing piece is more careful handling (and fixup) of the fp1
> alternate divisor state. The BIOS most likely doesn't bother to
> program that one to what we expect. So we need to be more careful with
> comparing that state, both for cross checking but also when checking
> for dpll sharing when acquiring shared dpll. Otherwise fastboot will
> deny a few shared dpll configurations which would otherwise work.
> 
> v2: We need to memcpy the pipe config dpll hw state into the pll, for
> otherwise the cross-check code will get angry.
> 
> v3: Don't forget to read the pch pll state in the crtc get_pipe_config
> function for ibx/ilk platforms.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

> ---
>  drivers/gpu/drm/i915/i915_drv.h      |  3 +++
>  drivers/gpu/drm/i915/intel_display.c | 38 ++++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_drv.h     |  3 +++
>  3 files changed, 44 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f23b033..4dc94ed 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -144,6 +144,9 @@ enum intel_dpll_id {
>  #define I915_NUM_PLLS 2
>  
>  struct intel_dpll_hw_state {
> +	uint32_t dpll;
> +	uint32_t fp0;
> +	uint32_t fp1;
>  };
>  
>  struct intel_shared_dpll {
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 388ac54..a30e27a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3055,7 +3055,11 @@ found:
>  	crtc->config.shared_dpll = i;
>  	DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
>  			 pipe_name(crtc->pipe));
> +
>  	if (pll->active == 0) {
> +		memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
> +		       sizeof(pll->hw_state));
> +
>  		DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
>  		WARN_ON(pll->on);
>  		assert_shared_dpll_disabled(dev_priv, pll);
> @@ -5659,6 +5663,13 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
>  					     &fp, &reduced_clock,
>  					     has_reduced_clock ? &fp2 : NULL);
>  
> +		intel_crtc->config.dpll_hw_state.dpll = dpll | DPLL_VCO_ENABLE;
> +		intel_crtc->config.dpll_hw_state.fp0 = fp;
> +		if (has_reduced_clock)
> +			intel_crtc->config.dpll_hw_state.fp1 = fp2;
> +		else
> +			intel_crtc->config.dpll_hw_state.fp1 = fp;
> +
>  		pll = intel_get_shared_dpll(intel_crtc, dpll, fp);
>  		if (pll == NULL) {
>  			DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
> @@ -5778,6 +5789,8 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
>  		return false;
>  
>  	if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
> +		struct intel_shared_dpll *pll;
> +
>  		pipe_config->has_pch_encoder = true;
>  
>  		tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
> @@ -5799,6 +5812,11 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
>  			else
>  				pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
>  		}
> +
> +		pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
> +
> +		WARN_ON(!pll->get_hw_state(dev_priv, pll,
> +					   &pipe_config->dpll_hw_state));
>  	} else {
>  		pipe_config->pixel_multiplier = 1;
>  	}
> @@ -7987,6 +8005,15 @@ intel_pipe_config_compare(struct drm_device *dev,
>  			  struct intel_crtc_config *current_config,
>  			  struct intel_crtc_config *pipe_config)
>  {
> +#define PIPE_CONF_CHECK_X(name)	\
> +	if (current_config->name != pipe_config->name) { \
> +		DRM_ERROR("mismatch in " #name " " \
> +			  "(expected 0x%08x, found 0x%08x)\n", \
> +			  current_config->name, \
> +			  pipe_config->name); \
> +		return false; \
> +	}
> +
>  #define PIPE_CONF_CHECK_I(name)	\
>  	if (current_config->name != pipe_config->name) { \
>  		DRM_ERROR("mismatch in " #name " " \
> @@ -8055,7 +8082,11 @@ intel_pipe_config_compare(struct drm_device *dev,
>  	PIPE_CONF_CHECK_I(ips_enabled);
>  
>  	PIPE_CONF_CHECK_I(shared_dpll);
> +	PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
> +	PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
> +	PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
>  
> +#undef PIPE_CONF_CHECK_X
>  #undef PIPE_CONF_CHECK_I
>  #undef PIPE_CONF_CHECK_FLAGS
>  
> @@ -8237,6 +8268,10 @@ check_shared_dpll_state(struct drm_device *dev)
>  		WARN(pll->refcount != enabled_crtcs,
>  		     "pll enabled crtcs mismatch (expected %i, found %i)\n",
>  		     pll->refcount, enabled_crtcs);
> +
> +		WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
> +				       sizeof(dpll_hw_state)),
> +		     "pll hw state mismatch\n");
>  	}
>  }
>  
> @@ -8692,6 +8727,9 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
>  	uint32_t val;
>  
>  	val = I915_READ(PCH_DPLL(pll->id));
> +	hw_state->dpll = val;
> +	hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
> +	hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
>  
>  	return val & DPLL_VCO_ENABLE;
>  }
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index e0e5d55..6f28375 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -244,6 +244,9 @@ struct intel_crtc_config {
>  	/* Selected dpll when shared or DPLL_ID_PRIVATE. */
>  	enum intel_dpll_id shared_dpll;
>  
> +	/* Actual register state of the dpll, for shared dpll cross-checking. */
> +	struct intel_dpll_hw_state dpll_hw_state;
> +
>  	int pipe_bpp;
>  	struct intel_link_m_n dp_m_n;
>  
> -- 
> 1.7.11.7
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 84+ messages in thread

* Re: [PATCH 19/31] drm/i915: fix up pch pll enabling for pixel multipliers
  2013-06-05 11:34 ` [PATCH 19/31] drm/i915: fix up pch pll enabling for pixel multipliers Daniel Vetter
@ 2013-06-12 15:12   ` Damien Lespiau
  2013-06-12 19:34     ` Daniel Vetter
  0 siblings, 1 reply; 84+ messages in thread
From: Damien Lespiau @ 2013-06-12 15:12 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: Intel Graphics Development

On Wed, Jun 05, 2013 at 01:34:21PM +0200, Daniel Vetter wrote:
> We have a nice comment saying that the pixel multiplier only sticks
> once the vco is on and stable. The only problem is that the enable bit
> wasn't set at all. This patch fixes this and so brings the ilk+ pch
> pll code in line with the i8xx/i9xx pll code. Or at least improves
> matters a lot.
> 
> This should fix sdvo on ilk-ivb for low-res modes.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

> ---
>  drivers/gpu/drm/i915/intel_display.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a30e27a..ecf0b1e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5601,7 +5601,7 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
>  	else
>  		dpll |= PLL_REF_INPUT_DREFCLK;
>  
> -	return dpll;
> +	return dpll | DPLL_VCO_ENABLE;
>  }
>  
>  static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
> @@ -5663,7 +5663,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
>  					     &fp, &reduced_clock,
>  					     has_reduced_clock ? &fp2 : NULL);
>  
> -		intel_crtc->config.dpll_hw_state.dpll = dpll | DPLL_VCO_ENABLE;
> +		intel_crtc->config.dpll_hw_state.dpll = dpll;
>  		intel_crtc->config.dpll_hw_state.fp0 = fp;
>  		if (has_reduced_clock)
>  			intel_crtc->config.dpll_hw_state.fp1 = fp2;
> -- 
> 1.7.11.7
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 84+ messages in thread

* Re: [PATCH 22/31] drm/i915: use sw tracked state to select shared dplls
  2013-06-05 11:34 ` [PATCH 22/31] drm/i915: use sw tracked state to select shared dplls Daniel Vetter
@ 2013-06-12 15:20   ` Damien Lespiau
  0 siblings, 0 replies; 84+ messages in thread
From: Damien Lespiau @ 2013-06-12 15:20 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: Intel Graphics Development

On Wed, Jun 05, 2013 at 01:34:24PM +0200, Daniel Vetter wrote:
> Just yet another prep step to be able to do all this up-front, before
> we've set up any of the shared dplls in the new state. This will
> eventually be useful for atomic modesetting.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

> ---
>  drivers/gpu/drm/i915/intel_display.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 334f86a..4d2284e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2999,7 +2999,7 @@ static void intel_put_shared_dpll(struct intel_crtc *crtc)
>  	crtc->config.shared_dpll = DPLL_ID_NONE;
>  }
>  
> -static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, u32 dpll, u32 fp)
> +static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
>  {
>  	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
>  	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
> @@ -3029,8 +3029,8 @@ static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
>  		if (pll->refcount == 0)
>  			continue;
>  
> -		if (dpll == (I915_READ(PCH_DPLL(pll->id)) & 0x7fffffff) &&
> -		    fp == I915_READ(PCH_FP0(pll->id))) {
> +		if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
> +			   sizeof(pll->hw_state)) == 0) {
>  			DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
>  				      crtc->base.base.id,
>  				      pll->name, pll->refcount, pll->active);
> @@ -5660,7 +5660,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
>  		else
>  			intel_crtc->config.dpll_hw_state.fp1 = fp;
>  
> -		pll = intel_get_shared_dpll(intel_crtc, dpll, fp);
> +		pll = intel_get_shared_dpll(intel_crtc);
>  		if (pll == NULL) {
>  			DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
>  					 pipe_name(pipe));
> -- 
> 1.7.11.7
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 84+ messages in thread

* Re: [PATCH 19/31] drm/i915: fix up pch pll enabling for pixel multipliers
  2013-06-12 15:12   ` Damien Lespiau
@ 2013-06-12 19:34     ` Daniel Vetter
  0 siblings, 0 replies; 84+ messages in thread
From: Daniel Vetter @ 2013-06-12 19:34 UTC (permalink / raw)
  To: Damien Lespiau; +Cc: Daniel Vetter, Intel Graphics Development

On Wed, Jun 12, 2013 at 04:12:48PM +0100, Damien Lespiau wrote:
> On Wed, Jun 05, 2013 at 01:34:21PM +0200, Daniel Vetter wrote:
> > We have a nice comment saying that the pixel multiplier only sticks
> > once the vco is on and stable. The only problem is that the enable bit
> > wasn't set at all. This patch fixes this and so brings the ilk+ pch
> > pll code in line with the i8xx/i9xx pll code. Or at least improves
> > matters a lot.
> > 
> > This should fix sdvo on ilk-ivb for low-res modes.
> > 
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> 
> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

Merged thus far, thanks a lot for the review.
-Daniel

> 
> -- 
> Damien
> 
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index a30e27a..ecf0b1e 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5601,7 +5601,7 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
> >  	else
> >  		dpll |= PLL_REF_INPUT_DREFCLK;
> >  
> > -	return dpll;
> > +	return dpll | DPLL_VCO_ENABLE;
> >  }
> >  
> >  static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
> > @@ -5663,7 +5663,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
> >  					     &fp, &reduced_clock,
> >  					     has_reduced_clock ? &fp2 : NULL);
> >  
> > -		intel_crtc->config.dpll_hw_state.dpll = dpll | DPLL_VCO_ENABLE;
> > +		intel_crtc->config.dpll_hw_state.dpll = dpll;
> >  		intel_crtc->config.dpll_hw_state.fp0 = fp;
> >  		if (has_reduced_clock)
> >  			intel_crtc->config.dpll_hw_state.fp1 = fp2;
> > -- 
> > 1.7.11.7
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

^ permalink raw reply	[flat|nested] 84+ messages in thread

* Re: [PATCH 20/31] drm/i915: simplify the reduced clock handling for pch plls
  2013-06-05 11:34 ` [PATCH 20/31] drm/i915: simplify the reduced clock handling for pch plls Daniel Vetter
@ 2013-06-13 11:26   ` Damien Lespiau
  2013-06-13 11:35     ` Daniel Vetter
  0 siblings, 1 reply; 84+ messages in thread
From: Damien Lespiau @ 2013-06-13 11:26 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: Intel Graphics Development

On Wed, Jun 05, 2013 at 01:34:22PM +0200, Daniel Vetter wrote:
> Just move the lowfreq_avail logic out of the register writing as a
> prep step for the next patch, which will coalesce all the pch pll
> enabling into one spot.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 11 ++++++-----
>  1 file changed, 6 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index ecf0b1e..fc1b5f7 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5686,7 +5686,10 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
>  		if (encoder->pre_pll_enable)
>  			encoder->pre_pll_enable(encoder);
>  
> -	intel_crtc->lowfreq_avail = false;
> +	if (is_lvds && has_reduced_clock && i915_powersave)
> +		intel_crtc->lowfreq_avail = true;

is_lvds doesn't seem necessary as ironlake_compute_clocks() won't set
has_reduced_clock to true if !is_lvds. Doesn't hurt either.

> +	else
> +		intel_crtc->lowfreq_avail = false;
>  
>  	if (intel_crtc->config.has_pch_encoder) {
>  		pll = intel_crtc_to_shared_dpll(intel_crtc);
> @@ -5704,12 +5707,10 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
>  		 */
>  		I915_WRITE(PCH_DPLL(pll->id), dpll);
>  
> -		if (is_lvds && has_reduced_clock && i915_powersave) {
> +		if (has_reduced_clock)
>  			I915_WRITE(PCH_FP1(pll->id), fp2);

Hum this is not quite the same condition? i915_powersave could be false
and we don't want to take that branch? maybe reuse lowfreq_avail?

Maybe compute_clocks() could check i915_powersave itself and set
has_reduced_clock (or use_reduced_clock) correctly.

> -			intel_crtc->lowfreq_avail = true;
> -		} else {
> +		else
>  			I915_WRITE(PCH_FP1(pll->id), fp);
> -		}
>  	}
>  
>  	intel_set_pipe_timings(intel_crtc);
> -- 
> 1.7.11.7
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 84+ messages in thread

* Re: [PATCH 20/31] drm/i915: simplify the reduced clock handling for pch plls
  2013-06-13 11:26   ` Damien Lespiau
@ 2013-06-13 11:35     ` Daniel Vetter
  2013-06-13 12:32       ` Damien Lespiau
  0 siblings, 1 reply; 84+ messages in thread
From: Daniel Vetter @ 2013-06-13 11:35 UTC (permalink / raw)
  To: Damien Lespiau; +Cc: Intel Graphics Development

On Thu, Jun 13, 2013 at 1:26 PM, Damien Lespiau
<damien.lespiau@intel.com> wrote:
> On Wed, Jun 05, 2013 at 01:34:22PM +0200, Daniel Vetter wrote:
>> Just move the lowfreq_avail logic out of the register writing as a
>> prep step for the next patch, which will coalesce all the pch pll
>> enabling into one spot.
>>
>> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>> ---
>>  drivers/gpu/drm/i915/intel_display.c | 11 ++++++-----
>>  1 file changed, 6 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index ecf0b1e..fc1b5f7 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -5686,7 +5686,10 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
>>               if (encoder->pre_pll_enable)
>>                       encoder->pre_pll_enable(encoder);
>>
>> -     intel_crtc->lowfreq_avail = false;
>> +     if (is_lvds && has_reduced_clock && i915_powersave)
>> +             intel_crtc->lowfreq_avail = true;
>
> is_lvds doesn't seem necessary as ironlake_compute_clocks() won't set
> has_reduced_clock to true if !is_lvds. Doesn't hurt either.

I want to move this all into encoder compute_config callbacks anyway,
so that we can neatly subsume eDP DRRS support, too. Until that's
fixed I don't care about a bit of fluff ...

>> +     else
>> +             intel_crtc->lowfreq_avail = false;
>>
>>       if (intel_crtc->config.has_pch_encoder) {
>>               pll = intel_crtc_to_shared_dpll(intel_crtc);
>> @@ -5704,12 +5707,10 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
>>                */
>>               I915_WRITE(PCH_DPLL(pll->id), dpll);
>>
>> -             if (is_lvds && has_reduced_clock && i915_powersave) {
>> +             if (has_reduced_clock)
>>                       I915_WRITE(PCH_FP1(pll->id), fp2);
>
> Hum this is not quite the same condition? i915_powersave could be false
> and we don't want to take that branch? maybe reuse lowfreq_avail?
>
> Maybe compute_clocks() could check i915_powersave itself and set
> has_reduced_clock (or use_reduced_clock) correctly.

Well the entire lowfreq stuff is ripe for overhaul anyway, my plan is
to move it all into the pipe config.

For this case here of writing the FP1 register it doesn't matter if we
uncodntionally do it, since FP1 doesn't have any effect if we don't
enable the lowfreq mode. Which despite the appearance we currently
don't do at all on ilk+ ;-)

I should have mentioned this in the comment message. r-b if I fix that
while applying?
-Daniel

>
>> -                     intel_crtc->lowfreq_avail = true;
>> -             } else {
>> +             else
>>                       I915_WRITE(PCH_FP1(pll->id), fp);
>> -             }
>>       }
>>
>>       intel_set_pipe_timings(intel_crtc);
>> --
>> 1.7.11.7
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

^ permalink raw reply	[flat|nested] 84+ messages in thread

* Re: [PATCH 20/31] drm/i915: simplify the reduced clock handling for pch plls
  2013-06-13 11:35     ` Daniel Vetter
@ 2013-06-13 12:32       ` Damien Lespiau
  2013-06-13 14:33         ` Daniel Vetter
  0 siblings, 1 reply; 84+ messages in thread
From: Damien Lespiau @ 2013-06-13 12:32 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: Intel Graphics Development

On Thu, Jun 13, 2013 at 01:35:44PM +0200, Daniel Vetter wrote:
> On Thu, Jun 13, 2013 at 1:26 PM, Damien Lespiau
> <damien.lespiau@intel.com> wrote:
> > On Wed, Jun 05, 2013 at 01:34:22PM +0200, Daniel Vetter wrote:
> >> Just move the lowfreq_avail logic out of the register writing as a
> >> prep step for the next patch, which will coalesce all the pch pll
> >> enabling into one spot.
> >>
> >> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> >> ---
> >>  drivers/gpu/drm/i915/intel_display.c | 11 ++++++-----
> >>  1 file changed, 6 insertions(+), 5 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> >> index ecf0b1e..fc1b5f7 100644
> >> --- a/drivers/gpu/drm/i915/intel_display.c
> >> +++ b/drivers/gpu/drm/i915/intel_display.c
> >> @@ -5686,7 +5686,10 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
> >>               if (encoder->pre_pll_enable)
> >>                       encoder->pre_pll_enable(encoder);
> >>
> >> -     intel_crtc->lowfreq_avail = false;
> >> +     if (is_lvds && has_reduced_clock && i915_powersave)
> >> +             intel_crtc->lowfreq_avail = true;
> >
> > is_lvds doesn't seem necessary as ironlake_compute_clocks() won't set
> > has_reduced_clock to true if !is_lvds. Doesn't hurt either.
> 
> I want to move this all into encoder compute_config callbacks anyway,
> so that we can neatly subsume eDP DRRS support, too. Until that's
> fixed I don't care about a bit of fluff ...
> 
> >> +     else
> >> +             intel_crtc->lowfreq_avail = false;
> >>
> >>       if (intel_crtc->config.has_pch_encoder) {
> >>               pll = intel_crtc_to_shared_dpll(intel_crtc);
> >> @@ -5704,12 +5707,10 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
> >>                */
> >>               I915_WRITE(PCH_DPLL(pll->id), dpll);
> >>
> >> -             if (is_lvds && has_reduced_clock && i915_powersave) {
> >> +             if (has_reduced_clock)
> >>                       I915_WRITE(PCH_FP1(pll->id), fp2);
> >
> > Hum this is not quite the same condition? i915_powersave could be false
> > and we don't want to take that branch? maybe reuse lowfreq_avail?
> >
> > Maybe compute_clocks() could check i915_powersave itself and set
> > has_reduced_clock (or use_reduced_clock) correctly.
> 
> Well the entire lowfreq stuff is ripe for overhaul anyway, my plan is
> to move it all into the pipe config.
> 
> For this case here of writing the FP1 register it doesn't matter if we
> uncodntionally do it, since FP1 doesn't have any effect if we don't
> enable the lowfreq mode. Which despite the appearance we currently
> don't do at all on ilk+ ;-)
> 
> I should have mentioned this in the comment message. r-b if I fix that
> while applying?

yes!

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

> -Daniel
> 
> >
> >> -                     intel_crtc->lowfreq_avail = true;
> >> -             } else {
> >> +             else
> >>                       I915_WRITE(PCH_FP1(pll->id), fp);
> >> -             }
> >>       }
> >>
> >>       intel_set_pipe_timings(intel_crtc);
> >> --
> >> 1.7.11.7
> >>
> >> _______________________________________________
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
> 
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch

^ permalink raw reply	[flat|nested] 84+ messages in thread

* Re: [PATCH 20/31] drm/i915: simplify the reduced clock handling for pch plls
  2013-06-13 12:32       ` Damien Lespiau
@ 2013-06-13 14:33         ` Daniel Vetter
  0 siblings, 0 replies; 84+ messages in thread
From: Daniel Vetter @ 2013-06-13 14:33 UTC (permalink / raw)
  To: Damien Lespiau; +Cc: Daniel Vetter, Intel Graphics Development

On Thu, Jun 13, 2013 at 01:32:03PM +0100, Damien Lespiau wrote:
> On Thu, Jun 13, 2013 at 01:35:44PM +0200, Daniel Vetter wrote:
> > On Thu, Jun 13, 2013 at 1:26 PM, Damien Lespiau
> > <damien.lespiau@intel.com> wrote:
> > > On Wed, Jun 05, 2013 at 01:34:22PM +0200, Daniel Vetter wrote:
> > >> Just move the lowfreq_avail logic out of the register writing as a
> > >> prep step for the next patch, which will coalesce all the pch pll
> > >> enabling into one spot.
> > >>
> > >> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> > >> ---
> > >>  drivers/gpu/drm/i915/intel_display.c | 11 ++++++-----
> > >>  1 file changed, 6 insertions(+), 5 deletions(-)
> > >>
> > >> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > >> index ecf0b1e..fc1b5f7 100644
> > >> --- a/drivers/gpu/drm/i915/intel_display.c
> > >> +++ b/drivers/gpu/drm/i915/intel_display.c
> > >> @@ -5686,7 +5686,10 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
> > >>               if (encoder->pre_pll_enable)
> > >>                       encoder->pre_pll_enable(encoder);
> > >>
> > >> -     intel_crtc->lowfreq_avail = false;
> > >> +     if (is_lvds && has_reduced_clock && i915_powersave)
> > >> +             intel_crtc->lowfreq_avail = true;
> > >
> > > is_lvds doesn't seem necessary as ironlake_compute_clocks() won't set
> > > has_reduced_clock to true if !is_lvds. Doesn't hurt either.
> > 
> > I want to move this all into encoder compute_config callbacks anyway,
> > so that we can neatly subsume eDP DRRS support, too. Until that's
> > fixed I don't care about a bit of fluff ...
> > 
> > >> +     else
> > >> +             intel_crtc->lowfreq_avail = false;
> > >>
> > >>       if (intel_crtc->config.has_pch_encoder) {
> > >>               pll = intel_crtc_to_shared_dpll(intel_crtc);
> > >> @@ -5704,12 +5707,10 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
> > >>                */
> > >>               I915_WRITE(PCH_DPLL(pll->id), dpll);
> > >>
> > >> -             if (is_lvds && has_reduced_clock && i915_powersave) {
> > >> +             if (has_reduced_clock)
> > >>                       I915_WRITE(PCH_FP1(pll->id), fp2);
> > >
> > > Hum this is not quite the same condition? i915_powersave could be false
> > > and we don't want to take that branch? maybe reuse lowfreq_avail?
> > >
> > > Maybe compute_clocks() could check i915_powersave itself and set
> > > has_reduced_clock (or use_reduced_clock) correctly.
> > 
> > Well the entire lowfreq stuff is ripe for overhaul anyway, my plan is
> > to move it all into the pipe config.
> > 
> > For this case here of writing the FP1 register it doesn't matter if we
> > uncodntionally do it, since FP1 doesn't have any effect if we don't
> > enable the lowfreq mode. Which despite the appearance we currently
> > don't do at all on ilk+ ;-)
> > 
> > I should have mentioned this in the comment message. r-b if I fix that
> > while applying?
> 
> yes!

Added ...

> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

... and queued for -next, thanks for the review.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

^ permalink raw reply	[flat|nested] 84+ messages in thread

* Re: [PATCH 24/31] drm/i915: asserts for lvds pre_enable
  2013-06-05 11:34 ` [PATCH 24/31] drm/i915: asserts for lvds pre_enable Daniel Vetter
@ 2013-06-13 20:26   ` Imre Deak
  2013-06-13 20:46     ` Daniel Vetter
  2013-06-16 19:42     ` [PATCH] " Daniel Vetter
  0 siblings, 2 replies; 84+ messages in thread
From: Imre Deak @ 2013-06-13 20:26 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: Intel Graphics Development

On Wed, 2013-06-05 at 13:34 +0200, Daniel Vetter wrote:
> Lots of bangin my head against the wall^UExperiments have shown that
> we really need to enable the lvds port before we enable plls. Strangely
> that seems to include the fdi rx pll on the pch.
> 
> Anyway, encode this new evidence with a few nice WARNs.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 23 ++++++++++-------------
>  drivers/gpu/drm/i915/intel_drv.h     | 16 ++++++++++++++++
>  drivers/gpu/drm/i915/intel_lvds.c    | 17 ++++++++++++-----
>  3 files changed, 38 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 5d84fea..7b34a92 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -874,8 +874,8 @@ static const char *state_string(bool enabled)
>  }
>  
>  /* Only for pre-ILK configs */
> -static void assert_pll(struct drm_i915_private *dev_priv,
> -		       enum pipe pipe, bool state)
> +void assert_pll(struct drm_i915_private *dev_priv,
> +		enum pipe pipe, bool state)
>  {
>  	int reg;
>  	u32 val;
> @@ -888,10 +888,8 @@ static void assert_pll(struct drm_i915_private *dev_priv,
>  	     "PLL state assertion failure (expected %s, current %s)\n",
>  	     state_string(state), state_string(cur_state));
>  }
> -#define assert_pll_enabled(d, p) assert_pll(d, p, true)
> -#define assert_pll_disabled(d, p) assert_pll(d, p, false)
>  
> -static struct intel_shared_dpll *
> +struct intel_shared_dpll *
>  intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
>  {
>  	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
> @@ -903,9 +901,9 @@ intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
>  }
>  
>  /* For ILK+ */
> -static void assert_shared_dpll(struct drm_i915_private *dev_priv,
> -			       struct intel_shared_dpll *pll,
> -			       bool state)
> +void assert_shared_dpll(struct drm_i915_private *dev_priv,
> +			struct intel_shared_dpll *pll,
> +			bool state)
>  {
>  	bool cur_state;
>  	struct intel_dpll_hw_state hw_state;
> @@ -924,8 +922,6 @@ static void assert_shared_dpll(struct drm_i915_private *dev_priv,
>  	     "%s assertion failure (expected %s, current %s)\n",
>  	     pll->name, state_string(state), state_string(cur_state));
>  }
> -#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
> -#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
>  
>  static void assert_fdi_tx(struct drm_i915_private *dev_priv,
>  			  enum pipe pipe, bool state)
> @@ -989,15 +985,16 @@ static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
>  	WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
>  }
>  
> -static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
> -				      enum pipe pipe)
> +void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
> +		       enum pipe pipe, bool state)
>  {
>  	int reg;
>  	u32 val;
>  
>  	reg = FDI_RX_CTL(pipe);
>  	val = I915_READ(reg);
> -	WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
> +	WARN(!!(val & FDI_RX_PLL_ENABLE) != state,
> +	     "FDI RX PLL assertion failure, should be active but is disabled\n");

The message should be updated too.

>  }
>  
>  static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 6f28375..ea8aa5e 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -732,6 +732,22 @@ extern int intel_overlay_attrs(struct drm_device *dev, void *data,
>  extern void intel_fb_output_poll_changed(struct drm_device *dev);
>  extern void intel_fb_restore_mode(struct drm_device *dev);
>  
> +struct intel_shared_dpll *
> +intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
> +
> +void assert_shared_dpll(struct drm_i915_private *dev_priv,
> +			struct intel_shared_dpll *pll,
> +			bool state);
> +#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
> +#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
> +void assert_pll(struct drm_i915_private *dev_priv,
> +		enum pipe pipe, bool state);
> +#define assert_pll_enabled(d, p) assert_pll(d, p, true)
> +#define assert_pll_disabled(d, p) assert_pll(d, p, false)
> +void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
> +		       enum pipe pipe, bool state);
> +#define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
> +#define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
>  extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
>  			bool state);
>  #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
> index 159aa9f..36f8901 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -120,12 +120,20 @@ static void intel_pre_pll_enable_lvds(struct intel_encoder *encoder)
>  	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
>  	struct drm_device *dev = encoder->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
>  	struct drm_display_mode *fixed_mode =
>  		lvds_encoder->attached_connector->base.panel.fixed_mode;
> -	int pipe = intel_crtc->pipe;
> +	int pipe = crtc->pipe;
>  	u32 temp;
>  
> +	if (HAS_PCH_SPLIT(dev)) {
> +		assert_fdi_rx_pll_disabled(dev_priv, pipe);
> +		assert_shared_dpll_disabled(dev_priv,
> +					    intel_crtc_to_shared_dpll(crtc));

I think if we pick a shared PLL that is currently used by another port
this will trigger. Should the PLL selection be limited to non-shared
PLLs for LVDS?

> +	} else {
> +		assert_pll_disabled(dev_priv, pipe);
> +	}
> +
>  	temp = I915_READ(lvds_encoder->reg);
>  	temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
>  
> @@ -142,7 +150,7 @@ static void intel_pre_pll_enable_lvds(struct intel_encoder *encoder)
>  
>  	/* set the corresponsding LVDS_BORDER bit */
>  	temp &= ~LVDS_BORDER_ENABLE;
> -	temp |= intel_crtc->config.gmch_pfit.lvds_border_bits;
> +	temp |= crtc->config.gmch_pfit.lvds_border_bits;
>  	/* Set the B0-B3 data pairs corresponding to whether we're going to
>  	 * set the DPLLs for dual-channel mode or not.
>  	 */
> @@ -162,8 +170,7 @@ static void intel_pre_pll_enable_lvds(struct intel_encoder *encoder)
>  	if (INTEL_INFO(dev)->gen == 4) {
>  		/* Bspec wording suggests that LVDS port dithering only exists
>  		 * for 18bpp panels. */
> -		if (intel_crtc->config.dither &&
> -		    intel_crtc->config.pipe_bpp == 18)
> +		if (crtc->config.dither && crtc->config.pipe_bpp == 18)
>  			temp |= LVDS_ENABLE_DITHER;
>  		else
>  			temp &= ~LVDS_ENABLE_DITHER;

^ permalink raw reply	[flat|nested] 84+ messages in thread

* Re: [PATCH 24/31] drm/i915: asserts for lvds pre_enable
  2013-06-13 20:26   ` Imre Deak
@ 2013-06-13 20:46     ` Daniel Vetter
  2013-06-14 10:45       ` Imre Deak
  2013-06-16 19:42     ` [PATCH] " Daniel Vetter
  1 sibling, 1 reply; 84+ messages in thread
From: Daniel Vetter @ 2013-06-13 20:46 UTC (permalink / raw)
  To: Imre Deak; +Cc: Intel Graphics Development

On Thu, Jun 13, 2013 at 10:26 PM, Imre Deak <imre.deak@intel.com> wrote:
>> +     if (HAS_PCH_SPLIT(dev)) {
>> +             assert_fdi_rx_pll_disabled(dev_priv, pipe);
>> +             assert_shared_dpll_disabled(dev_priv,
>> +                                         intel_crtc_to_shared_dpll(crtc));
>
> I think if we pick a shared PLL that is currently used by another port
> this will trigger. Should the PLL selection be limited to non-shared
> PLLs for LVDS?

LVDS has a special clock selection setting and there's only eve one
LVDS port on any given machine. Which means we won't ever be able to
share the dpll with anything else. I'll add this to the commit message
when I resend the patch to fix up the debug output.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

^ permalink raw reply	[flat|nested] 84+ messages in thread

* Re: [PATCH 24/31] drm/i915: asserts for lvds pre_enable
  2013-06-13 20:46     ` Daniel Vetter
@ 2013-06-14 10:45       ` Imre Deak
  0 siblings, 0 replies; 84+ messages in thread
From: Imre Deak @ 2013-06-14 10:45 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: Intel Graphics Development

On Thu, 2013-06-13 at 22:46 +0200, Daniel Vetter wrote:
> On Thu, Jun 13, 2013 at 10:26 PM, Imre Deak <imre.deak@intel.com> wrote:
> >> +     if (HAS_PCH_SPLIT(dev)) {
> >> +             assert_fdi_rx_pll_disabled(dev_priv, pipe);
> >> +             assert_shared_dpll_disabled(dev_priv,
> >> +                                         intel_crtc_to_shared_dpll(crtc));
> >
> > I think if we pick a shared PLL that is currently used by another port
> > this will trigger. Should the PLL selection be limited to non-shared
> > PLLs for LVDS?
> 
> LVDS has a special clock selection setting and there's only eve one
> LVDS port on any given machine. Which means we won't ever be able to
> share the dpll with anything else.

Ok, I should've looked closer and realize that dpll matching is not only
about rate matching, but also matching the rest of dpll mode bits. But
it's clear now we can't get here with a shared dpll, so the assert is
ok.

> I'll add this to the commit message when I resend the patch to fix up
> the debug output.

Ok.

--Imre

^ permalink raw reply	[flat|nested] 84+ messages in thread

* Re: [PATCH 27/31] drm/i915: move i9xx dpll enabling into crtc enable function
  2013-06-05 11:34 ` [PATCH 27/31] drm/i915: move i9xx dpll enabling into crtc enable function Daniel Vetter
  2013-06-05 15:13   ` Jani Nikula
@ 2013-06-14 16:02   ` Imre Deak
  2013-06-16 19:15     ` Daniel Vetter
  2013-06-16 19:24     ` [PATCH] " Daniel Vetter
  1 sibling, 2 replies; 84+ messages in thread
From: Imre Deak @ 2013-06-14 16:02 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: Intel Graphics Development

On Wed, 2013-06-05 at 13:34 +0200, Daniel Vetter wrote:
> Now that we have the proper pipe config to track this, we don't need
> to write any registers any more.
> 
> v2: Drop a few now unnecessary local variables and switch the enable
> function to take a struct intel_crtc * to simply arguments.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 102 +++++++++++++----------------------
>  1 file changed, 37 insertions(+), 65 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b9be047..b6f5e48 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1298,32 +1298,48 @@ static void vlv_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
>  	udelay(150); /* wait for warmup */
>  }
>  
> -static void i9xx_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
> +static void i9xx_enable_pll(struct intel_crtc *crtc)
>  {
> -	int reg;
> -	u32 val;
> +	struct drm_device *dev = crtc->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	int reg = DPLL(crtc->pipe);
> +	u32 dpll = crtc->config.dpll_hw_state.dpll;
>  
> -	assert_pipe_disabled(dev_priv, pipe);
> +	assert_pipe_disabled(dev_priv, crtc->pipe);
>  
>  	/* No really, not for ILK+ */
> -	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
> +	BUG_ON(!IS_VALLEYVIEW(dev) && dev_priv->info->gen >= 5);
>  
>  	/* PLL is protected by panel, make sure we can write it */
> -	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
> -		assert_panel_unlocked(dev_priv, pipe);
> +	if (IS_MOBILE(dev) && !IS_I830(dev))
> +		assert_panel_unlocked(dev_priv, crtc->pipe);
>  
> -	reg = DPLL(pipe);
> -	val = I915_READ(reg);
> -	val |= DPLL_VCO_ENABLE;
> +	I915_WRITE(reg, dpll);
> +
> +	/* Wait for the clocks to stabilize. */
> +	POSTING_READ(reg);
> +	udelay(150);
> +
> +	if (INTEL_INFO(dev)->gen >= 4) {
> +		I915_WRITE(DPLL_MD(crtc->pipe),
> +			   crtc->config.dpll_hw_state.dpll_md);
> +	} else {
> +		/* The pixel multiplier can only be updated once the
> +		 * DPLL is enabled and the clocks are stable.
> +		 *
> +		 * So write it again.
> +		 */
> +		I915_WRITE(reg, dpll);

It's ok but isn't really needed any more as now we write dpll right
after this with the same value.

> +	}
>  
>  	/* We do this three times for luck */
> -	I915_WRITE(reg, val);
> +	I915_WRITE(reg, dpll);
>  	POSTING_READ(reg);
>  	udelay(150); /* wait for warmup */
> -	I915_WRITE(reg, val);
> +	I915_WRITE(reg, dpll);
>  	POSTING_READ(reg);
>  	udelay(150); /* wait for warmup */
> -	I915_WRITE(reg, val);
> +	I915_WRITE(reg, dpll);
>  	POSTING_READ(reg);
>  	udelay(150); /* wait for warmup */
>  }
> @@ -3591,7 +3607,11 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
>  	intel_crtc->active = true;
>  	intel_update_watermarks(dev);
>  
> -	i9xx_enable_pll(dev_priv, pipe);
> +	for_each_encoder_on_crtc(dev, crtc, encoder)
> +		if (encoder->pre_pll_enable)
> +			encoder->pre_pll_enable(encoder);
> +
> +	i9xx_enable_pll(intel_crtc);
>  
>  	for_each_encoder_on_crtc(dev, crtc, encoder)
>  		if (encoder->pre_enable)
> @@ -4429,8 +4449,6 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
>  {
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_encoder *encoder;
> -	int pipe = crtc->pipe;
>  	u32 dpll;
>  	bool is_sdvo;
>  	struct dpll *clock = &crtc->config.dpll;
> @@ -4494,37 +4512,14 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
>  	dpll |= DPLL_VCO_ENABLE;
>  	crtc->config.dpll_hw_state.dpll = dpll;
>  
> -	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
> -	POSTING_READ(DPLL(pipe));
> -	udelay(150);
> -
> -	for_each_encoder_on_crtc(dev, &crtc->base, encoder)
> -		if (encoder->pre_pll_enable)
> -			encoder->pre_pll_enable(encoder);
> -
> -	if (crtc->config.has_dp_encoder)
> -		intel_dp_set_m_n(crtc);
> -
> -	I915_WRITE(DPLL(pipe), dpll);
> -
> -	/* Wait for the clocks to stabilize. */
> -	POSTING_READ(DPLL(pipe));
> -	udelay(150);
> -
>  	if (INTEL_INFO(dev)->gen >= 4) {
>  		u32 dpll_md = (crtc->config.pixel_multiplier - 1)
>  			<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
>  		crtc->config.dpll_hw_state.dpll_md = dpll_md;
> -
> -		I915_WRITE(DPLL_MD(pipe), dpll_md);
> -	} else {
> -		/* The pixel multiplier can only be updated once the
> -		 * DPLL is enabled and the clocks are stable.
> -		 *
> -		 * So write it again.
> -		 */
> -		I915_WRITE(DPLL(pipe), dpll);
>  	}
> +
> +	if (crtc->config.has_dp_encoder)
> +		intel_dp_set_m_n(crtc);
>  }
>  
>  static void i8xx_update_pll(struct intel_crtc *crtc,
> @@ -4533,8 +4528,6 @@ static void i8xx_update_pll(struct intel_crtc *crtc,
>  {
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_encoder *encoder;
> -	int pipe = crtc->pipe;
>  	u32 dpll;
>  	struct dpll *clock = &crtc->config.dpll;
>  
> @@ -4561,27 +4554,6 @@ static void i8xx_update_pll(struct intel_crtc *crtc,
>  
>  	dpll |= DPLL_VCO_ENABLE;
>  	crtc->config.dpll_hw_state.dpll = dpll;
> -
> -	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
> -	POSTING_READ(DPLL(pipe));
> -	udelay(150);
> -
> -	for_each_encoder_on_crtc(dev, &crtc->base, encoder)
> -		if (encoder->pre_pll_enable)
> -			encoder->pre_pll_enable(encoder);
> -
> -	I915_WRITE(DPLL(pipe), dpll);
> -
> -	/* Wait for the clocks to stabilize. */
> -	POSTING_READ(DPLL(pipe));
> -	udelay(150);
> -
> -	/* The pixel multiplier can only be updated once the
> -	 * DPLL is enabled and the clocks are stable.
> -	 *
> -	 * So write it again.
> -	 */
> -	I915_WRITE(DPLL(pipe), dpll);
>  }
>  
>  static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)

^ permalink raw reply	[flat|nested] 84+ messages in thread

* Re: [PATCH 28/31] drm/i915: s/pre_pll/pre/ on the lvds port enable function
  2013-06-05 11:34 ` [PATCH 28/31] drm/i915: s/pre_pll/pre/ on the lvds port " Daniel Vetter
@ 2013-06-15  8:32   ` Imre Deak
  2013-06-26 10:02     ` Daniel Vetter
  0 siblings, 1 reply; 84+ messages in thread
From: Imre Deak @ 2013-06-15  8:32 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: Intel Graphics Development

On Wed, 2013-06-05 at 13:34 +0200, Daniel Vetter wrote:
> i9xx doesn't use pre_enable at all, so we can fold this in now.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

I managed to review 23-28 for now, so on those apart from the two
nitpicks:

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 13 +++----------
>  drivers/gpu/drm/i915/intel_lvds.c    |  4 ++--
>  2 files changed, 5 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b6f5e48..2e30f45 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3157,12 +3157,9 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
>  
>  	intel_update_watermarks(dev);
>  
> -	for_each_encoder_on_crtc(dev, crtc, encoder) {
> -		if (encoder->pre_pll_enable)
> -			encoder->pre_pll_enable(encoder);
> +	for_each_encoder_on_crtc(dev, crtc, encoder)
>  		if (encoder->pre_enable)
>  			encoder->pre_enable(encoder);
> -	}
>  
>  	if (intel_crtc->config.has_pch_encoder) {
>  		/* Note: FDI PLL enabling _must_ be done before we enable the
> @@ -3608,15 +3605,11 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
>  	intel_update_watermarks(dev);
>  
>  	for_each_encoder_on_crtc(dev, crtc, encoder)
> -		if (encoder->pre_pll_enable)
> -			encoder->pre_pll_enable(encoder);
> -
> -	i9xx_enable_pll(intel_crtc);
> -
> -	for_each_encoder_on_crtc(dev, crtc, encoder)
>  		if (encoder->pre_enable)
>  			encoder->pre_enable(encoder);
>  
> +	i9xx_enable_pll(intel_crtc);
> +
>  	/* Enable panel fitting for LVDS */
>  	i9xx_pfit_enable(intel_crtc);
>  
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
> index 36f8901..b2a4894 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -115,7 +115,7 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
>   * This is an exception to the general rule that mode_set doesn't turn
>   * things on.
>   */
> -static void intel_pre_pll_enable_lvds(struct intel_encoder *encoder)
> +static void intel_pre_enable_lvds(struct intel_encoder *encoder)
>  {
>  	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
>  	struct drm_device *dev = encoder->base.dev;
> @@ -946,7 +946,7 @@ bool intel_lvds_init(struct drm_device *dev)
>  			 DRM_MODE_ENCODER_LVDS);
>  
>  	intel_encoder->enable = intel_enable_lvds;
> -	intel_encoder->pre_pll_enable = intel_pre_pll_enable_lvds;
> +	intel_encoder->pre_enable = intel_pre_enable_lvds;
>  	intel_encoder->compute_config = intel_lvds_compute_config;
>  	intel_encoder->disable = intel_disable_lvds;
>  	intel_encoder->get_hw_state = intel_lvds_get_hw_state;

^ permalink raw reply	[flat|nested] 84+ messages in thread

* Re: [PATCH 27/31] drm/i915: move i9xx dpll enabling into crtc enable function
  2013-06-14 16:02   ` [PATCH 27/31] " Imre Deak
@ 2013-06-16 19:15     ` Daniel Vetter
  2013-06-16 19:24     ` [PATCH] " Daniel Vetter
  1 sibling, 0 replies; 84+ messages in thread
From: Daniel Vetter @ 2013-06-16 19:15 UTC (permalink / raw)
  To: Imre Deak; +Cc: Daniel Vetter, Intel Graphics Development

On Fri, Jun 14, 2013 at 07:02:17PM +0300, Imre Deak wrote:
> On Wed, 2013-06-05 at 13:34 +0200, Daniel Vetter wrote:
> > Now that we have the proper pipe config to track this, we don't need
> > to write any registers any more.
> > 
> > v2: Drop a few now unnecessary local variables and switch the enable
> > function to take a struct intel_crtc * to simply arguments.
> > 
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 102 +++++++++++++----------------------
> >  1 file changed, 37 insertions(+), 65 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index b9be047..b6f5e48 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -1298,32 +1298,48 @@ static void vlv_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
> >  	udelay(150); /* wait for warmup */
> >  }
> >  
> > -static void i9xx_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
> > +static void i9xx_enable_pll(struct intel_crtc *crtc)
> >  {
> > -	int reg;
> > -	u32 val;
> > +	struct drm_device *dev = crtc->base.dev;
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	int reg = DPLL(crtc->pipe);
> > +	u32 dpll = crtc->config.dpll_hw_state.dpll;
> >  
> > -	assert_pipe_disabled(dev_priv, pipe);
> > +	assert_pipe_disabled(dev_priv, crtc->pipe);
> >  
> >  	/* No really, not for ILK+ */
> > -	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
> > +	BUG_ON(!IS_VALLEYVIEW(dev) && dev_priv->info->gen >= 5);
> >  
> >  	/* PLL is protected by panel, make sure we can write it */
> > -	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
> > -		assert_panel_unlocked(dev_priv, pipe);
> > +	if (IS_MOBILE(dev) && !IS_I830(dev))
> > +		assert_panel_unlocked(dev_priv, crtc->pipe);
> >  
> > -	reg = DPLL(pipe);
> > -	val = I915_READ(reg);
> > -	val |= DPLL_VCO_ENABLE;
> > +	I915_WRITE(reg, dpll);
> > +
> > +	/* Wait for the clocks to stabilize. */
> > +	POSTING_READ(reg);
> > +	udelay(150);
> > +
> > +	if (INTEL_INFO(dev)->gen >= 4) {
> > +		I915_WRITE(DPLL_MD(crtc->pipe),
> > +			   crtc->config.dpll_hw_state.dpll_md);
> > +	} else {
> > +		/* The pixel multiplier can only be updated once the
> > +		 * DPLL is enabled and the clocks are stable.
> > +		 *
> > +		 * So write it again.
> > +		 */
> > +		I915_WRITE(reg, dpll);
> 
> It's ok but isn't really needed any more as now we write dpll right
> after this with the same value.

The "do this trice for luck" comment below doesn't inspire confidence.
I'll amend the commit message to explain why I'll decided to keep things
as much as possible as they've been.
-Daniel

> 
> > +	}
> >  
> >  	/* We do this three times for luck */
> > -	I915_WRITE(reg, val);
> > +	I915_WRITE(reg, dpll);
> >  	POSTING_READ(reg);
> >  	udelay(150); /* wait for warmup */
> > -	I915_WRITE(reg, val);
> > +	I915_WRITE(reg, dpll);
> >  	POSTING_READ(reg);
> >  	udelay(150); /* wait for warmup */
> > -	I915_WRITE(reg, val);
> > +	I915_WRITE(reg, dpll);
> >  	POSTING_READ(reg);
> >  	udelay(150); /* wait for warmup */
> >  }
> > @@ -3591,7 +3607,11 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
> >  	intel_crtc->active = true;
> >  	intel_update_watermarks(dev);
> >  
> > -	i9xx_enable_pll(dev_priv, pipe);
> > +	for_each_encoder_on_crtc(dev, crtc, encoder)
> > +		if (encoder->pre_pll_enable)
> > +			encoder->pre_pll_enable(encoder);
> > +
> > +	i9xx_enable_pll(intel_crtc);
> >  
> >  	for_each_encoder_on_crtc(dev, crtc, encoder)
> >  		if (encoder->pre_enable)
> > @@ -4429,8 +4449,6 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
> >  {
> >  	struct drm_device *dev = crtc->base.dev;
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > -	struct intel_encoder *encoder;
> > -	int pipe = crtc->pipe;
> >  	u32 dpll;
> >  	bool is_sdvo;
> >  	struct dpll *clock = &crtc->config.dpll;
> > @@ -4494,37 +4512,14 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
> >  	dpll |= DPLL_VCO_ENABLE;
> >  	crtc->config.dpll_hw_state.dpll = dpll;
> >  
> > -	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
> > -	POSTING_READ(DPLL(pipe));
> > -	udelay(150);
> > -
> > -	for_each_encoder_on_crtc(dev, &crtc->base, encoder)
> > -		if (encoder->pre_pll_enable)
> > -			encoder->pre_pll_enable(encoder);
> > -
> > -	if (crtc->config.has_dp_encoder)
> > -		intel_dp_set_m_n(crtc);
> > -
> > -	I915_WRITE(DPLL(pipe), dpll);
> > -
> > -	/* Wait for the clocks to stabilize. */
> > -	POSTING_READ(DPLL(pipe));
> > -	udelay(150);
> > -
> >  	if (INTEL_INFO(dev)->gen >= 4) {
> >  		u32 dpll_md = (crtc->config.pixel_multiplier - 1)
> >  			<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
> >  		crtc->config.dpll_hw_state.dpll_md = dpll_md;
> > -
> > -		I915_WRITE(DPLL_MD(pipe), dpll_md);
> > -	} else {
> > -		/* The pixel multiplier can only be updated once the
> > -		 * DPLL is enabled and the clocks are stable.
> > -		 *
> > -		 * So write it again.
> > -		 */
> > -		I915_WRITE(DPLL(pipe), dpll);
> >  	}
> > +
> > +	if (crtc->config.has_dp_encoder)
> > +		intel_dp_set_m_n(crtc);
> >  }
> >  
> >  static void i8xx_update_pll(struct intel_crtc *crtc,
> > @@ -4533,8 +4528,6 @@ static void i8xx_update_pll(struct intel_crtc *crtc,
> >  {
> >  	struct drm_device *dev = crtc->base.dev;
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > -	struct intel_encoder *encoder;
> > -	int pipe = crtc->pipe;
> >  	u32 dpll;
> >  	struct dpll *clock = &crtc->config.dpll;
> >  
> > @@ -4561,27 +4554,6 @@ static void i8xx_update_pll(struct intel_crtc *crtc,
> >  
> >  	dpll |= DPLL_VCO_ENABLE;
> >  	crtc->config.dpll_hw_state.dpll = dpll;
> > -
> > -	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
> > -	POSTING_READ(DPLL(pipe));
> > -	udelay(150);
> > -
> > -	for_each_encoder_on_crtc(dev, &crtc->base, encoder)
> > -		if (encoder->pre_pll_enable)
> > -			encoder->pre_pll_enable(encoder);
> > -
> > -	I915_WRITE(DPLL(pipe), dpll);
> > -
> > -	/* Wait for the clocks to stabilize. */
> > -	POSTING_READ(DPLL(pipe));
> > -	udelay(150);
> > -
> > -	/* The pixel multiplier can only be updated once the
> > -	 * DPLL is enabled and the clocks are stable.
> > -	 *
> > -	 * So write it again.
> > -	 */
> > -	I915_WRITE(DPLL(pipe), dpll);
> >  }
> >  
> >  static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
> 
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

^ permalink raw reply	[flat|nested] 84+ messages in thread

* [PATCH] drm/i915: move i9xx dpll enabling into crtc enable function
  2013-06-14 16:02   ` [PATCH 27/31] " Imre Deak
  2013-06-16 19:15     ` Daniel Vetter
@ 2013-06-16 19:24     ` Daniel Vetter
  1 sibling, 0 replies; 84+ messages in thread
From: Daniel Vetter @ 2013-06-16 19:24 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

Now that we have the proper pipe config to track this, we don't need
to write any registers any more.

Note that for platforms without DPLL_MD (pre-gen4) which store the
pixel mutliplier in the DPLL register I've decided to keep the
seemingly "redundant" write: The comment right below saying "do this
trice for luck" doesn't instill confidence ...

v2: Drop a few now unnecessary local variables and switch the enable
function to take a struct intel_crtc * to simply arguments.

v3: Rebase on top of the newly-colored BUG_ON.

v4: Amend commit message to alliviate Imre's comment about the
redudant DPLL write for the pixel mutliplier.

Cc: Imre Deak <imre.deak@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 100 +++++++++++++----------------------
 1 file changed, 36 insertions(+), 64 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f66eee9..7c0d107 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1310,32 +1310,48 @@ static void vlv_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
 	udelay(150); /* wait for warmup */
 }
 
-static void i9xx_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
+static void i9xx_enable_pll(struct intel_crtc *crtc)
 {
-	int reg;
-	u32 val;
+	struct drm_device *dev = crtc->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int reg = DPLL(crtc->pipe);
+	u32 dpll = crtc->config.dpll_hw_state.dpll;
 
-	assert_pipe_disabled(dev_priv, pipe);
+	assert_pipe_disabled(dev_priv, crtc->pipe);
 
 	/* No really, not for ILK+ */
 	BUG_ON(dev_priv->info->gen >= 5);
 
 	/* PLL is protected by panel, make sure we can write it */
-	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
-		assert_panel_unlocked(dev_priv, pipe);
+	if (IS_MOBILE(dev) && !IS_I830(dev))
+		assert_panel_unlocked(dev_priv, crtc->pipe);
 
-	reg = DPLL(pipe);
-	val = I915_READ(reg);
-	val |= DPLL_VCO_ENABLE;
+	I915_WRITE(reg, dpll);
+
+	/* Wait for the clocks to stabilize. */
+	POSTING_READ(reg);
+	udelay(150);
+
+	if (INTEL_INFO(dev)->gen >= 4) {
+		I915_WRITE(DPLL_MD(crtc->pipe),
+			   crtc->config.dpll_hw_state.dpll_md);
+	} else {
+		/* The pixel multiplier can only be updated once the
+		 * DPLL is enabled and the clocks are stable.
+		 *
+		 * So write it again.
+		 */
+		I915_WRITE(reg, dpll);
+	}
 
 	/* We do this three times for luck */
-	I915_WRITE(reg, val);
+	I915_WRITE(reg, dpll);
 	POSTING_READ(reg);
 	udelay(150); /* wait for warmup */
-	I915_WRITE(reg, val);
+	I915_WRITE(reg, dpll);
 	POSTING_READ(reg);
 	udelay(150); /* wait for warmup */
-	I915_WRITE(reg, val);
+	I915_WRITE(reg, dpll);
 	POSTING_READ(reg);
 	udelay(150); /* wait for warmup */
 }
@@ -3625,7 +3641,11 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
 	intel_crtc->active = true;
 	intel_update_watermarks(dev);
 
-	i9xx_enable_pll(dev_priv, pipe);
+	for_each_encoder_on_crtc(dev, crtc, encoder)
+		if (encoder->pre_pll_enable)
+			encoder->pre_pll_enable(encoder);
+
+	i9xx_enable_pll(intel_crtc);
 
 	for_each_encoder_on_crtc(dev, crtc, encoder)
 		if (encoder->pre_enable)
@@ -4466,8 +4486,6 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
 {
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_encoder *encoder;
-	int pipe = crtc->pipe;
 	u32 dpll;
 	bool is_sdvo;
 	struct dpll *clock = &crtc->config.dpll;
@@ -4531,37 +4549,14 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
 	dpll |= DPLL_VCO_ENABLE;
 	crtc->config.dpll_hw_state.dpll = dpll;
 
-	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
-	POSTING_READ(DPLL(pipe));
-	udelay(150);
-
-	for_each_encoder_on_crtc(dev, &crtc->base, encoder)
-		if (encoder->pre_pll_enable)
-			encoder->pre_pll_enable(encoder);
-
-	if (crtc->config.has_dp_encoder)
-		intel_dp_set_m_n(crtc);
-
-	I915_WRITE(DPLL(pipe), dpll);
-
-	/* Wait for the clocks to stabilize. */
-	POSTING_READ(DPLL(pipe));
-	udelay(150);
-
 	if (INTEL_INFO(dev)->gen >= 4) {
 		u32 dpll_md = (crtc->config.pixel_multiplier - 1)
 			<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
 		crtc->config.dpll_hw_state.dpll_md = dpll_md;
-
-		I915_WRITE(DPLL_MD(pipe), dpll_md);
-	} else {
-		/* The pixel multiplier can only be updated once the
-		 * DPLL is enabled and the clocks are stable.
-		 *
-		 * So write it again.
-		 */
-		I915_WRITE(DPLL(pipe), dpll);
 	}
+
+	if (crtc->config.has_dp_encoder)
+		intel_dp_set_m_n(crtc);
 }
 
 static void i8xx_update_pll(struct intel_crtc *crtc,
@@ -4570,8 +4565,6 @@ static void i8xx_update_pll(struct intel_crtc *crtc,
 {
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_encoder *encoder;
-	int pipe = crtc->pipe;
 	u32 dpll;
 	struct dpll *clock = &crtc->config.dpll;
 
@@ -4598,27 +4591,6 @@ static void i8xx_update_pll(struct intel_crtc *crtc,
 
 	dpll |= DPLL_VCO_ENABLE;
 	crtc->config.dpll_hw_state.dpll = dpll;
-
-	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
-	POSTING_READ(DPLL(pipe));
-	udelay(150);
-
-	for_each_encoder_on_crtc(dev, &crtc->base, encoder)
-		if (encoder->pre_pll_enable)
-			encoder->pre_pll_enable(encoder);
-
-	I915_WRITE(DPLL(pipe), dpll);
-
-	/* Wait for the clocks to stabilize. */
-	POSTING_READ(DPLL(pipe));
-	udelay(150);
-
-	/* The pixel multiplier can only be updated once the
-	 * DPLL is enabled and the clocks are stable.
-	 *
-	 * So write it again.
-	 */
-	I915_WRITE(DPLL(pipe), dpll);
 }
 
 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
-- 
1.7.11.7

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* [PATCH] drm/i915: asserts for lvds pre_enable
  2013-06-13 20:26   ` Imre Deak
  2013-06-13 20:46     ` Daniel Vetter
@ 2013-06-16 19:42     ` Daniel Vetter
  1 sibling, 0 replies; 84+ messages in thread
From: Daniel Vetter @ 2013-06-16 19:42 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Daniel Vetter

Lots of bangin my head against the wall^UExperiments have shown that
we really need to enable the lvds port before we enable plls. Strangely
that seems to include the fdi rx pll on the pch.

Note that the pch pll assert can fire since the lvds port has it's own
special clock source settings in the DPLL register, which means it
will never have a shared dpll (since there's only one LVDS port).

Anyway, encode this new evidence with a few nice WARNs.

v2: Incorporate review comments from Imre.
- Explain why lvds can't have a shared dpll.
- Update the WARN output.

Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 26 +++++++++++++-------------
 drivers/gpu/drm/i915/intel_drv.h     | 16 ++++++++++++++++
 drivers/gpu/drm/i915/intel_lvds.c    | 17 ++++++++++++-----
 3 files changed, 41 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 575fea8..7fdd957 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -874,8 +874,8 @@ static const char *state_string(bool enabled)
 }
 
 /* Only for pre-ILK configs */
-static void assert_pll(struct drm_i915_private *dev_priv,
-		       enum pipe pipe, bool state)
+void assert_pll(struct drm_i915_private *dev_priv,
+		enum pipe pipe, bool state)
 {
 	int reg;
 	u32 val;
@@ -888,10 +888,8 @@ static void assert_pll(struct drm_i915_private *dev_priv,
 	     "PLL state assertion failure (expected %s, current %s)\n",
 	     state_string(state), state_string(cur_state));
 }
-#define assert_pll_enabled(d, p) assert_pll(d, p, true)
-#define assert_pll_disabled(d, p) assert_pll(d, p, false)
 
-static struct intel_shared_dpll *
+struct intel_shared_dpll *
 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
@@ -903,9 +901,9 @@ intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 }
 
 /* For ILK+ */
-static void assert_shared_dpll(struct drm_i915_private *dev_priv,
-			       struct intel_shared_dpll *pll,
-			       bool state)
+void assert_shared_dpll(struct drm_i915_private *dev_priv,
+			struct intel_shared_dpll *pll,
+			bool state)
 {
 	bool cur_state;
 	struct intel_dpll_hw_state hw_state;
@@ -924,8 +922,6 @@ static void assert_shared_dpll(struct drm_i915_private *dev_priv,
 	     "%s assertion failure (expected %s, current %s)\n",
 	     pll->name, state_string(state), state_string(cur_state));
 }
-#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
-#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
 
 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 			  enum pipe pipe, bool state)
@@ -989,15 +985,19 @@ static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 	WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
 }
 
-static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
-				      enum pipe pipe)
+void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
+		       enum pipe pipe, bool state)
 {
 	int reg;
 	u32 val;
+	bool cur_state;
 
 	reg = FDI_RX_CTL(pipe);
 	val = I915_READ(reg);
-	WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
+	cur_state = !!(val & FDI_RX_PLL_ENABLE);
+	WARN(cur_state != state,
+	     "FDI RX PLL assertion failure (expected %s, current %s)\n",
+	     state_string(state), state_string(cur_state));
 }
 
 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index ffe9d35..623da3c 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -746,6 +746,22 @@ extern int intel_overlay_attrs(struct drm_device *dev, void *data,
 extern void intel_fb_output_poll_changed(struct drm_device *dev);
 extern void intel_fb_restore_mode(struct drm_device *dev);
 
+struct intel_shared_dpll *
+intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
+
+void assert_shared_dpll(struct drm_i915_private *dev_priv,
+			struct intel_shared_dpll *pll,
+			bool state);
+#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
+#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
+void assert_pll(struct drm_i915_private *dev_priv,
+		enum pipe pipe, bool state);
+#define assert_pll_enabled(d, p) assert_pll(d, p, true)
+#define assert_pll_disabled(d, p) assert_pll(d, p, false)
+void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
+		       enum pipe pipe, bool state);
+#define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
+#define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
 extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
 			bool state);
 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 2abb2d3..a510fa8 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -120,12 +120,20 @@ static void intel_pre_pll_enable_lvds(struct intel_encoder *encoder)
 	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 	struct drm_device *dev = encoder->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 	struct drm_display_mode *fixed_mode =
 		lvds_encoder->attached_connector->base.panel.fixed_mode;
-	int pipe = intel_crtc->pipe;
+	int pipe = crtc->pipe;
 	u32 temp;
 
+	if (HAS_PCH_SPLIT(dev)) {
+		assert_fdi_rx_pll_disabled(dev_priv, pipe);
+		assert_shared_dpll_disabled(dev_priv,
+					    intel_crtc_to_shared_dpll(crtc));
+	} else {
+		assert_pll_disabled(dev_priv, pipe);
+	}
+
 	temp = I915_READ(lvds_encoder->reg);
 	temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
 
@@ -142,7 +150,7 @@ static void intel_pre_pll_enable_lvds(struct intel_encoder *encoder)
 
 	/* set the corresponsding LVDS_BORDER bit */
 	temp &= ~LVDS_BORDER_ENABLE;
-	temp |= intel_crtc->config.gmch_pfit.lvds_border_bits;
+	temp |= crtc->config.gmch_pfit.lvds_border_bits;
 	/* Set the B0-B3 data pairs corresponding to whether we're going to
 	 * set the DPLLs for dual-channel mode or not.
 	 */
@@ -162,8 +170,7 @@ static void intel_pre_pll_enable_lvds(struct intel_encoder *encoder)
 	if (INTEL_INFO(dev)->gen == 4) {
 		/* Bspec wording suggests that LVDS port dithering only exists
 		 * for 18bpp panels. */
-		if (intel_crtc->config.dither &&
-		    intel_crtc->config.pipe_bpp == 18)
+		if (crtc->config.dither && crtc->config.pipe_bpp == 18)
 			temp |= LVDS_ENABLE_DITHER;
 		else
 			temp &= ~LVDS_ENABLE_DITHER;
-- 
1.7.11.7

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* Re: [PATCH 21/31] drm/i915: consolidate pch pll enable sequence
  2013-06-05 11:34 ` [PATCH 21/31] drm/i915: consolidate pch pll enable sequence Daniel Vetter
@ 2013-06-24 14:30   ` Damien Lespiau
  0 siblings, 0 replies; 84+ messages in thread
From: Damien Lespiau @ 2013-06-24 14:30 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: Intel Graphics Development

On Wed, Jun 05, 2013 at 01:34:23PM +0200, Daniel Vetter wrote:
> It's been splattered over 3 different places all doing random things.
> Now we have (mostly) the same sequence as i8xx/i9xx, but all called
> from the crtc_enable hook (through the pll->enable function):
> - write new dividers
> - enable vco and wait for stable clocks
> - write again for the pixel mutliplier
> 
> I've left the seemingly random 200 usec delay in there, just in case.
> 
> Also move the encoder->pre_pll_enable hook into the crtc_enable
> function, at the same spot we currently have a hack to enable the lvds
> port. Since that hack is now redundant, kill it.
> 
> While doing this patch I've learned the hard way that we can only fire
> up the LVDS port if both the pch dpll _and_ the fdi rc pll are not yet
> enabled. Otherwise things go haywire, at least on cpt.
> 
> v2: It is paramount to write the FPx divisors before we enable the
> the vco by writing to the DPLL registers, for otherwise the divisors
> won't get updated. This is in line with the i8xx/i9xx dpll.
> 
> v3: To keep the nice abstraction add a ->mode_set callback to set the
> divisors. Also streamline the enabling/disabling code a bit by
> removing some cargo-cult duplication and clearing registers where
> possible in the ->disable hook.
> 
> v4: Remove now unused local variable.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

For some reason my brain refuses to work on this patch. I say, let's
test it in the wild instead.

Acked-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

> ---
>  drivers/gpu/drm/i915/i915_drv.h      |  2 +
>  drivers/gpu/drm/i915/intel_display.c | 75 +++++++++++++-----------------------
>  2 files changed, 29 insertions(+), 48 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 4dc94ed..9fc1ea4 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -157,6 +157,8 @@ struct intel_shared_dpll {
>  	/* should match the index in the dev_priv->shared_dplls array */
>  	enum intel_dpll_id id;
>  	struct intel_dpll_hw_state hw_state;
> +	void (*mode_set)(struct drm_i915_private *dev_priv,
> +			 struct intel_shared_dpll *pll);
>  	void (*enable)(struct drm_i915_private *dev_priv,
>  		       struct intel_shared_dpll *pll);
>  	void (*disable)(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index fc1b5f7..334f86a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3064,13 +3064,7 @@ found:
>  		WARN_ON(pll->on);
>  		assert_shared_dpll_disabled(dev_priv, pll);
>  
> -		/* Wait for the clocks to stabilize before rewriting the regs */
> -		I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
> -		POSTING_READ(PCH_DPLL(pll->id));
> -		udelay(150);
> -
> -		I915_WRITE(PCH_FP0(pll->id), fp);
> -		I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
> +		pll->mode_set(dev_priv, pll);
>  	}
>  	pll->refcount++;
>  
> @@ -3120,7 +3114,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
>  	struct intel_encoder *encoder;
>  	int pipe = intel_crtc->pipe;
>  	int plane = intel_crtc->plane;
> -	u32 temp;
>  
>  	WARN_ON(!crtc->enabled);
>  
> @@ -3134,12 +3127,9 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
>  
>  	intel_update_watermarks(dev);
>  
> -	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
> -		temp = I915_READ(PCH_LVDS);
> -		if ((temp & LVDS_PORT_EN) == 0)
> -			I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
> -	}
> -
> +	for_each_encoder_on_crtc(dev, crtc, encoder)
> +		if (encoder->pre_pll_enable)
> +			encoder->pre_pll_enable(encoder);
>  
>  	if (intel_crtc->config.has_pch_encoder) {
>  		/* Note: FDI PLL enabling _must_ be done before we enable the
> @@ -5682,10 +5672,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
>  	if (intel_crtc->config.has_dp_encoder)
>  		intel_dp_set_m_n(intel_crtc);
>  
> -	for_each_encoder_on_crtc(dev, crtc, encoder)
> -		if (encoder->pre_pll_enable)
> -			encoder->pre_pll_enable(encoder);
> -
>  	if (is_lvds && has_reduced_clock && i915_powersave)
>  		intel_crtc->lowfreq_avail = true;
>  	else
> @@ -5694,23 +5680,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
>  	if (intel_crtc->config.has_pch_encoder) {
>  		pll = intel_crtc_to_shared_dpll(intel_crtc);
>  
> -		I915_WRITE(PCH_DPLL(pll->id), dpll);
> -
> -		/* Wait for the clocks to stabilize. */
> -		POSTING_READ(PCH_DPLL(pll->id));
> -		udelay(150);
> -
> -		/* The pixel multiplier can only be updated once the
> -		 * DPLL is enabled and the clocks are stable.
> -		 *
> -		 * So write it again.
> -		 */
> -		I915_WRITE(PCH_DPLL(pll->id), dpll);
> -
> -		if (has_reduced_clock)
> -			I915_WRITE(PCH_FP1(pll->id), fp2);
> -		else
> -			I915_WRITE(PCH_FP1(pll->id), fp);
>  	}
>  
>  	intel_set_pipe_timings(intel_crtc);
> @@ -8735,19 +8704,32 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
>  	return val & DPLL_VCO_ENABLE;
>  }
>  
> +static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
> +				  struct intel_shared_dpll *pll)
> +{
> +	I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
> +	I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
> +}
> +
>  static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
>  				struct intel_shared_dpll *pll)
>  {
> -	uint32_t reg, val;
> -
>  	/* PCH refclock must be enabled first */
>  	assert_pch_refclk_enabled(dev_priv);
>  
> -	reg = PCH_DPLL(pll->id);
> -	val = I915_READ(reg);
> -	val |= DPLL_VCO_ENABLE;
> -	I915_WRITE(reg, val);
> -	POSTING_READ(reg);
> +	I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
> +
> +	/* Wait for the clocks to stabilize. */
> +	POSTING_READ(PCH_DPLL(pll->id));
> +	udelay(150);
> +
> +	/* The pixel multiplier can only be updated once the
> +	 * DPLL is enabled and the clocks are stable.
> +	 *
> +	 * So write it again.
> +	 */
> +	I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
> +	POSTING_READ(PCH_DPLL(pll->id));
>  	udelay(200);
>  }
>  
> @@ -8756,7 +8738,6 @@ static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
>  {
>  	struct drm_device *dev = dev_priv->dev;
>  	struct intel_crtc *crtc;
> -	uint32_t reg, val;
>  
>  	/* Make sure no transcoder isn't still depending on us. */
>  	list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
> @@ -8764,11 +8745,8 @@ static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
>  			assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
>  	}
>  
> -	reg = PCH_DPLL(pll->id);
> -	val = I915_READ(reg);
> -	val &= ~DPLL_VCO_ENABLE;
> -	I915_WRITE(reg, val);
> -	POSTING_READ(reg);
> +	I915_WRITE(PCH_DPLL(pll->id), 0);
> +	POSTING_READ(PCH_DPLL(pll->id));
>  	udelay(200);
>  }
>  
> @@ -8787,6 +8765,7 @@ static void ibx_pch_dpll_init(struct drm_device *dev)
>  	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
>  		dev_priv->shared_dplls[i].id = i;
>  		dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
> +		dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
>  		dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
>  		dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
>  		dev_priv->shared_dplls[i].get_hw_state =
> -- 
> 1.7.11.7
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 84+ messages in thread

* Re: [PATCH 28/31] drm/i915: s/pre_pll/pre/ on the lvds port enable function
  2013-06-15  8:32   ` Imre Deak
@ 2013-06-26 10:02     ` Daniel Vetter
  0 siblings, 0 replies; 84+ messages in thread
From: Daniel Vetter @ 2013-06-26 10:02 UTC (permalink / raw)
  To: Imre Deak; +Cc: Daniel Vetter, Intel Graphics Development

On Sat, Jun 15, 2013 at 11:32:51AM +0300, Imre Deak wrote:
> On Wed, 2013-06-05 at 13:34 +0200, Daniel Vetter wrote:
> > i9xx doesn't use pre_enable at all, so we can fold this in now.
> > 
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> 
> I managed to review 23-28 for now, so on those apart from the two
> nitpicks:
> 
> Reviewed-by: Imre Deak <imre.deak@intel.com>

Merged up to patch 28, thanks for the review.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

^ permalink raw reply	[flat|nested] 84+ messages in thread

* Re: [PATCH] drm/i915: clean up vlv ->pre_pll_enable and pll enable sequence
  2013-06-06  8:22   ` [PATCH] " Daniel Vetter
@ 2013-07-11 14:11     ` Imre Deak
  2013-07-11 20:13       ` Daniel Vetter
  2013-07-12 16:27       ` Daniel Vetter
  0 siblings, 2 replies; 84+ messages in thread
From: Imre Deak @ 2013-07-11 14:11 UTC (permalink / raw)
  To: Daniel Vetter; +Cc: Jani Nikula, Intel Graphics Development


[-- Attachment #1.1: Type: text/plain, Size: 4201 bytes --]

On Thu, 2013-06-06 at 10:22 +0200, Daniel Vetter wrote:
> No need to call the ->pre_pll_enable hook twice if we don't enable the
> dpll too early. This should make Jani a bit less grumpy.
> 
> v2: Rebase on top of the newly-colored BUG_ONs.
> 
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 45 +++++++++++++++---------------------
>  1 file changed, 18 insertions(+), 27 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 5e43b9a..6e4d666 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1268,32 +1268,38 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
>  	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
>  }
>  
> -static void vlv_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
> +static void vlv_enable_pll(struct intel_crtc *crtc)
>  {
> -	int reg;
> -	u32 val;
> +	struct drm_device *dev = crtc->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	int reg = DPLL(crtc->pipe);
> +	u32 dpll = crtc->config.dpll_hw_state.dpll;
>  
> -	assert_pipe_disabled(dev_priv, pipe);
> +	assert_pipe_disabled(dev_priv, crtc->pipe);
>  
>  	/* No really, not for ILK+ */
>  	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
>  
>  	/* PLL is protected by panel, make sure we can write it */
>  	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
> -		assert_panel_unlocked(dev_priv, pipe);
> +		assert_panel_unlocked(dev_priv, crtc->pipe);
> +
> +	I915_WRITE(reg, dpll);
> +	POSTING_READ(reg);
> +	udelay(150);
> +
> +	if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
> +		DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
>  
> -	reg = DPLL(pipe);
> -	val = I915_READ(reg);
> -	val |= DPLL_VCO_ENABLE;
>  
>  	/* We do this three times for luck */
> -	I915_WRITE(reg, val);
> +	I915_WRITE(reg, dpll);
>  	POSTING_READ(reg);
>  	udelay(150); /* wait for warmup */
> -	I915_WRITE(reg, val);
> +	I915_WRITE(reg, dpll);
>  	POSTING_READ(reg);
>  	udelay(150); /* wait for warmup */
> -	I915_WRITE(reg, val);
> +	I915_WRITE(reg, dpll);
>  	POSTING_READ(reg);
>  	udelay(150); /* wait for warmup */
>  }
> @@ -3561,7 +3567,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
>  		if (encoder->pre_pll_enable)
>  			encoder->pre_pll_enable(encoder);
>  
> -	vlv_enable_pll(dev_priv, pipe);
> +	vlv_enable_pll(intel_crtc);
>  
>  	for_each_encoder_on_crtc(dev, crtc, encoder)
>  		if (encoder->pre_enable)
> @@ -4315,7 +4321,6 @@ static void vlv_update_pll(struct intel_crtc *crtc)
>  {
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_encoder *encoder;
>  	int pipe = crtc->pipe;
>  	u32 dpll, mdiv;
>  	u32 bestn, bestm1, bestm2, bestp1, bestp2;
> @@ -4403,10 +4408,6 @@ static void vlv_update_pll(struct intel_crtc *crtc)
>  
>  	vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
>  
> -	for_each_encoder_on_crtc(dev, &crtc->base, encoder)
> -		if (encoder->pre_pll_enable)
> -			encoder->pre_pll_enable(encoder);
> -
>  	/* Enable DPIO clock input */
>  	dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
>  		DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
> @@ -4416,20 +4417,10 @@ static void vlv_update_pll(struct intel_crtc *crtc)
>  	dpll |= DPLL_VCO_ENABLE;
>  	crtc->config.dpll_hw_state.dpll = dpll;
>  
> -	I915_WRITE(DPLL(pipe), dpll);
> -	POSTING_READ(DPLL(pipe));
> -	udelay(150);
> -
> -	if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
> -		DRM_ERROR("DPLL %d failed to lock\n", pipe);
> -
>  	dpll_md = (crtc->config.pixel_multiplier - 1)
>  		<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
>  	crtc->config.dpll_hw_state.dpll_md = dpll_md;
>  
> -	I915_WRITE(DPLL_MD(pipe), dpll_md);
> -	POSTING_READ(DPLL_MD(pipe));

This piece was not added to vlv_enable_pll. Other than this patches
29-31 look ok, so on those:

Reviewed-by: Imre Deak <imre.deak@intel.com>


[-- Attachment #1.2: This is a digitally signed message part --]
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[-- Attachment #2: Type: text/plain, Size: 159 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 84+ messages in thread

* [PATCH] drm/i915: clean up vlv ->pre_pll_enable and pll enable sequence
  2013-07-11 14:11     ` Imre Deak
@ 2013-07-11 20:13       ` Daniel Vetter
  2013-07-12 16:27       ` Daniel Vetter
  1 sibling, 0 replies; 84+ messages in thread
From: Daniel Vetter @ 2013-07-11 20:13 UTC (permalink / raw)
  To: Intel Graphics Development; +Cc: Jani Nikula, Daniel Vetter

No need to call the ->pre_pll_enable hook twice if we don't enable the
dpll too early. This should make Jani a bit less grumpy.

v2: Rebase on top of the newly-colored BUG_ONs.

v3: Reinstate the lost write of the DPLL_MD register, spotted by Imre.

Cc: Imre Deak <imre.deak@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 47 +++++++++++++++---------------------
 1 file changed, 20 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4c647e0..923c913 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1300,32 +1300,40 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
 	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
 }
 
-static void vlv_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
+static void vlv_enable_pll(struct intel_crtc *crtc)
 {
-	int reg;
-	u32 val;
+	struct drm_device *dev = crtc->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int reg = DPLL(crtc->pipe);
+	u32 dpll = crtc->config.dpll_hw_state.dpll;
 
-	assert_pipe_disabled(dev_priv, pipe);
+	assert_pipe_disabled(dev_priv, crtc->pipe);
 
 	/* No really, not for ILK+ */
 	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
 
 	/* PLL is protected by panel, make sure we can write it */
 	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
-		assert_panel_unlocked(dev_priv, pipe);
+		assert_panel_unlocked(dev_priv, crtc->pipe);
 
-	reg = DPLL(pipe);
-	val = I915_READ(reg);
-	val |= DPLL_VCO_ENABLE;
+	I915_WRITE(reg, dpll);
+	POSTING_READ(reg);
+	udelay(150);
+
+	if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
+		DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
+
+	I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
+	POSTING_READ(DPLL_MD(crtc->pipe));
 
 	/* We do this three times for luck */
-	I915_WRITE(reg, val);
+	I915_WRITE(reg, dpll);
 	POSTING_READ(reg);
 	udelay(150); /* wait for warmup */
-	I915_WRITE(reg, val);
+	I915_WRITE(reg, dpll);
 	POSTING_READ(reg);
 	udelay(150); /* wait for warmup */
-	I915_WRITE(reg, val);
+	I915_WRITE(reg, dpll);
 	POSTING_READ(reg);
 	udelay(150); /* wait for warmup */
 }
@@ -3633,7 +3641,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
 		if (encoder->pre_pll_enable)
 			encoder->pre_pll_enable(encoder);
 
-	vlv_enable_pll(dev_priv, pipe);
+	vlv_enable_pll(intel_crtc);
 
 	for_each_encoder_on_crtc(dev, crtc, encoder)
 		if (encoder->pre_enable)
@@ -4388,7 +4396,6 @@ static void vlv_update_pll(struct intel_crtc *crtc)
 {
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_encoder *encoder;
 	int pipe = crtc->pipe;
 	u32 dpll, mdiv;
 	u32 bestn, bestm1, bestm2, bestp1, bestp2;
@@ -4477,10 +4484,6 @@ static void vlv_update_pll(struct intel_crtc *crtc)
 
 	vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
 
-	for_each_encoder_on_crtc(dev, &crtc->base, encoder)
-		if (encoder->pre_pll_enable)
-			encoder->pre_pll_enable(encoder);
-
 	/* Enable DPIO clock input */
 	dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
 		DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
@@ -4490,20 +4493,10 @@ static void vlv_update_pll(struct intel_crtc *crtc)
 	dpll |= DPLL_VCO_ENABLE;
 	crtc->config.dpll_hw_state.dpll = dpll;
 
-	I915_WRITE(DPLL(pipe), dpll);
-	POSTING_READ(DPLL(pipe));
-	udelay(150);
-
-	if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
-		DRM_ERROR("DPLL %d failed to lock\n", pipe);
-
 	dpll_md = (crtc->config.pixel_multiplier - 1)
 		<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
 	crtc->config.dpll_hw_state.dpll_md = dpll_md;
 
-	I915_WRITE(DPLL_MD(pipe), dpll_md);
-	POSTING_READ(DPLL_MD(pipe));
-
 	if (crtc->config.has_dp_encoder)
 		intel_dp_set_m_n(crtc);
 
-- 
1.8.3.1

^ permalink raw reply related	[flat|nested] 84+ messages in thread

* Re: [PATCH] drm/i915: clean up vlv ->pre_pll_enable and pll enable sequence
  2013-07-11 14:11     ` Imre Deak
  2013-07-11 20:13       ` Daniel Vetter
@ 2013-07-12 16:27       ` Daniel Vetter
  1 sibling, 0 replies; 84+ messages in thread
From: Daniel Vetter @ 2013-07-12 16:27 UTC (permalink / raw)
  To: Imre Deak; +Cc: Jani Nikula, Daniel Vetter, Intel Graphics Development

On Thu, Jul 11, 2013 at 05:11:41PM +0300, Imre Deak wrote:
> This piece was not added to vlv_enable_pll. Other than this patches
> 29-31 look ok, so on those:
> 
> Reviewed-by: Imre Deak <imre.deak@intel.com>

Ok, I've pushed the updated patch plus the other two, thanks for the
review.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

^ permalink raw reply	[flat|nested] 84+ messages in thread

end of thread, other threads:[~2013-07-12 16:27 UTC | newest]

Thread overview: 84+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-06-05 11:34 [PATCH 00/31] shared pch display pll rework Daniel Vetter
2013-06-05 11:34 ` [PATCH 01/31] drm/i915: fix up pch pll handling in ->mode_set Daniel Vetter
2013-06-05 11:34 ` [PATCH 02/31] drm/i915: conditionally disable pch resources in ilk_crtc_disable Daniel Vetter
2013-06-05 11:34 ` [PATCH 03/31] drm/i915: lock down pch pll accouting some more Daniel Vetter
2013-06-07 16:32   ` Ville Syrjälä
2013-06-07 20:03     ` Daniel Vetter
2013-06-07 20:46       ` Ville Syrjälä
2013-06-07 21:13         ` Daniel Vetter
2013-06-10 10:11           ` Ville Syrjälä
2013-06-10 14:34             ` Daniel Vetter
2013-06-10 14:47               ` Ville Syrjälä
2013-06-10 15:28                 ` [PATCH] " Daniel Vetter
2013-06-07 21:09     ` Daniel Vetter
2013-06-05 11:34 ` [PATCH 04/31] drm/i915: s/pch_pll/shared_dpll/ Daniel Vetter
2013-06-05 11:34 ` [PATCH 05/31] drm/i915: switch crtc->shared_dpll from a pointer to an enum Daniel Vetter
2013-06-07 16:48   ` Ville Syrjälä
2013-06-07 21:10     ` [PATCH] " Daniel Vetter
2013-06-05 11:34 ` [PATCH 06/31] drm/i915: move shared_dpll into the pipe config Daniel Vetter
2013-06-07 17:03   ` Ville Syrjälä
2013-06-07 21:10     ` [PATCH] " Daniel Vetter
2013-06-05 11:34 ` [PATCH 07/31] drm/i915: refactor PCH_DPLL_SEL #defines Daniel Vetter
2013-06-05 11:34 ` [PATCH 08/31] drm/i915: hw state readout for shared pch plls Daniel Vetter
2013-06-07 17:23   ` Ville Syrjälä
2013-06-07 20:11     ` Daniel Vetter
2013-06-07 21:11     ` [PATCH] " Daniel Vetter
2013-06-05 11:34 ` [PATCH 09/31] drm/i915: consolidate ->num_shared_dplls assignement Daniel Vetter
2013-06-05 11:34 ` [PATCH 10/31] drm/i915: metadata for shared dplls Daniel Vetter
2013-06-05 11:34 ` [PATCH 11/31] drm/i915: scrap register address storage Daniel Vetter
2013-06-05 11:34 ` [PATCH 12/31] drm/i915: enable/disable hooks for shared dplls Daniel Vetter
2013-06-05 11:34 ` [PATCH 13/31] drm/i915: drop crtc checking from assert_shared_dpll Daniel Vetter
2013-06-05 11:34 ` [PATCH 14/31] drm/i915: display pll hw state readout and checking Daniel Vetter
2013-06-12 13:31   ` Damien Lespiau
2013-06-12 13:39     ` Ville Syrjälä
2013-06-12 13:49       ` Damien Lespiau
2013-06-05 11:34 ` [PATCH 15/31] drm/i915: extract readout_hw_state from setup_hw_state Daniel Vetter
2013-06-12 13:32   ` Damien Lespiau
2013-06-12 14:26   ` Daniel Vetter
2013-06-05 11:34 ` [PATCH 16/31] drm/i915: split up intel_modeset_check_state Daniel Vetter
2013-06-12 13:33   ` Damien Lespiau
2013-06-05 11:34 ` [PATCH 17/31] drm/i915: WARN on lack of shared dpll Daniel Vetter
2013-06-12 13:38   ` Damien Lespiau
2013-06-05 11:34 ` [PATCH 18/31] drm/i915: hw state readout and cross-checking for shared dplls Daniel Vetter
2013-06-12 15:04   ` Damien Lespiau
2013-06-05 11:34 ` [PATCH 19/31] drm/i915: fix up pch pll enabling for pixel multipliers Daniel Vetter
2013-06-12 15:12   ` Damien Lespiau
2013-06-12 19:34     ` Daniel Vetter
2013-06-05 11:34 ` [PATCH 20/31] drm/i915: simplify the reduced clock handling for pch plls Daniel Vetter
2013-06-13 11:26   ` Damien Lespiau
2013-06-13 11:35     ` Daniel Vetter
2013-06-13 12:32       ` Damien Lespiau
2013-06-13 14:33         ` Daniel Vetter
2013-06-05 11:34 ` [PATCH 21/31] drm/i915: consolidate pch pll enable sequence Daniel Vetter
2013-06-24 14:30   ` Damien Lespiau
2013-06-05 11:34 ` [PATCH 22/31] drm/i915: use sw tracked state to select shared dplls Daniel Vetter
2013-06-12 15:20   ` Damien Lespiau
2013-06-05 11:34 ` [PATCH 23/31] drm/i915: duplicate intel_enable_pll into i9xx and vlv versions Daniel Vetter
2013-06-05 15:12   ` Jani Nikula
2013-06-05 22:52     ` [PATCH] " Daniel Vetter
2013-06-05 11:34 ` [PATCH 24/31] drm/i915: asserts for lvds pre_enable Daniel Vetter
2013-06-13 20:26   ` Imre Deak
2013-06-13 20:46     ` Daniel Vetter
2013-06-14 10:45       ` Imre Deak
2013-06-16 19:42     ` [PATCH] " Daniel Vetter
2013-06-05 11:34 ` [PATCH 25/31] drm/i915: move encoder pre enable hooks togther on ilk+ Daniel Vetter
2013-06-05 11:34 ` [PATCH 26/31] drm/i915: hw state readout for i9xx dplls Daniel Vetter
2013-06-05 11:34 ` [PATCH 27/31] drm/i915: move i9xx dpll enabling into crtc enable function Daniel Vetter
2013-06-05 15:13   ` Jani Nikula
2013-06-06  8:20     ` [PATCH] " Daniel Vetter
2013-06-14 16:02   ` [PATCH 27/31] " Imre Deak
2013-06-16 19:15     ` Daniel Vetter
2013-06-16 19:24     ` [PATCH] " Daniel Vetter
2013-06-05 11:34 ` [PATCH 28/31] drm/i915: s/pre_pll/pre/ on the lvds port " Daniel Vetter
2013-06-15  8:32   ` Imre Deak
2013-06-26 10:02     ` Daniel Vetter
2013-06-05 11:34 ` [PATCH 29/31] drm/i915: clean up vlv ->pre_pll_enable and pll enable sequence Daniel Vetter
2013-06-06  8:22   ` [PATCH] " Daniel Vetter
2013-07-11 14:11     ` Imre Deak
2013-07-11 20:13       ` Daniel Vetter
2013-07-12 16:27       ` Daniel Vetter
2013-06-05 11:34 ` [PATCH 30/31] drm/i915: Fix up cpt pixel multiplier " Daniel Vetter
2013-06-05 11:34 ` [PATCH 31/31] drm/i915: clear DPLL reg when disabling i9xx dplls Daniel Vetter
2013-06-07 17:46 ` [PATCH 00/31] shared pch display pll rework Ville Syrjälä
2013-06-10 15:57   ` Ville Syrjälä
2013-06-10 18:16     ` Daniel Vetter

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