From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: [PATCH 20/31] drm/i915: simplify the reduced clock handling for pch plls Date: Wed, 5 Jun 2013 13:34:22 +0200 Message-ID: <1370432073-27634-21-git-send-email-daniel.vetter@ffwll.ch> References: <1370432073-27634-1-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ea0-f180.google.com (mail-ea0-f180.google.com [209.85.215.180]) by gabe.freedesktop.org (Postfix) with ESMTP id AF673E64B9 for ; Wed, 5 Jun 2013 04:35:19 -0700 (PDT) Received: by mail-ea0-f180.google.com with SMTP id k10so1071250eaj.39 for ; Wed, 05 Jun 2013 04:35:19 -0700 (PDT) In-Reply-To: <1370432073-27634-1-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Intel Graphics Development Cc: Daniel Vetter List-Id: intel-gfx@lists.freedesktop.org Just move the lowfreq_avail logic out of the register writing as a prep step for the next patch, which will coalesce all the pch pll enabling into one spot. Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index ecf0b1e..fc1b5f7 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5686,7 +5686,10 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, if (encoder->pre_pll_enable) encoder->pre_pll_enable(encoder); - intel_crtc->lowfreq_avail = false; + if (is_lvds && has_reduced_clock && i915_powersave) + intel_crtc->lowfreq_avail = true; + else + intel_crtc->lowfreq_avail = false; if (intel_crtc->config.has_pch_encoder) { pll = intel_crtc_to_shared_dpll(intel_crtc); @@ -5704,12 +5707,10 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, */ I915_WRITE(PCH_DPLL(pll->id), dpll); - if (is_lvds && has_reduced_clock && i915_powersave) { + if (has_reduced_clock) I915_WRITE(PCH_FP1(pll->id), fp2); - intel_crtc->lowfreq_avail = true; - } else { + else I915_WRITE(PCH_FP1(pll->id), fp); - } } intel_set_pipe_timings(intel_crtc); -- 1.7.11.7