From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42492) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UoFLO-0007Bz-HZ for qemu-devel@nongnu.org; Sun, 16 Jun 2013 11:58:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UoFLM-00076F-E3 for qemu-devel@nongnu.org; Sun, 16 Jun 2013 11:58:18 -0400 Received: from cantor2.suse.de ([195.135.220.15]:60005 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UoFLL-00075r-Ls for qemu-devel@nongnu.org; Sun, 16 Jun 2013 11:58:16 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sun, 16 Jun 2013 17:57:38 +0200 Message-Id: <1371398269-6213-19-git-send-email-afaerber@suse.de> In-Reply-To: <1371398269-6213-1-git-send-email-afaerber@suse.de> References: <1371398269-6213-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH qom-cpu v2 18/29] cpu: Turn cpu_unassigned_access() into a CPUState hook List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Blue Swirl , "Edgar E. Iglesias" , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Aurelien Jarno , Richard Henderson Use it for all targets, but be careful not to pass invalid CPUState. cpu_single_env can be NULL, e.g. on Xen. Signed-off-by: Andreas F=C3=A4rber --- cputlb.c | 15 +++++++++------ hw/alpha/typhoon.c | 14 ++++++++++---- include/qom/cpu.h | 33 +++++++++++++++++++++++++++++++++ memory.c | 14 ++++++++------ target-alpha/cpu.c | 1 + target-alpha/cpu.h | 6 +++--- target-alpha/mem_helper.c | 10 +++++++--- target-microblaze/cpu.c | 2 +- target-microblaze/cpu.h | 5 +++-- target-microblaze/op_helper.c | 17 +++++++++++++---- target-mips/cpu.c | 1 + target-mips/cpu.h | 5 +++-- target-mips/op_helper.c | 13 +++++++++---- target-sparc/cpu.c | 1 + target-sparc/cpu.h | 5 +++-- target-sparc/ldst_helper.c | 27 +++++++++++++++++++-------- 16 files changed, 124 insertions(+), 45 deletions(-) diff --git a/cputlb.c b/cputlb.c index 1230e9e..232c488 100644 --- a/cputlb.c +++ b/cputlb.c @@ -331,12 +331,15 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env= 1, target_ulong addr) pd =3D env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK; mr =3D iotlb_to_region(pd); if (memory_region_is_unassigned(mr)) { -#if defined(TARGET_ALPHA) || defined(TARGET_MIPS) || defined(TARGET_SPAR= C) - cpu_unassigned_access(env1, addr, 0, 1, 0, 4); -#else - cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x= " - TARGET_FMT_lx "\n", addr); -#endif + CPUState *cpu =3D ENV_GET_CPU(env1); + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + if (cc->do_unassigned_access) { + cc->do_unassigned_access(cpu, addr, false, true, 0, 4); + } else { + cpu_abort(env1, "Trying to execute code outside RAM or ROM a= t 0x" + TARGET_FMT_lx "\n", addr); + } } p =3D (void *)((uintptr_t)addr + env1->tlb_table[mmu_idx][page_index= ].addend); return qemu_ram_addr_from_host_nofail(p); diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c index 1ead187..207dcad 100644 --- a/hw/alpha/typhoon.c +++ b/hw/alpha/typhoon.c @@ -197,7 +197,8 @@ static uint64_t cchip_read(void *opaque, hwaddr addr,= unsigned size) break; =20 default: - cpu_unassigned_access(cpu_single_env, addr, 0, 0, 0, size); + cpu =3D CPU(alpha_env_get_cpu(cpu_single_env)); + cpu_unassigned_access(cpu, addr, false, false, 0, size); return -1; } =20 @@ -214,6 +215,7 @@ static uint64_t dchip_read(void *opaque, hwaddr addr,= unsigned size) static uint64_t pchip_read(void *opaque, hwaddr addr, unsigned size) { TyphoonState *s =3D opaque; + CPUState *cs; uint64_t ret =3D 0; =20 if (addr & 4) { @@ -300,7 +302,8 @@ static uint64_t pchip_read(void *opaque, hwaddr addr,= unsigned size) break; =20 default: - cpu_unassigned_access(cpu_single_env, addr, 0, 0, 0, size); + cs =3D CPU(alpha_env_get_cpu(cpu_single_env)); + cpu_unassigned_access(cs, addr, false, false, 0, size); return -1; } =20 @@ -312,6 +315,7 @@ static void cchip_write(void *opaque, hwaddr addr, uint64_t v32, unsigned size) { TyphoonState *s =3D opaque; + CPUState *cpu_single_cpu =3D CPU(alpha_env_get_cpu(cpu_single_env)); uint64_t val, oldval, newval; =20 if (addr & 4) { @@ -461,7 +465,7 @@ static void cchip_write(void *opaque, hwaddr addr, break; =20 default: - cpu_unassigned_access(cpu_single_env, addr, 1, 0, 0, size); + cpu_unassigned_access(cpu_single_cpu, addr, true, false, 0, size= ); return; } } @@ -476,6 +480,7 @@ static void pchip_write(void *opaque, hwaddr addr, uint64_t v32, unsigned size) { TyphoonState *s =3D opaque; + CPUState *cs; uint64_t val, oldval; =20 if (addr & 4) { @@ -577,7 +582,8 @@ static void pchip_write(void *opaque, hwaddr addr, break; =20 default: - cpu_unassigned_access(cpu_single_env, addr, 1, 0, 0, size); + cs =3D CPU(alpha_env_get_cpu(cpu_single_env)); + cpu_unassigned_access(cs, addr, true, false, 0, size); return; } } diff --git a/include/qom/cpu.h b/include/qom/cpu.h index be2a0bd..7afc442 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -22,6 +22,7 @@ =20 #include #include "hw/qdev-core.h" +#include "exec/hwaddr.h" #include "qemu/thread.h" #include "qemu/typedefs.h" =20 @@ -42,12 +43,17 @@ typedef int (*WriteCoreDumpFunction)(void *buf, size_= t size, void *opaque); =20 typedef struct CPUState CPUState; =20 +typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr, + bool is_write, bool is_exec, int opa= que, + unsigned size); + /** * CPUClass: * @class_by_name: Callback to map -cpu command line model name to an * instantiatable CPU type. * @reset: Callback to reset the #CPUState to its initial state. * @do_interrupt: Callback for interrupt handling. + * @do_unassigned_access: Callback for unassigned access handling. * @dump_state: Callback for dumping state. * @dump_statistics: Callback for dumping statistics. * @get_arch_id: Callback for getting architecture-dependent CPU ID. @@ -66,6 +72,7 @@ typedef struct CPUClass { =20 void (*reset)(CPUState *cpu); void (*do_interrupt)(CPUState *cpu); + CPUUnassignedAccess do_unassigned_access; void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fpri= ntf, int flags); void (*dump_statistics)(CPUState *cpu, FILE *f, @@ -280,6 +287,17 @@ static inline void cpu_class_set_vmsd(CPUClass *cc, #define cpu_class_set_vmsd(cc, value) ((cc)->vmsd =3D NULL) #endif =20 +#ifndef CONFIG_USER_ONLY +static inline void cpu_class_set_do_unassigned_access(CPUClass *cc, + CPUUnassignedAcces= s value) +{ + cc->do_unassigned_access =3D value; +} +#else +#define cpu_class_set_do_unassigned_access(cc, value) \ + ((cc)->do_unassigned_access =3D NULL) +#endif + /** * qemu_cpu_has_work: * @cpu: The vCPU to check. @@ -382,6 +400,21 @@ void cpu_interrupt(CPUState *cpu, int mask); =20 #endif /* USER_ONLY */ =20 +#ifndef CONFIG_USER_ONLY + +static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr, + bool is_write, bool is_exec, + int opaque, unsigned size) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + if (cc->do_unassigned_access) { + cc->do_unassigned_access(cpu, addr, is_write, is_exec, opaque, s= ize); + } +} + +#endif + /** * cpu_reset_interrupt: * @cpu: The CPU to clear the interrupt on. diff --git a/memory.c b/memory.c index 5cb8f4a..3bc98ad 100644 --- a/memory.c +++ b/memory.c @@ -857,9 +857,10 @@ static uint64_t unassigned_mem_read(void *opaque, hw= addr addr, #ifdef DEBUG_UNASSIGNED printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); #endif -#if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MIC= ROBLAZE) - cpu_unassigned_access(cpu_single_env, addr, 0, 0, 0, size); -#endif + if (cpu_single_env !=3D NULL) { + cpu_unassigned_access(ENV_GET_CPU(cpu_single_env), + addr, false, false, 0, size); + } return 0; } =20 @@ -869,9 +870,10 @@ static void unassigned_mem_write(void *opaque, hwadd= r addr, #ifdef DEBUG_UNASSIGNED printf("Unassigned mem write " TARGET_FMT_plx " =3D 0x%"PRIx64"\n", = addr, val); #endif -#if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MIC= ROBLAZE) - cpu_unassigned_access(cpu_single_env, addr, 1, 0, 0, size); -#endif + if (cpu_single_env !=3D NULL) { + cpu_unassigned_access(ENV_GET_CPU(cpu_single_env), + addr, true, false, 0, size); + } } =20 static bool unassigned_mem_accepts(void *opaque, hwaddr addr, diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c index 7d5d6f9..71da1af 100644 --- a/target-alpha/cpu.c +++ b/target-alpha/cpu.c @@ -262,6 +262,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, voi= d *data) cc->class_by_name =3D alpha_cpu_class_by_name; cc->do_interrupt =3D alpha_cpu_do_interrupt; cc->dump_state =3D alpha_cpu_dump_state; + cpu_class_set_do_unassigned_access(cc, alpha_cpu_unassigned_access); } =20 static const TypeInfo alpha_cpu_type_info =3D { diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h index 2156a1e..01f4ebb 100644 --- a/target-alpha/cpu.h +++ b/target-alpha/cpu.h @@ -457,9 +457,9 @@ uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env); void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val); #ifndef CONFIG_USER_ONLY void swap_shadow_regs(CPUAlphaState *env); -QEMU_NORETURN void cpu_unassigned_access(CPUAlphaState *env1, - hwaddr addr, int is_write, - int is_exec, int unused, int si= ze); +QEMU_NORETURN void alpha_cpu_unassigned_access(CPUState *cpu, hwaddr add= r, + bool is_write, bool is_ex= ec, + int unused, unsigned size= ); #endif =20 /* Bits in TB->FLAGS that control how translation is processed. */ diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c index 3d2cd61..7160a1c 100644 --- a/target-alpha/mem_helper.c +++ b/target-alpha/mem_helper.c @@ -109,11 +109,15 @@ static void do_unaligned_access(CPUAlphaState *env,= target_ulong addr, cpu_loop_exit(env); } =20 -void cpu_unassigned_access(CPUAlphaState *env, hwaddr addr, - int is_write, int is_exec, int unused, int si= ze) +void alpha_cpu_unassigned_access(CPUState *cs, hwaddr addr, + bool is_write, bool is_exec, int unused= , + unsigned size) { + AlphaCPU *cpu =3D ALPHA_CPU(cs); + CPUAlphaState *env =3D &cpu->env; + env->trap_arg0 =3D addr; - env->trap_arg1 =3D is_write; + env->trap_arg1 =3D is_write ? 1 : 0; dynamic_excp(env, 0, EXCP_MCHK, 0); } =20 diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c index b9a097c..a0fcdf4 100644 --- a/target-microblaze/cpu.c +++ b/target-microblaze/cpu.c @@ -138,8 +138,8 @@ static void mb_cpu_class_init(ObjectClass *oc, void *= data) =20 cc->do_interrupt =3D mb_cpu_do_interrupt; cc->dump_state =3D mb_cpu_dump_state; + cpu_class_set_do_unassigned_access(cc, mb_cpu_unassigned_access); dc->vmsd =3D &vmstate_mb_cpu; - dc->props =3D mb_properties; } =20 diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h index 1813939..75ae5ba 100644 --- a/target-microblaze/cpu.h +++ b/target-microblaze/cpu.h @@ -367,8 +367,9 @@ static inline void cpu_get_tb_cpu_state(CPUMBState *e= nv, target_ulong *pc, } =20 #if !defined(CONFIG_USER_ONLY) -void cpu_unassigned_access(CPUMBState *env1, hwaddr addr, - int is_write, int is_exec, int is_asi, int si= ze); +void mb_cpu_unassigned_access(CPUState *cpu, hwaddr addr, + bool is_write, bool is_exec, int is_asi, + unsigned size); #endif =20 static inline bool cpu_has_work(CPUState *cpu) diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.= c index f2cb88b..14baa84 100644 --- a/target-microblaze/op_helper.c +++ b/target-microblaze/op_helper.c @@ -495,12 +495,21 @@ void helper_mmu_write(CPUMBState *env, uint32_t rn,= uint32_t v) mmu_write(env, rn, v); } =20 -void cpu_unassigned_access(CPUMBState *env, hwaddr addr, - int is_write, int is_exec, int is_asi, int si= ze) +void mb_cpu_unassigned_access(CPUState *cs, hwaddr addr, + bool is_write, bool is_exec, int is_asi, + unsigned size) { + MicroBlazeCPU *cpu; + CPUMBState *env; + qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=3D%d ex= e=3D%d\n", - addr, is_write, is_exec); - if (!env || !(env->sregs[SR_MSR] & MSR_EE)) { + addr, is_write ? 1 : 0, is_exec ? 1 : 0); + if (cs =3D=3D NULL) { + return; + } + cpu =3D MICROBLAZE_CPU(cs); + env =3D &cpu->env; + if (!(env->sregs[SR_MSR] & MSR_EE)) { return; } =20 diff --git a/target-mips/cpu.c b/target-mips/cpu.c index 0fdc316..b61e207 100644 --- a/target-mips/cpu.c +++ b/target-mips/cpu.c @@ -80,6 +80,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) =20 cc->do_interrupt =3D mips_cpu_do_interrupt; cc->dump_state =3D mips_cpu_dump_state; + cpu_class_set_do_unassigned_access(cc, mips_cpu_unassigned_access); } =20 static const TypeInfo mips_cpu_type_info =3D { diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 6e761e0..fa0f0d1 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -493,8 +493,9 @@ void r4k_helper_tlbwr(CPUMIPSState *env); void r4k_helper_tlbp(CPUMIPSState *env); void r4k_helper_tlbr(CPUMIPSState *env); =20 -void cpu_unassigned_access(CPUMIPSState *env, hwaddr addr, - int is_write, int is_exec, int unused, int si= ze); +void mips_cpu_unassigned_access(CPUState *cpu, hwaddr addr, + bool is_write, bool is_exec, int unused, + unsigned size); #endif =20 void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf); diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 3fa0d00..f6838ec 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -2147,13 +2147,18 @@ void tlb_fill(CPUMIPSState *env, target_ulong add= r, int is_write, int mmu_idx, } } =20 -void cpu_unassigned_access(CPUMIPSState *env, hwaddr addr, - int is_write, int is_exec, int unused, int si= ze) +void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr, + bool is_write, bool is_exec, int unused, + unsigned size) { - if (is_exec) + MIPSCPU *cpu =3D MIPS_CPU(cs); + CPUMIPSState *env =3D &cpu->env; + + if (is_exec) { helper_raise_exception(env, EXCP_IBE); - else + } else { helper_raise_exception(env, EXCP_DBE); + } } #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c index ff1200c..65ae6f7 100644 --- a/target-sparc/cpu.c +++ b/target-sparc/cpu.c @@ -771,6 +771,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, voi= d *data) =20 cc->do_interrupt =3D sparc_cpu_do_interrupt; cc->dump_state =3D sparc_cpu_dump_state; + cpu_class_set_do_unassigned_access(cc, sparc_cpu_unassigned_access); } =20 static const TypeInfo sparc_cpu_type_info =3D { diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index 6fa7778..021eb157 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -582,8 +582,9 @@ static inline int tlb_compare_context(const SparcTLBE= ntry *tlb, =20 /* cpu-exec.c */ #if !defined(CONFIG_USER_ONLY) -void cpu_unassigned_access(CPUSPARCState *env1, hwaddr addr, - int is_write, int is_exec, int is_asi, int si= ze); +void sparc_cpu_unassigned_access(CPUState *cpu, hwaddr addr, + bool is_write, bool is_exec, int is_asi= , + unsigned size); #if defined(TARGET_SPARC64) hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr, int mmu_idx); diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c index 6d767fb..2936b58 100644 --- a/target-sparc/ldst_helper.c +++ b/target-sparc/ldst_helper.c @@ -686,7 +686,8 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulo= ng addr, int asi, int size, break; case 8: /* User code access, XXX */ default: - cpu_unassigned_access(env, addr, 0, 0, asi, size); + cpu_unassigned_access(CPU(sparc_env_get_cpu(env)), + addr, false, false, asi, size); ret =3D 0; break; } @@ -1088,7 +1089,8 @@ void helper_st_asi(CPUSPARCState *env, target_ulong= addr, uint64_t val, int asi, case 8: /* User code access, XXX */ case 9: /* Supervisor code access, XXX */ default: - cpu_unassigned_access(env, addr, 1, 0, asi, size); + cpu_unassigned_access(CPU(sparc_env_get_cpu(env)), + addr, true, false, asi, size); break; } #ifdef DEBUG_ASI @@ -1594,7 +1596,8 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_u= long addr, int asi, int size, case 0x5f: /* D-MMU demap, WO */ case 0x77: /* Interrupt vector, WO */ default: - cpu_unassigned_access(env, addr, 0, 0, 1, size); + cpu_unassigned_access(CPU(sparc_env_get_cpu(env)), + addr, false, false, 1, size); ret =3D 0; break; } @@ -2027,7 +2030,8 @@ void helper_st_asi(CPUSPARCState *env, target_ulong= addr, target_ulong val, case 0x8a: /* Primary no-fault LE, RO */ case 0x8b: /* Secondary no-fault LE, RO */ default: - cpu_unassigned_access(env, addr, 1, 0, 1, size); + cpu_unassigned_access(CPU(sparc_env_get_cpu(env)), + addr, true, false, 1, size); return; } } @@ -2322,9 +2326,12 @@ void helper_stqf(CPUSPARCState *env, target_ulong = addr, int mem_idx) =20 #if !defined(CONFIG_USER_ONLY) #ifndef TARGET_SPARC64 -void cpu_unassigned_access(CPUSPARCState *env, hwaddr addr, - int is_write, int is_exec, int is_asi, int si= ze) +void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr, + bool is_write, bool is_exec, int is_asi= , + unsigned size) { + SPARCCPU *cpu =3D SPARC_CPU(cs); + CPUSPARCState *env =3D &cpu->env; int fault_type; =20 #ifdef DEBUG_UNASSIGNED @@ -2382,9 +2389,13 @@ void cpu_unassigned_access(CPUSPARCState *env, hwa= ddr addr, } } #else -void cpu_unassigned_access(CPUSPARCState *env, hwaddr addr, - int is_write, int is_exec, int is_asi, int si= ze) +void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr, + bool is_write, bool is_exec, int is_asi= , + unsigned size) { + SPARCCPU *cpu =3D SPARC_CPU(cs); + CPUSPARCState *env =3D &cpu->env; + #ifdef DEBUG_UNASSIGNED printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FM= T_lx "\n", addr, env->pc); --=20 1.8.1.4