From: Michael Ellerman <michael@ellerman.id.au>
To: <linuxppc-dev@ozlabs.org>
Cc: sukadev@linux.vnet.ibm.com, Paul Mackerras <paulus@samba.org>,
khandual@linux.vnet.ibm.com
Subject: [PATCH 1/9] powerpc/perf: Check that events only include valid bits on Power8
Date: Fri, 28 Jun 2013 18:15:10 +1000 [thread overview]
Message-ID: <1372407319-718-1-git-send-email-michael@ellerman.id.au> (raw)
A mistake we have made in the past is that we pull out the fields we
need from the event code, but don't check that there are no unknown bits
set. This means that we can't ever assign meaning to those unknown bits
in future.
Although we have once again failed to do this at release, it is still
early days for Power8 so I think we can still slip this in and get away
with it.
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
---
arch/powerpc/perf/power8-pmu.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/powerpc/perf/power8-pmu.c b/arch/powerpc/perf/power8-pmu.c
index f7d1c4f..84cdc6d 100644
--- a/arch/powerpc/perf/power8-pmu.c
+++ b/arch/powerpc/perf/power8-pmu.c
@@ -109,6 +109,16 @@
#define EVENT_IS_MARKED (EVENT_MARKED_MASK << EVENT_MARKED_SHIFT)
#define EVENT_PSEL_MASK 0xff /* PMCxSEL value */
+#define EVENT_VALID_MASK \
+ ((EVENT_THRESH_MASK << EVENT_THRESH_SHIFT) | \
+ (EVENT_SAMPLE_MASK << EVENT_SAMPLE_SHIFT) | \
+ (EVENT_CACHE_SEL_MASK << EVENT_CACHE_SEL_SHIFT) | \
+ (EVENT_PMC_MASK << EVENT_PMC_SHIFT) | \
+ (EVENT_UNIT_MASK << EVENT_UNIT_SHIFT) | \
+ (EVENT_COMBINE_MASK << EVENT_COMBINE_SHIFT) | \
+ (EVENT_MARKED_MASK << EVENT_MARKED_SHIFT) | \
+ EVENT_PSEL_MASK)
+
/* MMCRA IFM bits - POWER8 */
#define POWER8_MMCRA_IFM1 0x0000000040000000UL
#define POWER8_MMCRA_IFM2 0x0000000080000000UL
@@ -212,6 +222,9 @@ static int power8_get_constraint(u64 event, unsigned long *maskp, unsigned long
mask = value = 0;
+ if (event & ~EVENT_VALID_MASK)
+ return -1;
+
pmc = (event >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
unit = (event >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK;
cache = (event >> EVENT_CACHE_SEL_SHIFT) & EVENT_CACHE_SEL_MASK;
--
1.7.10.4
next reply other threads:[~2013-06-28 8:15 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-06-28 8:15 Michael Ellerman [this message]
2013-06-28 8:15 ` [PATCH 2/9] powerpc/perf: Rework disable logic in pmu_disable() Michael Ellerman
2013-06-28 8:15 ` [PATCH 3/9] powerpc/perf: Freeze PMC5/6 if we're not using them Michael Ellerman
2013-06-28 8:15 ` [PATCH 4/9] powerpc/perf: Use existing out label in power_pmu_enable() Michael Ellerman
2013-06-28 8:15 ` [PATCH 5/9] powerpc/perf: Don't enable if we have zero events Michael Ellerman
2013-06-28 8:15 ` [PATCH 6/9] powerpc/perf: Drop MMCRA from thread_struct Michael Ellerman
2013-06-28 8:15 ` [PATCH 7/9] powerpc/perf: Core EBB support for 64-bit book3s Michael Ellerman
2013-06-28 8:15 ` [PATCH 8/9] powerpc/perf: Add power8 EBB support Michael Ellerman
2013-06-28 8:15 ` [PATCH 9/9] powerpc/pseries: Inform the hypervisor we are using EBB regs Michael Ellerman
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