From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42442) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Usb1l-0007X6-82 for qemu-devel@nongnu.org; Fri, 28 Jun 2013 11:56:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Usb1i-0003eW-Mu for qemu-devel@nongnu.org; Fri, 28 Jun 2013 11:56:01 -0400 Received: from cantor2.suse.de ([195.135.220.15]:44124 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Usb1i-0003do-5H for qemu-devel@nongnu.org; Fri, 28 Jun 2013 11:55:58 -0400 Received: from relay2.suse.de (unknown [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id 4E09EA5464 for ; Fri, 28 Jun 2013 17:55:57 +0200 (CEST) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Fri, 28 Jun 2013 17:55:27 +0200 Message-Id: <1372434946-18489-6-git-send-email-afaerber@suse.de> In-Reply-To: <1372434946-18489-1-git-send-email-afaerber@suse.de> References: <1372434946-18489-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PULL 05/24] target-openrisc: Register VMStateDescription for OpenRISCCPU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= Since commit e67db06e9f6d7e514ee2a9b9b769ecd42977f6fb (target-or32: Add target stubs and QOM cpu) a VMStateDescription existed, but CPU_SAVE_VERSION was not set, so it was never registered. Drop cpu_{save,load}() and register VMStateDescription via DeviceState. Use a version_id of 1 and specify minimum versions as well. Reviewed-by: Juan Quintela Signed-off-by: Andreas F=C3=A4rber --- target-openrisc/cpu.c | 1 + target-openrisc/cpu.h | 2 ++ target-openrisc/machine.c | 27 ++++++++++++++++----------- 3 files changed, 19 insertions(+), 11 deletions(-) diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c index ffe14f3..f8703a0 100644 --- a/target-openrisc/cpu.c +++ b/target-openrisc/cpu.c @@ -149,6 +149,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, = void *data) =20 cc->class_by_name =3D openrisc_cpu_class_by_name; cc->do_interrupt =3D openrisc_cpu_do_interrupt; + device_class_set_vmsd(dc, &vmstate_openrisc_cpu); } =20 static void cpu_register(const OpenRISCCPUInfo *info) diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h index b9c55ba..aee7769 100644 --- a/target-openrisc/cpu.h +++ b/target-openrisc/cpu.h @@ -360,6 +360,8 @@ int cpu_openrisc_signal_handler(int host_signum, void= *pinfo, void *puc); #define cpu_signal_handler cpu_openrisc_signal_handler =20 #ifndef CONFIG_USER_ONLY +extern const struct VMStateDescription vmstate_openrisc_cpu; + /* hw/openrisc_pic.c */ void cpu_openrisc_pic_init(OpenRISCCPU *cpu); =20 diff --git a/target-openrisc/machine.c b/target-openrisc/machine.c index cba9811..6f864fe 100644 --- a/target-openrisc/machine.c +++ b/target-openrisc/machine.c @@ -20,8 +20,11 @@ #include "hw/hw.h" #include "hw/boards.h" =20 -static const VMStateDescription vmstate_cpu =3D { - .name =3D "cpu", +static const VMStateDescription vmstate_env =3D { + .name =3D "env", + .version_id =3D 1, + .minimum_version_id =3D 1, + .minimum_version_id_old =3D 1, .fields =3D (VMStateField[]) { VMSTATE_UINT32_ARRAY(gpr, CPUOpenRISCState, 32), VMSTATE_UINT32(sr, CPUOpenRISCState), @@ -36,12 +39,14 @@ static const VMStateDescription vmstate_cpu =3D { } }; =20 -void cpu_save(QEMUFile *f, void *opaque) -{ - vmstate_save_state(f, &vmstate_cpu, opaque); -} - -int cpu_load(QEMUFile *f, void *opaque, int version_id) -{ - return vmstate_load_state(f, &vmstate_cpu, opaque, version_id); -} +const VMStateDescription vmstate_openrisc_cpu =3D { + .name =3D "cpu", + .version_id =3D 1, + .minimum_version_id =3D 1, + .minimum_version_id_old =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_CPU(), + VMSTATE_STRUCT(env, OpenRISCCPU, 1, vmstate_env, CPUOpenRISCStat= e), + VMSTATE_END_OF_LIST() + } +}; --=20 1.8.1.4