From: Ian Campbell <ian.campbell@citrix.com>
To: xen-devel@lists.xen.org
Cc: julien.grall@citrix.com, tim@xen.org,
Ian Campbell <ian.campbell@citrix.com>,
stefano.stabellini@eu.citrix.com
Subject: [PATCH 03/10] xen: arm: reduce instruction cache and tlb flushes to inner-shareable.
Date: Fri, 28 Jun 2013 17:10:49 +0100 [thread overview]
Message-ID: <1372435856-14040-3-git-send-email-ian.campbell@citrix.com> (raw)
In-Reply-To: <1372435809.8976.169.camel@zakaz.uk.xensource.com>
Now that Xen maps memory and performs pagetable walks as inner shareable we
don't need to push updates down so far when modifying page tables etc.
Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
---
xen/include/asm-arm/arm32/flushtlb.h | 4 ++--
xen/include/asm-arm/arm32/page.h | 8 ++++----
xen/include/asm-arm/arm64/flushtlb.h | 4 ++--
xen/include/asm-arm/arm64/page.h | 6 +++---
4 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/xen/include/asm-arm/arm32/flushtlb.h b/xen/include/asm-arm/arm32/flushtlb.h
index a258f58..14e8827 100644
--- a/xen/include/asm-arm/arm32/flushtlb.h
+++ b/xen/include/asm-arm/arm32/flushtlb.h
@@ -6,7 +6,7 @@ static inline void flush_tlb_local(void)
{
dsb();
- WRITE_CP32((uint32_t) 0, TLBIALL);
+ WRITE_CP32((uint32_t) 0, TLBIALLIS);
dsb();
isb();
@@ -17,7 +17,7 @@ static inline void flush_tlb_all_local(void)
{
dsb();
- WRITE_CP32((uint32_t) 0, TLBIALLNSNH);
+ WRITE_CP32((uint32_t) 0, TLBIALLNSNHIS);
dsb();
isb();
diff --git a/xen/include/asm-arm/arm32/page.h b/xen/include/asm-arm/arm32/page.h
index 38bcffd..e573502 100644
--- a/xen/include/asm-arm/arm32/page.h
+++ b/xen/include/asm-arm/arm32/page.h
@@ -39,8 +39,8 @@ static inline void flush_xen_text_tlb(void)
asm volatile (
"isb;" /* Ensure synchronization with previous changes to text */
STORE_CP32(0, TLBIALLH) /* Flush hypervisor TLB */
- STORE_CP32(0, ICIALLU) /* Flush I-cache */
- STORE_CP32(0, BPIALL) /* Flush branch predictor */
+ STORE_CP32(0, ICIALLUIS) /* Flush I-cache */
+ STORE_CP32(0, BPIALLIS) /* Flush branch predictor */
"dsb;" /* Ensure completion of TLB+BP flush */
"isb;"
: : "r" (r0) /*dummy*/ : "memory");
@@ -54,7 +54,7 @@ static inline void flush_xen_data_tlb(void)
{
register unsigned long r0 asm ("r0");
asm volatile("dsb;" /* Ensure preceding are visible */
- STORE_CP32(0, TLBIALLH)
+ STORE_CP32(0, TLBIALLHIS)
"dsb;" /* Ensure completion of the TLB flush */
"isb;"
: : "r" (r0) /* dummy */: "memory");
@@ -69,7 +69,7 @@ static inline void flush_xen_data_tlb_range_va(unsigned long va, unsigned long s
unsigned long end = va + size;
dsb(); /* Ensure preceding are visible */
while ( va < end ) {
- asm volatile(STORE_CP32(0, TLBIMVAH)
+ asm volatile(STORE_CP32(0, TLBIMVAHIS)
: : "r" (va) : "memory");
va += PAGE_SIZE;
}
diff --git a/xen/include/asm-arm/arm64/flushtlb.h b/xen/include/asm-arm/arm64/flushtlb.h
index d0535a0..3a6d2cb 100644
--- a/xen/include/asm-arm/arm64/flushtlb.h
+++ b/xen/include/asm-arm/arm64/flushtlb.h
@@ -6,7 +6,7 @@ static inline void flush_tlb_local(void)
{
asm volatile(
"dsb sy;"
- "tlbi vmalle1;"
+ "tlbi vmalle1is;"
"dsb sy;"
"isb;"
: : : "memory");
@@ -17,7 +17,7 @@ static inline void flush_tlb_all_local(void)
{
asm volatile(
"dsb sy;"
- "tlbi alle1;"
+ "tlbi alle1is;"
"dsb sy;"
"isb;"
: : : "memory");
diff --git a/xen/include/asm-arm/arm64/page.h b/xen/include/asm-arm/arm64/page.h
index bd48fe3..28748d3 100644
--- a/xen/include/asm-arm/arm64/page.h
+++ b/xen/include/asm-arm/arm64/page.h
@@ -33,7 +33,7 @@ static inline void flush_xen_text_tlb(void)
asm volatile (
"isb;" /* Ensure synchronization with previous changes to text */
"tlbi alle2;" /* Flush hypervisor TLB */
- "ic iallu;" /* Flush I-cache */
+ "ic ialluis;" /* Flush I-cache */
"dsb sy;" /* Ensure completion of TLB flush */
"isb;"
: : : "memory");
@@ -47,7 +47,7 @@ static inline void flush_xen_data_tlb(void)
{
asm volatile (
"dsb sy;" /* Ensure visibility of PTE writes */
- "tlbi alle2;" /* Flush hypervisor TLB */
+ "tlbi alle2is;" /* Flush hypervisor TLB */
"dsb sy;" /* Ensure completion of TLB flush */
"isb;"
: : : "memory");
@@ -62,7 +62,7 @@ static inline void flush_xen_data_tlb_range_va(unsigned long va, unsigned long s
unsigned long end = va + size;
dsb(); /* Ensure preceding are visible */
while ( va < end ) {
- asm volatile("tlbi vae2, %0;"
+ asm volatile("tlbi vae2is, %0;"
: : "r" (va>>PAGE_SHIFT) : "memory");
va += PAGE_SIZE;
}
--
1.7.2.5
next prev parent reply other threads:[~2013-06-28 16:10 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-06-28 16:10 [PATCH 00/10] xen: arm: map normal memory as inner shareable, reduce scope of various barriers Ian Campbell
2013-06-28 16:10 ` [PATCH 01/10] xen: arm: map memory as inner shareable Ian Campbell
2013-07-01 15:39 ` Stefano Stabellini
2013-07-01 15:42 ` Ian Campbell
2013-07-02 14:09 ` Leif Lindholm
2013-07-02 14:26 ` Ian Campbell
2013-07-04 10:58 ` Tim Deegan
2013-07-04 11:03 ` Ian Campbell
2013-06-28 16:10 ` [PATCH 02/10] xen: arm: Only upgrade guest barriers to " Ian Campbell
2013-07-01 15:24 ` Stefano Stabellini
2013-07-04 10:58 ` Tim Deegan
2013-06-28 16:10 ` Ian Campbell [this message]
2013-07-01 15:25 ` [PATCH 03/10] xen: arm: reduce instruction cache and tlb flushes to inner-shareable Stefano Stabellini
2013-07-04 11:07 ` Tim Deegan
2013-07-04 11:19 ` Tim Deegan
2013-07-04 11:21 ` Tim Deegan
2013-06-28 16:10 ` [PATCH 04/10] xen: arm: consolidate barrier definitions Ian Campbell
2013-07-01 15:25 ` Stefano Stabellini
2013-07-04 11:07 ` Tim Deegan
2013-06-28 16:10 ` [PATCH 05/10] xen: use SMP barrier in common code dealing with shared memory protocols Ian Campbell
2013-06-28 16:15 ` Ian Campbell
2013-06-28 16:20 ` Keir Fraser
2013-07-04 11:26 ` Tim Deegan
2013-06-28 16:10 ` [PATCH 06/10] xen: arm: Use SMP barriers when that is all which is required Ian Campbell
2013-07-01 15:19 ` Stefano Stabellini
2013-07-01 15:24 ` Ian Campbell
2013-07-04 11:30 ` Tim Deegan
2013-06-28 16:10 ` [PATCH 07/10] xen: arm: Use dmb for smp barriers Ian Campbell
2013-07-01 15:20 ` Stefano Stabellini
2013-07-04 11:31 ` Tim Deegan
2013-06-28 16:10 ` [PATCH 08/10] xen: arm: add scope to dsb and dmb macros Ian Campbell
2013-07-01 15:21 ` Stefano Stabellini
2013-07-01 15:22 ` Stefano Stabellini
2013-07-04 11:44 ` (no subject) Tim Deegan
2013-06-28 16:10 ` [PATCH 09/10] xen: arm: weaken SMP barriers to inner shareable Ian Campbell
2013-07-01 15:21 ` Stefano Stabellini
2013-07-01 15:22 ` Stefano Stabellini
2013-07-04 11:35 ` Tim Deegan
2013-06-28 16:10 ` [PATCH 10/10] xen: arm: use more specific barriers for read and write barriers Ian Campbell
2013-07-01 15:22 ` Stefano Stabellini
2013-07-04 11:42 ` Tim Deegan
2013-07-04 11:46 ` Ian Campbell
2013-06-28 16:11 ` [PATCH 00/10] xen: arm: map normal memory as inner shareable, reduce scope of various barriers Ian Campbell
2013-07-04 11:32 (no subject) Tim Deegan
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