[U-Boot] [PATCH 1/1] socfpga: Consolidating reset code into reset_manager.c. Also separating reset configuration for virtual target and real hardware Cyclone V development kit

* [U-Boot] [PATCH 1/1] socfpga: Consolidating reset code into reset_manager.c. Also separating reset configuration for virtual target and real hardware Cyclone V development kit
       [not found] ` <0BB3B561D7068A4E89FD8E9ABFB538BEB3B2E44331@PG-ITMSG03.altera.priv.altera.com>
@ 2013-06-27 13:27   ` Chin Liang See
  2013-06-28 11:44     ` Pavel Machek
  0 siblings, 1 reply; 9+ messages in thread
From: Chin Liang See @ 2013-06-27 13:27 UTC (permalink / raw)
  To: u-boot

socfpga: Consolidating reset code into reset_manager.c. Also separating
reset configuration for virtual target  and real hardware Cyclone V
development kit

Signed-off-by: Chin Liang See <clsee@altera.com>
---
 arch/arm/cpu/armv7/socfpga/Makefile               |    2 +-
 arch/arm/cpu/armv7/socfpga/misc.c                 |   27 -----------
 arch/arm/cpu/armv7/socfpga/reset_manager.c        |   50 +++++++++++++++++++++
 arch/arm/include/asm/arch-socfpga/reset_manager.h |   17 +++++++
 4 files changed, 68 insertions(+), 28 deletions(-)  create mode
100644 arch/arm/cpu/armv7/socfpga/reset_manager.c

diff --git a/arch/arm/cpu/armv7/socfpga/Makefile
b/arch/arm/cpu/armv7/socfpga/Makefile
index 376a4bd..518e67a 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk
 LIB    =  $(obj)lib$(SOC).o

 SOBJS    := lowlevel_init.o
-COBJS-y    := misc.o timer.o
+COBJS-y    := misc.o timer.o reset_manager.o
 COBJS-$(CONFIG_SPL_BUILD) += spl.o

 COBJS    := $(COBJS-y)
diff --git a/arch/arm/cpu/armv7/socfpga/misc.c
b/arch/arm/cpu/armv7/socfpga/misc.c
index fa16424..59f5b94 100644
--- a/arch/arm/cpu/armv7/socfpga/misc.c
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -17,36 +17,9 @@

 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/reset_manager.h>

 DECLARE_GLOBAL_DATA_PTR;

-static const struct socfpga_reset_manager *reset_manager_base =
-        (void *)SOCFPGA_RSTMGR_ADDRESS;
-
-/*
- * Write the reset manager register to cause reset
- */
-void reset_cpu(ulong addr)
-{
-    /* request a warm reset */
-    writel(RSTMGR_CTRL_SWWARMRSTREQ_LSB, &reset_manager_base->ctrl);
-    /*
-     * infinite loop here as watchdog will trigger and reset
-     * the processor
-     */
-    while (1)
-        ;
-}
-
-/*
- * Release peripherals from reset based on handoff
- */
-void reset_deassert_peripherals_handoff(void)
-{
-    writel(0, &reset_manager_base->per_mod_reset);
-}
-
 int dram_init(void)
 {
     gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
PHYS_SDRAM_1_SIZE); diff --git
a/arch/arm/cpu/armv7/socfpga/reset_manager.c
b/arch/arm/cpu/armv7/socfpga/reset_manager.c
new file mode 100644
index 0000000..b0cc399
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c
@@ -0,0 +1,50 @@
+/*
+ *  Copyright Altera Corporation (C) <2013>. All rights reserved
+ *
+ *  This program is free software; you can redistribute it and/or
+modify it
+ *  under the terms and conditions of the GNU General Public License,
+ *  version 2, as published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but
+WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+License for
+ *  more details.
+ *
+ *  You should have received a copy of the GNU General Public License
along with
+ *  this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/reset_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_reset_manager *reset_manager_base =
+        (void *)SOCFPGA_RSTMGR_ADDRESS;
+
+/*
+ * Write the reset manager register to cause reset  */ void
+reset_cpu(ulong addr) {
+    /* request a warm reset */
+    writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB),
+        &reset_manager_base->ctrl);
+    /*
+     * infinite loop here as watchdog will trigger and reset
+     * the processor
+     */
+    while (1)
+        ;
+}
+
+/*
+ * Release peripherals from reset based on handoff  */ void
+reset_deassert_peripherals_handoff(void)
+{
+    writel(0, &reset_manager_base->per_mod_reset);
+}
+
+
diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h
b/arch/arm/include/asm/arch-socfpga/reset_manager.h
index d9d2c1c..58d85e3 100644
--- a/arch/arm/include/asm/arch-socfpga/reset_manager.h
+++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h
@@ -21,6 +21,7 @@
 void reset_cpu(ulong addr);
 void reset_deassert_peripherals_handoff(void);

+#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
 struct socfpga_reset_manager {
     u32    padding1;
     u32    ctrl;
@@ -31,7 +32,23 @@ struct socfpga_reset_manager {
     u32    per2_mod_reset;
     u32    brg_mod_reset;
 };
+#else
+struct socfpga_reset_manager {
+    u32    status;
+    u32    ctrl;
+    u32    counts;
+    u32    padding1;
+    u32    mpu_mod_reset;
+    u32    per_mod_reset;
+    u32    per2_mod_reset;
+    u32    brg_mod_reset;
+};
+#endif

+#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
+#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
+#else
 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
+#endif

 #endif /* _RESET_MANAGER_H_ */
--
1.7.7.4


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