From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mika Kuoppala Subject: [PATCH 4/7] drm/i915: no hangcheck when reset is in progress Date: Wed, 3 Jul 2013 17:22:09 +0300 Message-ID: <1372861332-6308-5-git-send-email-mika.kuoppala@intel.com> References: <1372861332-6308-1-git-send-email-mika.kuoppala@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 08E52E5EEB for ; Wed, 3 Jul 2013 07:22:22 -0700 (PDT) In-Reply-To: <1372861332-6308-1-git-send-email-mika.kuoppala@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org From: Mika Kuoppala The timer for hangchecking can run again before the previous reset it has triggered has been handled. This can corrupt the hangcheck state as reset handling will access and write to the hangcheck data. To prevent this, avoid running the hangcheck logic while reset is in progress. Signed-off-by: Mika Kuoppala Reviewed-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_irq.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index dc1b878..b0fec7f 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2447,6 +2447,9 @@ void i915_hangcheck_elapsed(unsigned long data) if (!i915_enable_hangcheck) return; + if (i915_reset_in_progress(&dev_priv->gpu_error)) + return; + for_each_ring(ring, dev_priv, i) { u32 seqno, acthd; bool busy = true; -- 1.7.9.5