From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35410) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Uud7r-00071T-FJ for qemu-devel@nongnu.org; Thu, 04 Jul 2013 02:34:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Uud4J-0001fm-51 for qemu-devel@nongnu.org; Thu, 04 Jul 2013 02:31:05 -0400 Message-ID: <1372919197.4122.93.camel@pasglop> From: Benjamin Herrenschmidt Date: Thu, 04 Jul 2013 16:26:37 +1000 In-Reply-To: <51D50E2F.7000900@suse.de> References: <1372315560-5478-1-git-send-email-aik@ozlabs.ru> <1372315560-5478-17-git-send-email-aik@ozlabs.ru> <51D50E2F.7000900@suse.de> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH 16/17] ppc64: Enable QEMU to run on POWER 8 DD1 chip. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Andreas =?ISO-8859-1?Q?F=E4rber?= Cc: Anthony Liguori , Alexey Kardashevskiy , Alexander Graf , qemu-devel@nongnu.org, qemu-ppc@nongnu.org, Prerna Saxena , Paolo Bonzini , Paul Mackerras , David Gibson On Thu, 2013-07-04 at 07:54 +0200, Andreas F=C3=A4rber wrote: > Am 27.06.2013 08:45, schrieb Alexey Kardashevskiy: > > From: Prerna Saxena > >=20 > > This patch enables QEMU to launch VM guests on POWER8 chip. I have te= sted > > this to work with BML kernel on P8 dd1 chip. > >=20 > > Signed-off-by: Prerna Saxena > > Signed-off-by: Alexey Kardashevskiy > > Reviewed-by: Paul Mackerras >=20 > The subject slightly hides what the patch is actually doing: > Suggest "target-ppc: Add POWER8 v0.1 CPU model"? It's 1.0 anyway :-) > What's DD1, should that be added to the textual description? "DD" is how we call our chip revisions internally. DD1 is 1.0, DD1.1 is 1.1, etc.. Cheers, Ben. > > --- > > target-ppc/cpu-models.c | 3 +++ > > target-ppc/cpu-models.h | 1 + > > target-ppc/translate_init.c | 34 +++++++++++++++++++++++++++++++++= + > > 3 files changed, 38 insertions(+) > >=20 > > diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c > > index 9bb68c8..f8c64dd 100644 > > --- a/target-ppc/cpu-models.c > > +++ b/target-ppc/cpu-models.c > > @@ -1145,6 +1145,8 @@ > > "POWER7 v2.1") > > POWERPC_DEF("POWER7_v2.3", CPU_POWERPC_POWER7_v23, = POWER7, > > "POWER7 v2.3") > > + POWERPC_DEF("POWER8_v0.1", CPU_POWERPC_POWER8_v01, = POWER8, > > + "POWER8 v0.1") > > POWERPC_DEF("970", CPU_POWERPC_970, = 970, > > "PowerPC 970") > > POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, = 970FX, > > @@ -1390,6 +1392,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] =3D { > > { "Dino", "POWER3" }, > > { "POWER3+", "631" }, > > { "POWER7", "POWER7_v2.3" }, > > + { "POWER8", "POWER8_v0.1" }, > > { "970fx", "970fx_v3.1" }, > > { "970mp", "970mp_v1.1" }, > > { "Apache", "RS64" }, > > diff --git a/target-ppc/cpu-models.h b/target-ppc/cpu-models.h > > index 262ca47..b349ad2 100644 > > --- a/target-ppc/cpu-models.h > > +++ b/target-ppc/cpu-models.h > > @@ -556,6 +556,7 @@ enum { > > CPU_POWERPC_POWER7_v20 =3D 0x003F0200, > > CPU_POWERPC_POWER7_v21 =3D 0x003F0201, > > CPU_POWERPC_POWER7_v23 =3D 0x003F0203, > > + CPU_POWERPC_POWER8_v01 =3D 0x004B0100, >=20 > Are you sure this PVR is v0.1 and not v1.0? >=20 > Rest looks okay, although I wouldn't know how to check all flags. >=20 > Andreas >=20 > > CPU_POWERPC_970 =3D 0x00390202, > > CPU_POWERPC_970FX_v10 =3D 0x00391100, > > CPU_POWERPC_970FX_v20 =3D 0x003C0200, > > diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.= c > > index 95aebf7..2502758 100644 > > --- a/target-ppc/translate_init.c > > +++ b/target-ppc/translate_init.c > > @@ -7011,6 +7011,40 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *= data) > > pcc->l1_dcache_size =3D 0x8000; > > pcc->l1_icache_size =3D 0x8000; > > } > > + > > +POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) > > +{ > > + DeviceClass *dc =3D DEVICE_CLASS(oc); > > + PowerPCCPUClass *pcc =3D POWERPC_CPU_CLASS(oc); > > + > > + dc->desc =3D "POWER8"; > > + pcc->init_proc =3D init_proc_POWER7; > > + pcc->check_pow =3D check_pow_nocheck; > > + pcc->insns_flags =3D PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | > > + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | > > + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | > > + PPC_FLOAT_STFIWX | > > + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | > > + PPC_MEM_SYNC | PPC_MEM_EIEIO | > > + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | > > + PPC_64B | PPC_ALTIVEC | > > + PPC_SEGMENT_64B | PPC_SLBI | > > + PPC_POPCNTB | PPC_POPCNTWD; > > + pcc->insns_flags2 =3D PPC2_VSX | PPC2_DFP | PPC2_DBRX; > > + pcc->msr_mask =3D 0x800000000204FF36ULL; > > + pcc->mmu_model =3D POWERPC_MMU_2_06; > > +#if defined(CONFIG_SOFTMMU) > > + pcc->handle_mmu_fault =3D ppc_hash64_handle_mmu_fault; > > +#endif > > + pcc->excp_model =3D POWERPC_EXCP_POWER7; > > + pcc->bus_model =3D PPC_FLAGS_INPUT_POWER7; > > + pcc->bfd_mach =3D bfd_mach_ppc64; > > + pcc->flags =3D POWERPC_FLAG_VRE | POWERPC_FLAG_SE | > > + POWERPC_FLAG_BE | POWERPC_FLAG_PMM | > > + POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR; > > + pcc->l1_dcache_size =3D 0x8000; > > + pcc->l1_icache_size =3D 0x8000; > > +} > > #endif /* defined (TARGET_PPC64) */ > > =20 > > =20 >=20 >=20