From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52623) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Uvtfy-0005Lb-JW for qemu-devel@nongnu.org; Sun, 07 Jul 2013 14:27:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Uvtfp-0004qq-27 for qemu-devel@nongnu.org; Sun, 07 Jul 2013 14:27:10 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sun, 7 Jul 2013 20:26:04 +0200 Message-Id: <1373221591-17091-16-git-send-email-afaerber@suse.de> In-Reply-To: <1373221591-17091-1-git-send-email-afaerber@suse.de> References: <1373221591-17091-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH qom-cpu v2 15/42] cpu: Turn cpu_get_phys_page_debug() into a CPUClass hook List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Jia Liu , Anthony Green , Alexander Graf , Blue Swirl , Max Filippov , Michael Walle , "open list:PowerPC" , Paul Brook , "Edgar E. Iglesias" , Guan Xuetao , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Aurelien Jarno , Richard Henderson Change breakpoint_invalidate() argument to CPUState alongside. Since all targets now assign a softmmu-only field, we can drop helpers cpu_class_set_{do_unassigned_access,vmsd}() and device_class_set_vmsd(). Prepares for changing cpu_memory_rw_debug() argument to CPUState. Signed-off-by: Andreas F=C3=A4rber --- exec.c | 20 ++++++------ hw/i386/kvmvapic.c | 6 ++-- hw/xtensa/xtensa_lx60.c | 8 +++-- hw/xtensa/xtensa_sim.c | 10 +++--- include/exec/cpu-all.h | 5 --- include/qom/cpu.h | 74 +++++++++++++--------------------------= ------ target-alpha/cpu-qom.h | 1 + target-alpha/cpu.c | 7 +++-- target-alpha/helper.c | 5 +-- target-arm/cpu-qom.h | 2 ++ target-arm/cpu.c | 5 ++- target-arm/helper.c | 8 +++-- target-cris/cpu-qom.h | 2 ++ target-cris/cpu.c | 3 ++ target-cris/helper.c | 7 +++-- target-i386/cpu-qom.h | 2 ++ target-i386/cpu.c | 3 +- target-i386/helper.c | 4 ++- target-lm32/cpu-qom.h | 1 + target-lm32/cpu.c | 5 ++- target-lm32/helper.c | 6 ++-- target-m68k/cpu-qom.h | 1 + target-m68k/cpu.c | 3 ++ target-m68k/helper.c | 2 +- target-microblaze/cpu-qom.h | 1 + target-microblaze/cpu.c | 5 ++- target-microblaze/helper.c | 4 ++- target-mips/cpu-qom.h | 1 + target-mips/cpu.c | 5 ++- target-mips/helper.c | 7 +++-- target-moxie/cpu.c | 5 ++- target-moxie/cpu.h | 1 + target-moxie/helper.c | 11 +++---- target-openrisc/cpu.c | 5 ++- target-openrisc/cpu.h | 1 + target-openrisc/mmu.c | 5 ++- target-ppc/cpu-qom.h | 1 + target-ppc/mmu_helper.c | 4 ++- target-ppc/translate_init.c | 3 ++ target-s390x/cpu-qom.h | 1 + target-s390x/cpu.c | 3 ++ target-s390x/helper.c | 5 +-- target-sh4/cpu-qom.h | 1 + target-sh4/cpu.c | 3 ++ target-sh4/helper.c | 5 +-- target-sparc/cpu-qom.h | 1 + target-sparc/cpu.c | 5 ++- target-sparc/mmu_helper.c | 11 ++++--- target-unicore32/cpu-qom.h | 1 + target-unicore32/cpu.c | 3 ++ target-unicore32/softmmu.c | 7 +++-- target-xtensa/cpu-qom.h | 1 + target-xtensa/cpu.c | 3 ++ target-xtensa/helper.c | 7 +++-- target-xtensa/xtensa-semi.c | 4 +-- 55 files changed, 182 insertions(+), 128 deletions(-) diff --git a/exec.c b/exec.c index 4c9e921..a768aea 100644 --- a/exec.c +++ b/exec.c @@ -415,14 +415,14 @@ void cpu_exec_init(CPUArchState *env) =20 #if defined(TARGET_HAS_ICE) #if defined(CONFIG_USER_ONLY) -static void breakpoint_invalidate(CPUArchState *env, target_ulong pc) +static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) { tb_invalidate_phys_page_range(pc, pc + 1, 0); } #else -static void breakpoint_invalidate(CPUArchState *env, target_ulong pc) +static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) { - tb_invalidate_phys_addr(cpu_get_phys_page_debug(env, pc) | + tb_invalidate_phys_addr(cpu_get_phys_page_debug(cpu, pc) | (pc & ~TARGET_PAGE_MASK)); } #endif @@ -525,15 +525,17 @@ int cpu_breakpoint_insert(CPUArchState *env, target= _ulong pc, int flags, bp->flags =3D flags; =20 /* keep all GDB-injected breakpoints in front */ - if (flags & BP_GDB) + if (flags & BP_GDB) { QTAILQ_INSERT_HEAD(&env->breakpoints, bp, entry); - else + } else { QTAILQ_INSERT_TAIL(&env->breakpoints, bp, entry); + } =20 - breakpoint_invalidate(env, pc); + breakpoint_invalidate(ENV_GET_CPU(env), pc); =20 - if (breakpoint) + if (breakpoint) { *breakpoint =3D bp; + } return 0; #else return -ENOSYS; @@ -564,7 +566,7 @@ void cpu_breakpoint_remove_by_ref(CPUArchState *env, = CPUBreakpoint *breakpoint) #if defined(TARGET_HAS_ICE) QTAILQ_REMOVE(&env->breakpoints, breakpoint, entry); =20 - breakpoint_invalidate(env, breakpoint->pc); + breakpoint_invalidate(ENV_GET_CPU(env), breakpoint->pc); =20 g_free(breakpoint); #endif @@ -2581,7 +2583,7 @@ int cpu_memory_rw_debug(CPUArchState *env, target_u= long addr, =20 while (len > 0) { page =3D addr & TARGET_PAGE_MASK; - phys_addr =3D cpu_get_phys_page_debug(env, page); + phys_addr =3D cpu_get_phys_page_debug(ENV_GET_CPU(env), page); /* if no physical page mapped, return an error */ if (phys_addr =3D=3D -1) return -1; diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c index ccd089a..224601f 100644 --- a/hw/i386/kvmvapic.c +++ b/hw/i386/kvmvapic.c @@ -146,6 +146,7 @@ static void update_guest_rom_state(VAPICROMState *s) =20 static int find_real_tpr_addr(VAPICROMState *s, CPUX86State *env) { + CPUState *cs =3D CPU(x86_env_get_cpu(env)); hwaddr paddr; target_ulong addr; =20 @@ -158,7 +159,7 @@ static int find_real_tpr_addr(VAPICROMState *s, CPUX8= 6State *env) * virtual address space for the APIC mapping. */ for (addr =3D 0xfffff000; addr >=3D 0x80000000; addr -=3D TARGET_PAG= E_SIZE) { - paddr =3D cpu_get_phys_page_debug(env, addr); + paddr =3D cpu_get_phys_page_debug(cs, addr); if (paddr !=3D APIC_DEFAULT_ADDRESS) { continue; } @@ -271,6 +272,7 @@ instruction_ok: =20 static int update_rom_mapping(VAPICROMState *s, CPUX86State *env, target= _ulong ip) { + CPUState *cs =3D CPU(x86_env_get_cpu(env)); hwaddr paddr; uint32_t rom_state_vaddr; uint32_t pos, patch, offset; @@ -287,7 +289,7 @@ static int update_rom_mapping(VAPICROMState *s, CPUX8= 6State *env, target_ulong i =20 /* find out virtual address of the ROM */ rom_state_vaddr =3D s->rom_state_paddr + (ip & 0xf0000000); - paddr =3D cpu_get_phys_page_debug(env, rom_state_vaddr); + paddr =3D cpu_get_phys_page_debug(cs, rom_state_vaddr); if (paddr =3D=3D -1) { return -1; } diff --git a/hw/xtensa/xtensa_lx60.c b/hw/xtensa/xtensa_lx60.c index 075daf1..1138666 100644 --- a/hw/xtensa/xtensa_lx60.c +++ b/hw/xtensa/xtensa_lx60.c @@ -144,9 +144,11 @@ static void lx60_net_init(MemoryRegion *address_spac= e, memory_region_add_subregion(address_space, buffers, ram); } =20 -static uint64_t translate_phys_addr(void *env, uint64_t addr) +static uint64_t translate_phys_addr(void *opaque, uint64_t addr) { - return cpu_get_phys_page_debug(env, addr); + XtensaCPU *cpu =3D opaque; + + return cpu_get_phys_page_debug(CPU(cpu), addr); } =20 static void lx60_reset(void *opaque) @@ -252,7 +254,7 @@ static void lx_init(const LxBoardDesc *board, QEMUMac= hineInitArgs *args) } uint64_t elf_entry; uint64_t elf_lowaddr; - int success =3D load_elf(kernel_filename, translate_phys_addr, e= nv, + int success =3D load_elf(kernel_filename, translate_phys_addr, c= pu, &elf_entry, &elf_lowaddr, NULL, be, ELF_MACHINE, 0); if (success > 0) { env->pc =3D elf_entry; diff --git a/hw/xtensa/xtensa_sim.c b/hw/xtensa/xtensa_sim.c index a88707e..ea91162 100644 --- a/hw/xtensa/xtensa_sim.c +++ b/hw/xtensa/xtensa_sim.c @@ -32,9 +32,11 @@ #include "exec/memory.h" #include "exec/address-spaces.h" =20 -static uint64_t translate_phys_addr(void *env, uint64_t addr) +static uint64_t translate_phys_addr(void *opaque, uint64_t addr) { - return cpu_get_phys_page_debug(env, addr); + XtensaCPU *cpu =3D opaque; + + return cpu_get_phys_page_debug(CPU(cpu), addr); } =20 static void sim_reset(void *opaque) @@ -88,10 +90,10 @@ static void xtensa_sim_init(QEMUMachineInitArgs *args= ) uint64_t elf_entry; uint64_t elf_lowaddr; #ifdef TARGET_WORDS_BIGENDIAN - int success =3D load_elf(kernel_filename, translate_phys_addr, e= nv, + int success =3D load_elf(kernel_filename, translate_phys_addr, c= pu, &elf_entry, &elf_lowaddr, NULL, 1, ELF_MACHINE, 0); #else - int success =3D load_elf(kernel_filename, translate_phys_addr, e= nv, + int success =3D load_elf(kernel_filename, translate_phys_addr, c= pu, &elf_entry, &elf_lowaddr, NULL, 0, ELF_MACHINE, 0); #endif if (success > 0) { diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 1f3c002..16eeb7a 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -430,11 +430,6 @@ void cpu_watchpoint_remove_all(CPUArchState *env, in= t mask); =20 #if !defined(CONFIG_USER_ONLY) =20 -/* Return the physical page corresponding to a virtual one. Use it - only for debugging because no protection checks are done. Return -1 - if no page found. */ -hwaddr cpu_get_phys_page_debug(CPUArchState *env, target_ulong addr); - /* memory API */ =20 extern int phys_ram_fd; diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 641be1c..fe82822 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -74,6 +74,7 @@ struct TranslationBlock; * @set_pc: Callback for setting the Program Counter register. * @synchronize_from_tb: Callback for synchronizing state from a TCG * #TranslationBlock. + * @get_phys_page_debug: Callback for obtaining a physical address. * @vmsd: State description for migration. * * Represents a CPU family or model. @@ -99,6 +100,7 @@ typedef struct CPUClass { Error **errp); void (*set_pc)(CPUState *cpu, vaddr value); void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *= tb); + hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); =20 const struct VMStateDescription *vmsd; int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu, @@ -276,6 +278,25 @@ void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_= function cpu_fprintf, void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fp= rintf, int flags); =20 +#ifndef CONFIG_USER_ONLY +/** + * cpu_get_phys_page_debug: + * @cpu: The CPU to obtain the physical page address for. + * @addr: The virtual address. + * + * Obtains the physical page corresponding to a virtual one. + * Use it only for debugging because no protection checks are done. + * + * Returns: Corresponding physical page address or -1 if no page found. + */ +static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + return cc->get_phys_page_debug(cpu, addr); +} +#endif + /** * cpu_reset: * @cpu: The CPU whose state is to be reset. @@ -294,59 +315,6 @@ void cpu_reset(CPUState *cpu); ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_mod= el); =20 /** - * cpu_class_set_vmsd: - * @cc: CPU class - * @value: Value to set. Unused for %CONFIG_USER_ONLY. - * - * Sets #VMStateDescription for @cc. - * - * The @value argument is intentionally discarded for the non-softmmu ta= rgets - * to avoid linker errors or excessive preprocessor usage. If this behav= ior - * is undesired, you should assign #CPUClass.vmsd directly instead. - */ -#ifndef CONFIG_USER_ONLY -static inline void cpu_class_set_vmsd(CPUClass *cc, - const struct VMStateDescription *v= alue) -{ - cc->vmsd =3D value; -} -#else -#define cpu_class_set_vmsd(cc, value) ((cc)->vmsd =3D NULL) -#endif - -#ifndef CONFIG_USER_ONLY -static inline void cpu_class_set_do_unassigned_access(CPUClass *cc, - CPUUnassignedAcces= s value) -{ - cc->do_unassigned_access =3D value; -} -#else -#define cpu_class_set_do_unassigned_access(cc, value) \ - ((cc)->do_unassigned_access =3D NULL) -#endif - -/** - * device_class_set_vmsd: - * @dc: Device class - * @value: Value to set. Unused for %CONFIG_USER_ONLY. - * - * Sets #VMStateDescription for @dc. - * - * The @value argument is intentionally discarded for the non-softmmu ta= rgets - * to avoid linker errors or excessive preprocessor usage. If this behav= ior - * is undesired, you should assign #DeviceClass.vmsd directly instead. - */ -#ifndef CONFIG_USER_ONLY -static inline void device_class_set_vmsd(DeviceClass *dc, - const struct VMStateDescription= *value) -{ - dc->vmsd =3D value; -} -#else -#define device_class_set_vmsd(dc, value) ((dc)->vmsd =3D NULL) -#endif - -/** * qemu_cpu_has_work: * @cpu: The vCPU to check. * diff --git a/target-alpha/cpu-qom.h b/target-alpha/cpu-qom.h index 60125b1..b2eeba3 100644 --- a/target-alpha/cpu-qom.h +++ b/target-alpha/cpu-qom.h @@ -81,5 +81,6 @@ extern const struct VMStateDescription vmstate_alpha_cp= u; void alpha_cpu_do_interrupt(CPUState *cpu); void alpha_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fp= rintf, int flags); +hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); =20 #endif diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c index 09bb7a8..c8c8c2c 100644 --- a/target-alpha/cpu.c +++ b/target-alpha/cpu.c @@ -270,9 +270,12 @@ static void alpha_cpu_class_init(ObjectClass *oc, vo= id *data) cc->class_by_name =3D alpha_cpu_class_by_name; cc->do_interrupt =3D alpha_cpu_do_interrupt; cc->dump_state =3D alpha_cpu_dump_state; - cpu_class_set_do_unassigned_access(cc, alpha_cpu_unassigned_access); cc->set_pc =3D alpha_cpu_set_pc; - device_class_set_vmsd(dc, &vmstate_alpha_cpu); +#ifndef CONFIG_USER_ONLY + cc->do_unassigned_access =3D alpha_cpu_unassigned_access; + cc->get_phys_page_debug =3D alpha_cpu_get_phys_page_debug; + dc->vmsd =3D &vmstate_alpha_cpu; +#endif } =20 static const TypeInfo alpha_cpu_type_info =3D { diff --git a/target-alpha/helper.c b/target-alpha/helper.c index ff57dd6..fc61bb0 100644 --- a/target-alpha/helper.c +++ b/target-alpha/helper.c @@ -315,12 +315,13 @@ static int get_physical_address(CPUAlphaState *env,= target_ulong addr, return ret; } =20 -hwaddr cpu_get_phys_page_debug(CPUAlphaState *env, target_ulong addr) +hwaddr alpha_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { + AlphaCPU *cpu =3D ALPHA_CPU(cs); target_ulong phys; int prot, fail; =20 - fail =3D get_physical_address(env, addr, 0, 0, &phys, &prot); + fail =3D get_physical_address(&cpu->env, addr, 0, 0, &phys, &prot); return (fail >=3D 0 ? -1 : phys); } =20 diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index 48ba605..02162c9 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -147,4 +147,6 @@ void arm_v7m_cpu_do_interrupt(CPUState *cpu); void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fpri= ntf, int flags); =20 +hwaddr arm_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); + #endif diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 4809fd0..90f6455 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -819,7 +819,10 @@ static void arm_cpu_class_init(ObjectClass *oc, void= *data) cc->do_interrupt =3D arm_cpu_do_interrupt; cc->dump_state =3D arm_cpu_dump_state; cc->set_pc =3D arm_cpu_set_pc; - cpu_class_set_vmsd(cc, &vmstate_arm_cpu); +#ifndef CONFIG_USER_ONLY + cc->get_phys_page_debug =3D arm_cpu_get_phys_page_debug; + cc->vmsd =3D &vmstate_arm_cpu; +#endif } =20 static void cpu_register(const ARMCPUInfo *info) diff --git a/target-arm/helper.c b/target-arm/helper.c index 5f639fd..2a2bb83 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2749,17 +2749,19 @@ int cpu_arm_handle_mmu_fault (CPUARMState *env, t= arget_ulong address, return 1; } =20 -hwaddr cpu_get_phys_page_debug(CPUARMState *env, target_ulong addr) +hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { + ARMCPU *cpu =3D ARM_CPU(cs); hwaddr phys_addr; target_ulong page_size; int prot; int ret; =20 - ret =3D get_phys_addr(env, addr, 0, 0, &phys_addr, &prot, &page_size= ); + ret =3D get_phys_addr(&cpu->env, addr, 0, 0, &phys_addr, &prot, &pag= e_size); =20 - if (ret !=3D 0) + if (ret !=3D 0) { return -1; + } =20 return phys_addr; } diff --git a/target-cris/cpu-qom.h b/target-cris/cpu-qom.h index af7d14d..d7baf07 100644 --- a/target-cris/cpu-qom.h +++ b/target-cris/cpu-qom.h @@ -79,4 +79,6 @@ void crisv10_cpu_do_interrupt(CPUState *cpu); void cris_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fpr= intf, int flags); =20 +hwaddr cris_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); + #endif diff --git a/target-cris/cpu.c b/target-cris/cpu.c index b72fd98..ba095e7 100644 --- a/target-cris/cpu.c +++ b/target-cris/cpu.c @@ -255,6 +255,9 @@ static void cris_cpu_class_init(ObjectClass *oc, void= *data) cc->do_interrupt =3D cris_cpu_do_interrupt; cc->dump_state =3D cris_cpu_dump_state; cc->set_pc =3D cris_cpu_set_pc; +#ifndef CONFIG_USER_ONLY + cc->get_phys_page_debug =3D cris_cpu_get_phys_page_debug; +#endif } =20 static const TypeInfo cris_cpu_type_info =3D { diff --git a/target-cris/helper.c b/target-cris/helper.c index aba7537..d274b38 100644 --- a/target-cris/helper.c +++ b/target-cris/helper.c @@ -255,16 +255,17 @@ void cris_cpu_do_interrupt(CPUState *cs) env->pregs[PR_ERP]); } =20 -hwaddr cpu_get_phys_page_debug(CPUCRISState * env, target_ulong addr) +hwaddr cris_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { + CRISCPU *cpu =3D CRIS_CPU(cs); uint32_t phy =3D addr; struct cris_mmu_result res; int miss; =20 - miss =3D cris_mmu_translate(&res, env, addr, 0, 0, 1); + miss =3D cris_mmu_translate(&res, &cpu->env, addr, 0, 0, 1); /* If D TLB misses, try I TLB. */ if (miss) { - miss =3D cris_mmu_translate(&res, env, addr, 2, 0, 1); + miss =3D cris_mmu_translate(&res, &cpu->env, addr, 2, 0, 1); } =20 if (!miss) { diff --git a/target-i386/cpu-qom.h b/target-i386/cpu-qom.h index 7e55e5f..d928562 100644 --- a/target-i386/cpu-qom.h +++ b/target-i386/cpu-qom.h @@ -104,4 +104,6 @@ void x86_cpu_get_memory_mapping(CPUState *cpu, Memory= MappingList *list, void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fpri= ntf, int flags); =20 +hwaddr x86_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); + #endif diff --git a/target-i386/cpu.c b/target-i386/cpu.c index b57ea4b..cd350cb 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -2542,12 +2542,13 @@ static void x86_cpu_common_class_init(ObjectClass= *oc, void *data) cc->get_paging_enabled =3D x86_cpu_get_paging_enabled; #ifndef CONFIG_USER_ONLY cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; + cc->get_phys_page_debug =3D x86_cpu_get_phys_page_debug; cc->write_elf64_note =3D x86_cpu_write_elf64_note; cc->write_elf64_qemunote =3D x86_cpu_write_elf64_qemunote; cc->write_elf32_note =3D x86_cpu_write_elf32_note; cc->write_elf32_qemunote =3D x86_cpu_write_elf32_qemunote; + cc->vmsd =3D &vmstate_x86_cpu; #endif - cpu_class_set_vmsd(cc, &vmstate_x86_cpu); } =20 static const TypeInfo x86_cpu_type_info =3D { diff --git a/target-i386/helper.c b/target-i386/helper.c index d6f43d7..2745292 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -884,8 +884,10 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, targe= t_ulong addr, return 1; } =20 -hwaddr cpu_get_phys_page_debug(CPUX86State *env, target_ulong addr) +hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; target_ulong pde_addr, pte_addr; uint64_t pte; hwaddr paddr; diff --git a/target-lm32/cpu-qom.h b/target-lm32/cpu-qom.h index e3bb619..9e27329 100644 --- a/target-lm32/cpu-qom.h +++ b/target-lm32/cpu-qom.h @@ -78,5 +78,6 @@ extern const struct VMStateDescription vmstate_lm32_cpu= ; void lm32_cpu_do_interrupt(CPUState *cpu); void lm32_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fp= rintf, int flags); +hwaddr lm32_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); =20 #endif diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c index 8aa28b5..ce55e48 100644 --- a/target-lm32/cpu.c +++ b/target-lm32/cpu.c @@ -87,7 +87,10 @@ static void lm32_cpu_class_init(ObjectClass *oc, void = *data) cc->do_interrupt =3D lm32_cpu_do_interrupt; cc->dump_state =3D lm32_cpu_dump_state; cc->set_pc =3D lm32_cpu_set_pc; - cpu_class_set_vmsd(cc, &vmstate_lm32_cpu); +#ifndef CONFIG_USER_ONLY + cc->get_phys_page_debug =3D lm32_cpu_get_phys_page_debug; + cc->vmsd =3D &vmstate_lm32_cpu; +#endif } =20 static const TypeInfo lm32_cpu_type_info =3D { diff --git a/target-lm32/helper.c b/target-lm32/helper.c index 615b44e..15bc615 100644 --- a/target-lm32/helper.c +++ b/target-lm32/helper.c @@ -37,10 +37,12 @@ int cpu_lm32_handle_mmu_fault(CPULM32State *env, targ= et_ulong address, int rw, return 0; } =20 -hwaddr cpu_get_phys_page_debug(CPULM32State *env, target_ulong addr) +hwaddr lm32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { + LM32CPU *cpu =3D LM32_CPU(cs); + addr &=3D TARGET_PAGE_MASK; - if (env->flags & LM32_FLAG_IGNORE_MSB) { + if (cpu->env.flags & LM32_FLAG_IGNORE_MSB) { return addr & 0x7fffffff; } else { return addr; diff --git a/target-m68k/cpu-qom.h b/target-m68k/cpu-qom.h index 858bf30..7115707 100644 --- a/target-m68k/cpu-qom.h +++ b/target-m68k/cpu-qom.h @@ -73,5 +73,6 @@ static inline M68kCPU *m68k_env_get_cpu(CPUM68KState *e= nv) void m68k_cpu_do_interrupt(CPUState *cpu); void m68k_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fp= rintf, int flags); +hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); =20 #endif diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c index 43011e7..988f476 100644 --- a/target-m68k/cpu.c +++ b/target-m68k/cpu.c @@ -190,6 +190,9 @@ static void m68k_cpu_class_init(ObjectClass *c, void = *data) cc->do_interrupt =3D m68k_cpu_do_interrupt; cc->dump_state =3D m68k_cpu_dump_state; cc->set_pc =3D m68k_cpu_set_pc; +#ifndef CONFIG_USER_ONLY + cc->get_phys_page_debug =3D m68k_cpu_get_phys_page_debug; +#endif dc->vmsd =3D &vmstate_m68k_cpu; } =20 diff --git a/target-m68k/helper.c b/target-m68k/helper.c index 54fa419..dcadfab 100644 --- a/target-m68k/helper.c +++ b/target-m68k/helper.c @@ -290,7 +290,7 @@ int cpu_m68k_handle_mmu_fault (CPUM68KState *env, tar= get_ulong address, int rw, /* MMU */ =20 /* TODO: This will need fixing once the MMU is implemented. */ -hwaddr cpu_get_phys_page_debug(CPUM68KState *env, target_ulong addr) +hwaddr m68k_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { return addr; } diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h index ec2b989..1318a36 100644 --- a/target-microblaze/cpu-qom.h +++ b/target-microblaze/cpu-qom.h @@ -74,5 +74,6 @@ static inline MicroBlazeCPU *mb_env_get_cpu(CPUMBState = *env) void mb_cpu_do_interrupt(CPUState *cs); void mb_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fpri= ntf, int flags); +hwaddr mb_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); =20 #endif diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c index 0a9bcfa..9f10c8c 100644 --- a/target-microblaze/cpu.c +++ b/target-microblaze/cpu.c @@ -140,8 +140,11 @@ static void mb_cpu_class_init(ObjectClass *oc, void = *data) =20 cc->do_interrupt =3D mb_cpu_do_interrupt; cc->dump_state =3D mb_cpu_dump_state; - cpu_class_set_do_unassigned_access(cc, mb_cpu_unassigned_access); cc->set_pc =3D mb_cpu_set_pc; +#ifndef CONFIG_USER_ONLY + cc->do_unassigned_access =3D mb_cpu_unassigned_access; + cc->get_phys_page_debug =3D mb_cpu_get_phys_page_debug; +#endif dc->vmsd =3D &vmstate_mb_cpu; dc->props =3D mb_properties; } diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c index c6c96d4..4fa9ce9 100644 --- a/target-microblaze/helper.c +++ b/target-microblaze/helper.c @@ -265,8 +265,10 @@ void mb_cpu_do_interrupt(CPUState *cs) } } =20 -hwaddr cpu_get_phys_page_debug(CPUMBState * env, target_ulong addr) +hwaddr mb_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { + MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); + CPUMBState *env =3D &cpu->env; target_ulong vaddr, paddr =3D 0; struct microblaze_mmu_lookup lu; unsigned int hit; diff --git a/target-mips/cpu-qom.h b/target-mips/cpu-qom.h index 654744a..7c8e616 100644 --- a/target-mips/cpu-qom.h +++ b/target-mips/cpu-qom.h @@ -77,5 +77,6 @@ static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *e= nv) void mips_cpu_do_interrupt(CPUState *cpu); void mips_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fp= rintf, int flags); +hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); =20 #endif diff --git a/target-mips/cpu.c b/target-mips/cpu.c index 1581cd9..4834c86 100644 --- a/target-mips/cpu.c +++ b/target-mips/cpu.c @@ -98,9 +98,12 @@ static void mips_cpu_class_init(ObjectClass *c, void *= data) =20 cc->do_interrupt =3D mips_cpu_do_interrupt; cc->dump_state =3D mips_cpu_dump_state; - cpu_class_set_do_unassigned_access(cc, mips_cpu_unassigned_access); cc->set_pc =3D mips_cpu_set_pc; cc->synchronize_from_tb =3D mips_cpu_synchronize_from_tb; +#ifndef CONFIG_USER_ONLY + cc->do_unassigned_access =3D mips_cpu_unassigned_access; + cc->get_phys_page_debug =3D mips_cpu_get_phys_page_debug; +#endif } =20 static const TypeInfo mips_cpu_type_info =3D { diff --git a/target-mips/helper.c b/target-mips/helper.c index 6983b92..6feef7b 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -254,13 +254,16 @@ static void raise_mmu_exception(CPUMIPSState *env, = target_ulong address, } =20 #if !defined(CONFIG_USER_ONLY) -hwaddr cpu_get_phys_page_debug(CPUMIPSState *env, target_ulong addr) +hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { + MIPSCPU *cpu =3D MIPS_CPU(cs); hwaddr phys_addr; int prot; =20 - if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT= ) !=3D 0) + if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, + ACCESS_INT) !=3D 0) { return -1; + } return phys_addr; } #endif diff --git a/target-moxie/cpu.c b/target-moxie/cpu.c index 91f6197..6550be5 100644 --- a/target-moxie/cpu.c +++ b/target-moxie/cpu.c @@ -101,7 +101,10 @@ static void moxie_cpu_class_init(ObjectClass *oc, vo= id *data) cc->do_interrupt =3D moxie_cpu_do_interrupt; cc->dump_state =3D moxie_cpu_dump_state; cc->set_pc =3D moxie_cpu_set_pc; - cpu_class_set_vmsd(cc, &vmstate_moxie_cpu); +#ifndef CONFIG_USER_ONLY + cc->get_phys_page_debug =3D moxie_cpu_get_phys_page_debug; + cc->vmsd =3D &vmstate_moxie_cpu; +#endif } =20 static void moxielite_initfn(Object *obj) diff --git a/target-moxie/cpu.h b/target-moxie/cpu.h index d5030a4..5ce14b5 100644 --- a/target-moxie/cpu.h +++ b/target-moxie/cpu.h @@ -118,6 +118,7 @@ int cpu_moxie_exec(CPUMoxieState *s); void moxie_cpu_do_interrupt(CPUState *cs); void moxie_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, int flags); +hwaddr moxie_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void moxie_translate_init(void); int cpu_moxie_signal_handler(int host_signum, void *pinfo, void *puc); diff --git a/target-moxie/helper.c b/target-moxie/helper.c index ea0788f..b12e4ff 100644 --- a/target-moxie/helper.c +++ b/target-moxie/helper.c @@ -118,11 +118,6 @@ int cpu_moxie_handle_mmu_fault(CPUMoxieState *env, t= arget_ulong address, return 1; } =20 -hwaddr cpu_get_phys_page_debug(CPUState *env, target_ulong addr) -{ - return addr; -} - #else /* !CONFIG_USER_ONLY */ =20 int cpu_moxie_handle_mmu_fault(CPUMoxieState *env, target_ulong address, @@ -162,12 +157,14 @@ void moxie_cpu_do_interrupt(CPUState *cs) } } =20 -hwaddr cpu_get_phys_page_debug(CPUMoxieState *env, target_ulong addr) +hwaddr moxie_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { + MoxieCPU *cpu =3D MOXIE_CPU(cs); uint32_t phy =3D addr; MoxieMMUResult res; int miss; - miss =3D moxie_mmu_translate(&res, env, addr, 0, 0); + + miss =3D moxie_mmu_translate(&res, &cpu->env, addr, 0, 0); if (!miss) { phy =3D res.phy; } diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c index 27ee9f4..3da5a7a 100644 --- a/target-openrisc/cpu.c +++ b/target-openrisc/cpu.c @@ -154,7 +154,10 @@ static void openrisc_cpu_class_init(ObjectClass *oc,= void *data) cc->do_interrupt =3D openrisc_cpu_do_interrupt; cc->dump_state =3D openrisc_cpu_dump_state; cc->set_pc =3D openrisc_cpu_set_pc; - device_class_set_vmsd(dc, &vmstate_openrisc_cpu); +#ifndef CONFIG_USER_ONLY + cc->get_phys_page_debug =3D openrisc_cpu_get_phys_page_debug; + dc->vmsd =3D &vmstate_openrisc_cpu; +#endif } =20 static void cpu_register(const OpenRISCCPUInfo *info) diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h index 82bfd03..3ddb767 100644 --- a/target-openrisc/cpu.h +++ b/target-openrisc/cpu.h @@ -349,6 +349,7 @@ int cpu_openrisc_exec(CPUOpenRISCState *s); void openrisc_cpu_do_interrupt(CPUState *cpu); void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, int flags); +hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void openrisc_translate_init(void); int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env, target_ulong address, diff --git a/target-openrisc/mmu.c b/target-openrisc/mmu.c index d354e1f..57f5616 100644 --- a/target-openrisc/mmu.c +++ b/target-openrisc/mmu.c @@ -219,12 +219,11 @@ int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState = *env, #endif =20 #ifndef CONFIG_USER_ONLY -hwaddr cpu_get_phys_page_debug(CPUOpenRISCState *env, - target_ulong addr) +hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { + OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); hwaddr phys_addr; int prot; - OpenRISCCPU *cpu =3D openrisc_env_get_cpu(env); =20 if (cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, 0)) { return -1; diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h index 7132599..3341c51 100644 --- a/target-ppc/cpu-qom.h +++ b/target-ppc/cpu-qom.h @@ -105,5 +105,6 @@ void ppc_cpu_dump_state(CPUState *cpu, FILE *f, fprin= tf_function cpu_fprintf, int flags); void ppc_cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, int flags); +hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); =20 #endif diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index 77102c4..5dd4e05 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -1409,8 +1409,10 @@ static int get_physical_address(CPUPPCState *env, = mmu_ctx_t *ctx, return ret; } =20 -hwaddr cpu_get_phys_page_debug(CPUPPCState *env, target_ulong addr) +hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + CPUPPCState *env =3D &cpu->env; mmu_ctx_t ctx; =20 switch (env->mmu_model) { diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index ec47bc8..82fc463 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -8298,6 +8298,9 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->dump_state =3D ppc_cpu_dump_state; cc->dump_statistics =3D ppc_cpu_dump_statistics; cc->set_pc =3D ppc_cpu_set_pc; +#ifndef CONFIG_USER_ONLY + cc->get_phys_page_debug =3D ppc_cpu_get_phys_page_debug; +#endif } =20 static const TypeInfo ppc_cpu_type_info =3D { diff --git a/target-s390x/cpu-qom.h b/target-s390x/cpu-qom.h index 4c091e3..a4fe8fb 100644 --- a/target-s390x/cpu-qom.h +++ b/target-s390x/cpu-qom.h @@ -74,5 +74,6 @@ static inline S390CPU *s390_env_get_cpu(CPUS390XState *= env) void s390_cpu_do_interrupt(CPUState *cpu); void s390_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fp= rintf, int flags); +hwaddr s390_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); =20 #endif diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c index fe3cd8e..cb89d1a 100644 --- a/target-s390x/cpu.c +++ b/target-s390x/cpu.c @@ -173,6 +173,9 @@ static void s390_cpu_class_init(ObjectClass *oc, void= *data) cc->do_interrupt =3D s390_cpu_do_interrupt; cc->dump_state =3D s390_cpu_dump_state; cc->set_pc =3D s390_cpu_set_pc; +#ifndef CONFIG_USER_ONLY + cc->get_phys_page_debug =3D s390_cpu_get_phys_page_debug; +#endif dc->vmsd =3D &vmstate_s390_cpu; } =20 diff --git a/target-s390x/helper.c b/target-s390x/helper.c index b425054..61abfd7 100644 --- a/target-s390x/helper.c +++ b/target-s390x/helper.c @@ -417,9 +417,10 @@ int cpu_s390x_handle_mmu_fault(CPUS390XState *env, t= arget_ulong orig_vaddr, return 0; } =20 -hwaddr cpu_get_phys_page_debug(CPUS390XState *env, - target_ulong vaddr) +hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr) { + S390CPU *cpu =3D S390_CPU(cs); + CPUS390XState *env =3D &cpu->env; target_ulong raddr; int prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; int old_exc =3D env->exception_index; diff --git a/target-sh4/cpu-qom.h b/target-sh4/cpu-qom.h index c229a9a..7c9160b 100644 --- a/target-sh4/cpu-qom.h +++ b/target-sh4/cpu-qom.h @@ -86,5 +86,6 @@ static inline SuperHCPU *sh_env_get_cpu(CPUSH4State *en= v) void superh_cpu_do_interrupt(CPUState *cpu); void superh_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, int flags); +hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); =20 #endif diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c index 03dedc1..51a7757 100644 --- a/target-sh4/cpu.c +++ b/target-sh4/cpu.c @@ -286,6 +286,9 @@ static void superh_cpu_class_init(ObjectClass *oc, vo= id *data) cc->dump_state =3D superh_cpu_dump_state; cc->set_pc =3D superh_cpu_set_pc; cc->synchronize_from_tb =3D superh_cpu_synchronize_from_tb; +#ifndef CONFIG_USER_ONLY + cc->get_phys_page_debug =3D superh_cpu_get_phys_page_debug; +#endif dc->vmsd =3D &vmstate_sh_cpu; } =20 diff --git a/target-sh4/helper.c b/target-sh4/helper.c index cb6a2d2..9ac2825 100644 --- a/target-sh4/helper.c +++ b/target-sh4/helper.c @@ -508,12 +508,13 @@ int cpu_sh4_handle_mmu_fault(CPUSH4State * env, tar= get_ulong address, int rw, return 0; } =20 -hwaddr cpu_get_phys_page_debug(CPUSH4State * env, target_ulong addr) +hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { + SuperHCPU *cpu =3D SUPERH_CPU(cs); target_ulong physical; int prot; =20 - get_physical_address(env, &physical, &prot, addr, 0, 0); + get_physical_address(&cpu->env, &physical, &prot, addr, 0, 0); return physical; } =20 diff --git a/target-sparc/cpu-qom.h b/target-sparc/cpu-qom.h index 033a5b5..39d975b 100644 --- a/target-sparc/cpu-qom.h +++ b/target-sparc/cpu-qom.h @@ -78,5 +78,6 @@ static inline SPARCCPU *sparc_env_get_cpu(CPUSPARCState= *env) void sparc_cpu_do_interrupt(CPUState *cpu); void sparc_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, int flags); +hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); =20 #endif diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c index a2deba5..12494cc 100644 --- a/target-sparc/cpu.c +++ b/target-sparc/cpu.c @@ -782,9 +782,12 @@ static void sparc_cpu_class_init(ObjectClass *oc, vo= id *data) =20 cc->do_interrupt =3D sparc_cpu_do_interrupt; cc->dump_state =3D sparc_cpu_dump_state; - cpu_class_set_do_unassigned_access(cc, sparc_cpu_unassigned_access); cc->set_pc =3D sparc_cpu_set_pc; cc->synchronize_from_tb =3D sparc_cpu_synchronize_from_tb; +#ifndef CONFIG_USER_ONLY + cc->do_unassigned_access =3D sparc_cpu_unassigned_access; + cc->get_phys_page_debug =3D sparc_cpu_get_phys_page_debug; +#endif } =20 static const TypeInfo sparc_cpu_type_info =3D { diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c index 740cbe8..846d129 100644 --- a/target-sparc/mmu_helper.c +++ b/target-sparc/mmu_helper.c @@ -310,6 +310,7 @@ target_ulong mmu_probe(CPUSPARCState *env, target_ulo= ng address, int mmulev) =20 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env) { + CPUState *cs =3D CPU(sparc_env_get_cpu(env)); target_ulong va, va1, va2; unsigned int n, m, o; hwaddr pde_ptr, pa; @@ -322,20 +323,20 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf= , CPUSPARCState *env) for (n =3D 0, va =3D 0; n < 256; n++, va +=3D 16 * 1024 * 1024) { pde =3D mmu_probe(env, va, 2); if (pde) { - pa =3D cpu_get_phys_page_debug(env, va); + pa =3D cpu_get_phys_page_debug(cs, va); (*cpu_fprintf)(f, "VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_p= lx " PDE: " TARGET_FMT_lx "\n", va, pa, pde); for (m =3D 0, va1 =3D va; m < 64; m++, va1 +=3D 256 * 1024) = { pde =3D mmu_probe(env, va1, 1); if (pde) { - pa =3D cpu_get_phys_page_debug(env, va1); + pa =3D cpu_get_phys_page_debug(cs, va1); (*cpu_fprintf)(f, " VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx " PDE: " TARGET_FMT_lx= "\n", va1, pa, pde); for (o =3D 0, va2 =3D va1; o < 64; o++, va2 +=3D 4 *= 1024) { pde =3D mmu_probe(env, va2, 0); if (pde) { - pa =3D cpu_get_phys_page_debug(env, va2); + pa =3D cpu_get_phys_page_debug(cs, va2); (*cpu_fprintf)(f, " VA: " TARGET_FMT_lx ", = PA: " TARGET_FMT_plx " PTE: " TARGET_FMT_lx "\n", @@ -833,8 +834,10 @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env,= target_ulong addr, } #endif =20 -hwaddr cpu_get_phys_page_debug(CPUSPARCState *env, target_ulong addr) +hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { + SPARCCPU *cpu =3D SPARC_CPU(cs); + CPUSPARCState *env =3D &cpu->env; hwaddr phys_addr; int mmu_idx =3D cpu_mmu_index(env); MemoryRegionSection section; diff --git a/target-unicore32/cpu-qom.h b/target-unicore32/cpu-qom.h index 350d480..f727760 100644 --- a/target-unicore32/cpu-qom.h +++ b/target-unicore32/cpu-qom.h @@ -63,5 +63,6 @@ static inline UniCore32CPU *uc32_env_get_cpu(CPUUniCore= 32State *env) void uc32_cpu_do_interrupt(CPUState *cpu); void uc32_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, int flags); +hwaddr uc32_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); =20 #endif diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c index 79f2292..46813e5 100644 --- a/target-unicore32/cpu.c +++ b/target-unicore32/cpu.c @@ -139,6 +139,9 @@ static void uc32_cpu_class_init(ObjectClass *oc, void= *data) cc->do_interrupt =3D uc32_cpu_do_interrupt; cc->dump_state =3D uc32_cpu_dump_state; cc->set_pc =3D uc32_cpu_set_pc; +#ifndef CONFIG_USER_ONLY + cc->get_phys_page_debug =3D uc32_cpu_get_phys_page_debug; +#endif dc->vmsd =3D &vmstate_uc32_cpu; } =20 diff --git a/target-unicore32/softmmu.c b/target-unicore32/softmmu.c index eadaeb1..1e13a85 100644 --- a/target-unicore32/softmmu.c +++ b/target-unicore32/softmmu.c @@ -261,9 +261,10 @@ int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env= , target_ulong address, return ret; } =20 -hwaddr cpu_get_phys_page_debug(CPUUniCore32State *env, - target_ulong addr) +hwaddr uc32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { - cpu_abort(env, "%s not supported yet\n", __func__); + UniCore32CPU *cpu =3D UNICORE32_CPU(cs); + + cpu_abort(&cpu->env, "%s not supported yet\n", __func__); return addr; } diff --git a/target-xtensa/cpu-qom.h b/target-xtensa/cpu-qom.h index 31e7498..b9896f2 100644 --- a/target-xtensa/cpu-qom.h +++ b/target-xtensa/cpu-qom.h @@ -83,5 +83,6 @@ static inline XtensaCPU *xtensa_env_get_cpu(const CPUXt= ensaState *env) void xtensa_cpu_do_interrupt(CPUState *cpu); void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, int flags); +hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); =20 #endif diff --git a/target-xtensa/cpu.c b/target-xtensa/cpu.c index e3d742a..d2bcfc6 100644 --- a/target-xtensa/cpu.c +++ b/target-xtensa/cpu.c @@ -108,6 +108,9 @@ static void xtensa_cpu_class_init(ObjectClass *oc, vo= id *data) cc->do_interrupt =3D xtensa_cpu_do_interrupt; cc->dump_state =3D xtensa_cpu_dump_state; cc->set_pc =3D xtensa_cpu_set_pc; +#ifndef CONFIG_USER_ONLY + cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; +#endif dc->vmsd =3D &vmstate_xtensa_cpu; } =20 diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c index 6f613c66..de6cc3b 100644 --- a/target-xtensa/helper.c +++ b/target-xtensa/helper.c @@ -108,17 +108,18 @@ void xtensa_cpu_list(FILE *f, fprintf_function cpu_= fprintf) } } =20 -hwaddr cpu_get_phys_page_debug(CPUXtensaState *env, target_ulong addr) +hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { + XtensaCPU *cpu =3D XTENSA_CPU(cs); uint32_t paddr; uint32_t page_size; unsigned access; =20 - if (xtensa_get_physical_addr(env, false, addr, 0, 0, + if (xtensa_get_physical_addr(&cpu->env, false, addr, 0, 0, &paddr, &page_size, &access) =3D=3D 0) { return paddr; } - if (xtensa_get_physical_addr(env, false, addr, 2, 0, + if (xtensa_get_physical_addr(&cpu->env, false, addr, 2, 0, &paddr, &page_size, &access) =3D=3D 0) { return paddr; } diff --git a/target-xtensa/xtensa-semi.c b/target-xtensa/xtensa-semi.c index 5fe0361..d9dd222 100644 --- a/target-xtensa/xtensa-semi.c +++ b/target-xtensa/xtensa-semi.c @@ -152,6 +152,7 @@ static uint32_t errno_h2g(int host_errno) =20 void HELPER(simcall)(CPUXtensaState *env) { + CPUState *cs =3D CPU(xtensa_env_get_cpu(env)); uint32_t *regs =3D env->regs; =20 switch (regs[2]) { @@ -169,8 +170,7 @@ void HELPER(simcall)(CPUXtensaState *env) uint32_t len =3D regs[5]; =20 while (len > 0) { - hwaddr paddr =3D - cpu_get_phys_page_debug(env, vaddr); + hwaddr paddr =3D cpu_get_phys_page_debug(cs, vaddr); uint32_t page_left =3D TARGET_PAGE_SIZE - (vaddr & (TARGET_PAGE_SIZE - 1)); uint32_t io_sz =3D page_left < len ? page_left : len; --=20 1.8.1.4