From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37323) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Uxbdb-0000yB-7f for qemu-devel@nongnu.org; Fri, 12 Jul 2013 07:35:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Uxbda-0006PI-61 for qemu-devel@nongnu.org; Fri, 12 Jul 2013 07:35:47 -0400 Message-ID: <1373628932.19894.158.camel@pasglop> From: Benjamin Herrenschmidt Date: Fri, 12 Jul 2013 21:35:32 +1000 In-Reply-To: <02433CA4-954D-4C56-A4A4-7BC0D62638C0@suse.de> References: <51C75FA6.6080903@reactos.org> <51C7E21A.9090005@web.de> <8A36D64D-0625-49E1-9E59-391DAEEBD1FC@suse.de> <51DEA91B.40903@suse.de> <3FAA7DE1-06A0-45C5-885C-0433BCC0CFE8@suse.de> <5D205309-1154-4730-902E-BF07F5D3B4EB@suse.de> <1373581960.19894.109.camel@pasglop> <02433CA4-954D-4C56-A4A4-7BC0D62638C0@suse.de> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH v3 11/14] ioport: Switch dispatching to memory core layer List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf Cc: Liu Ping Fan , qemu-devel Developers , "qemu-ppc@nongnu.org list:PowerPC" , Paolo Bonzini , Jan Kiszka , Andreas =?ISO-8859-1?Q?F=E4rber?= , =?ISO-8859-1?Q?Herv=E9?= Poussineau On Fri, 2013-07-12 at 05:18 +0200, Alexander Graf wrote: > We model a single system wide io space today and access to that one > happens through you pci host controller. I just messed up the > terminology here. Single system wide IO space is broken. We have separate IO space per PHB. That was working afaik. In any case, I completely object to all that business with conversion in bridges. That's fundamentally WRONG. The whole business of endianness in qemu is a mess. In the end what matters and the only thing that does is: * The endianness of a given memory access by the guest (which may or may not be the endianness of the guest -> MSR:LE, byteswap load/store instsructions, etc..) vs. * The endianness of the target device register (and I say register ... a framebuffer does NOT have endianness per-se and thus accesses to BAR mapping a "memory" range (framebuffer, ROM, ...) should go such that the *byte order* of individual bytes is preserved, which typically means untranslated). Unless they are completely broken (and those exist, don't get me wrong, though mostly they are a thing of a past long gone), bridges and busses have no effect on endianness. So I'm not sure what you guys are up to, but from what I read, it's wrong, and the fact at this stage is that your broke IO space (and thus virtio and VGA) on powerpc (including pseries). Cheers, Ben.