From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37812) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V0uK6-0008Gw-Gw for qemu-devel@nongnu.org; Sun, 21 Jul 2013 10:09:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V0uK1-00053i-AS for qemu-devel@nongnu.org; Sun, 21 Jul 2013 10:09:18 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sun, 21 Jul 2013 16:09:01 +0200 Message-Id: <1374415744-6675-2-git-send-email-afaerber@suse.de> In-Reply-To: <1374415744-6675-1-git-send-email-afaerber@suse.de> References: <1374415744-6675-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH RFC qom-next 1/4] pci-bridge: Turn into abstract QOM type List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: "Michael S. Tsirkin" , "open list:New World" , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Alexander Graf Introduce TYPE_PCI_BRIDGE as base type and use PCI_BRIDGE() casts. Signed-off-by: Andreas F=C3=A4rber --- hw/pci-bridge/dec.c | 4 ++-- hw/pci-bridge/i82801b11.c | 6 +++--- hw/pci-bridge/ioh3420.c | 18 ++++++++--------- hw/pci-bridge/pci_bridge_dev.c | 10 +++++----- hw/pci-bridge/xio3130_downstream.c | 18 ++++++++--------- hw/pci-bridge/xio3130_upstream.c | 17 ++++++++-------- hw/pci-host/apb.c | 4 ++-- hw/pci/pci_bridge.c | 40 +++++++++++++++++++++++++++-----= ------ hw/pci/pcie.c | 2 +- include/hw/pci/pci_bus.h | 7 ++++++- 10 files changed, 75 insertions(+), 51 deletions(-) diff --git a/hw/pci-bridge/dec.c b/hw/pci-bridge/dec.c index efc07c4..e5e3be8 100644 --- a/hw/pci-bridge/dec.c +++ b/hw/pci-bridge/dec.c @@ -74,7 +74,7 @@ static void dec_21154_pci_bridge_class_init(ObjectClass= *klass, void *data) =20 static const TypeInfo dec_21154_pci_bridge_info =3D { .name =3D "dec-21154-p2p-bridge", - .parent =3D TYPE_PCI_DEVICE, + .parent =3D TYPE_PCI_BRIDGE, .instance_size =3D sizeof(PCIBridge), .class_init =3D dec_21154_pci_bridge_class_init, }; @@ -86,7 +86,7 @@ PCIBus *pci_dec_21154_init(PCIBus *parent_bus, int devf= n) =20 dev =3D pci_create_multifunction(parent_bus, devfn, false, "dec-21154-p2p-bridge"); - br =3D DO_UPCAST(PCIBridge, dev, dev); + br =3D PCI_BRIDGE(dev); pci_bridge_map_irq(br, "DEC 21154 PCI-PCI bridge", dec_map_irq); qdev_init_nofail(&dev->qdev); return pci_bridge_get_sec_bus(br); diff --git a/hw/pci-bridge/i82801b11.c b/hw/pci-bridge/i82801b11.c index b98bfb0..88f489a 100644 --- a/hw/pci-bridge/i82801b11.c +++ b/hw/pci-bridge/i82801b11.c @@ -91,7 +91,7 @@ static void i82801b11_bridge_class_init(ObjectClass *kl= ass, void *data) =20 static const TypeInfo i82801b11_bridge_info =3D { .name =3D "i82801b11-bridge", - .parent =3D TYPE_PCI_DEVICE, + .parent =3D TYPE_PCI_BRIDGE, .instance_size =3D sizeof(I82801b11Bridge), .class_init =3D i82801b11_bridge_class_init, }; @@ -107,8 +107,8 @@ PCIBus *ich9_d2pbr_init(PCIBus *bus, int devfn, int s= ec_bus) if (!d) { return NULL; } - br =3D DO_UPCAST(PCIBridge, dev, d); - qdev =3D &br->dev.qdev; + br =3D PCI_BRIDGE(d); + qdev =3D DEVICE(d); =20 snprintf(buf, sizeof(buf), "pci.%d", sec_bus); pci_bridge_map_irq(br, buf, pci_swizzle_map_irq_fn); diff --git a/hw/pci-bridge/ioh3420.c b/hw/pci-bridge/ioh3420.c index bb541eb..728f658 100644 --- a/hw/pci-bridge/ioh3420.c +++ b/hw/pci-bridge/ioh3420.c @@ -92,7 +92,7 @@ static void ioh3420_reset(DeviceState *qdev) =20 static int ioh3420_initfn(PCIDevice *d) { - PCIBridge* br =3D DO_UPCAST(PCIBridge, dev, d); + PCIBridge *br =3D PCI_BRIDGE(d); PCIEPort *p =3D DO_UPCAST(PCIEPort, br, br); PCIESlot *s =3D DO_UPCAST(PCIESlot, port, p); int rc; @@ -148,7 +148,7 @@ err_bridge: =20 static void ioh3420_exitfn(PCIDevice *d) { - PCIBridge* br =3D DO_UPCAST(PCIBridge, dev, d); + PCIBridge *br =3D PCI_BRIDGE(d); PCIEPort *p =3D DO_UPCAST(PCIEPort, br, br); PCIESlot *s =3D DO_UPCAST(PCIESlot, port, p); =20 @@ -171,9 +171,9 @@ PCIESlot *ioh3420_init(PCIBus *bus, int devfn, bool m= ultifunction, if (!d) { return NULL; } - br =3D DO_UPCAST(PCIBridge, dev, d); + br =3D PCI_BRIDGE(d); =20 - qdev =3D &br->dev.qdev; + qdev =3D DEVICE(d); pci_bridge_map_irq(br, bus_name, map_irq); qdev_prop_set_uint8(qdev, "port", port); qdev_prop_set_uint8(qdev, "chassis", chassis); @@ -190,8 +190,8 @@ static const VMStateDescription vmstate_ioh3420 =3D { .minimum_version_id_old =3D 1, .post_load =3D pcie_cap_slot_post_load, .fields =3D (VMStateField[]) { - VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot), - VMSTATE_STRUCT(port.br.dev.exp.aer_log, PCIESlot, 0, + VMSTATE_PCIE_DEVICE(port.br.parent_obj, PCIESlot), + VMSTATE_STRUCT(port.br.parent_obj.exp.aer_log, PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog), VMSTATE_END_OF_LIST() } @@ -202,8 +202,8 @@ static Property ioh3420_properties[] =3D { DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0), DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0), DEFINE_PROP_UINT16("aer_log_max", PCIESlot, - port.br.dev.exp.aer_log.log_max, - PCIE_AER_LOG_MAX_DEFAULT), + port.br.parent_obj.exp.aer_log.log_max, + PCIE_AER_LOG_MAX_DEFAULT), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -228,7 +228,7 @@ static void ioh3420_class_init(ObjectClass *klass, vo= id *data) =20 static const TypeInfo ioh3420_info =3D { .name =3D "ioh3420", - .parent =3D TYPE_PCI_DEVICE, + .parent =3D TYPE_PCI_BRIDGE, .instance_size =3D sizeof(PCIESlot), .class_init =3D ioh3420_class_init, }; diff --git a/hw/pci-bridge/pci_bridge_dev.c b/hw/pci-bridge/pci_bridge_de= v.c index 5f11323..00d2382 100644 --- a/hw/pci-bridge/pci_bridge_dev.c +++ b/hw/pci-bridge/pci_bridge_dev.c @@ -38,7 +38,7 @@ typedef struct PCIBridgeDev PCIBridgeDev; =20 static int pci_bridge_dev_initfn(PCIDevice *dev) { - PCIBridge *br =3D DO_UPCAST(PCIBridge, dev, dev); + PCIBridge *br =3D PCI_BRIDGE(dev); PCIBridgeDev *bridge_dev =3D DO_UPCAST(PCIBridgeDev, bridge, br); int err; =20 @@ -81,7 +81,7 @@ bridge_error: =20 static void pci_bridge_dev_exitfn(PCIDevice *dev) { - PCIBridge *br =3D DO_UPCAST(PCIBridge, dev, dev); + PCIBridge *br =3D PCI_BRIDGE(dev); PCIBridgeDev *bridge_dev =3D DO_UPCAST(PCIBridgeDev, bridge, br); if (msi_present(dev)) { msi_uninit(dev); @@ -120,8 +120,8 @@ static Property pci_bridge_dev_properties[] =3D { static const VMStateDescription pci_bridge_dev_vmstate =3D { .name =3D "pci_bridge", .fields =3D (VMStateField[]) { - VMSTATE_PCI_DEVICE(bridge.dev, PCIBridgeDev), - SHPC_VMSTATE(bridge.dev.shpc, PCIBridgeDev), + VMSTATE_PCI_DEVICE(bridge.parent_obj, PCIBridgeDev), + SHPC_VMSTATE(bridge.parent_obj.shpc, PCIBridgeDev), VMSTATE_END_OF_LIST() } }; @@ -145,7 +145,7 @@ static void pci_bridge_dev_class_init(ObjectClass *kl= ass, void *data) =20 static const TypeInfo pci_bridge_dev_info =3D { .name =3D "pci-bridge", - .parent =3D TYPE_PCI_DEVICE, + .parent =3D TYPE_PCI_BRIDGE, .instance_size =3D sizeof(PCIBridgeDev), .class_init =3D pci_bridge_dev_class_init, }; diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_d= ownstream.c index 1810dd2..9acce3f 100644 --- a/hw/pci-bridge/xio3130_downstream.c +++ b/hw/pci-bridge/xio3130_downstream.c @@ -56,7 +56,7 @@ static void xio3130_downstream_reset(DeviceState *qdev) =20 static int xio3130_downstream_initfn(PCIDevice *d) { - PCIBridge* br =3D DO_UPCAST(PCIBridge, dev, d); + PCIBridge *br =3D PCI_BRIDGE(d); PCIEPort *p =3D DO_UPCAST(PCIEPort, br, br); PCIESlot *s =3D DO_UPCAST(PCIESlot, port, p); int rc; @@ -113,7 +113,7 @@ err_bridge: =20 static void xio3130_downstream_exitfn(PCIDevice *d) { - PCIBridge* br =3D DO_UPCAST(PCIBridge, dev, d); + PCIBridge *br =3D PCI_BRIDGE(d); PCIEPort *p =3D DO_UPCAST(PCIEPort, br, br); PCIESlot *s =3D DO_UPCAST(PCIESlot, port, p); =20 @@ -138,9 +138,9 @@ PCIESlot *xio3130_downstream_init(PCIBus *bus, int de= vfn, bool multifunction, if (!d) { return NULL; } - br =3D DO_UPCAST(PCIBridge, dev, d); + br =3D PCI_BRIDGE(d); =20 - qdev =3D &br->dev.qdev; + qdev =3D DEVICE(d); pci_bridge_map_irq(br, bus_name, map_irq); qdev_prop_set_uint8(qdev, "port", port); qdev_prop_set_uint8(qdev, "chassis", chassis); @@ -157,8 +157,8 @@ static const VMStateDescription vmstate_xio3130_downs= tream =3D { .minimum_version_id_old =3D 1, .post_load =3D pcie_cap_slot_post_load, .fields =3D (VMStateField[]) { - VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot), - VMSTATE_STRUCT(port.br.dev.exp.aer_log, PCIESlot, 0, + VMSTATE_PCIE_DEVICE(port.br.parent_obj, PCIESlot), + VMSTATE_STRUCT(port.br.parent_obj.exp.aer_log, PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog), VMSTATE_END_OF_LIST() } @@ -169,8 +169,8 @@ static Property xio3130_downstream_properties[] =3D { DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0), DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0), DEFINE_PROP_UINT16("aer_log_max", PCIESlot, - port.br.dev.exp.aer_log.log_max, - PCIE_AER_LOG_MAX_DEFAULT), + port.br.parent_obj.exp.aer_log.log_max, + PCIE_AER_LOG_MAX_DEFAULT), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -195,7 +195,7 @@ static void xio3130_downstream_class_init(ObjectClass= *klass, void *data) =20 static const TypeInfo xio3130_downstream_info =3D { .name =3D "xio3130-downstream", - .parent =3D TYPE_PCI_DEVICE, + .parent =3D TYPE_PCI_BRIDGE, .instance_size =3D sizeof(PCIESlot), .class_init =3D xio3130_downstream_class_init, }; diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_ups= tream.c index 8e0d97a..6bbcf98 100644 --- a/hw/pci-bridge/xio3130_upstream.c +++ b/hw/pci-bridge/xio3130_upstream.c @@ -53,7 +53,7 @@ static void xio3130_upstream_reset(DeviceState *qdev) =20 static int xio3130_upstream_initfn(PCIDevice *d) { - PCIBridge* br =3D DO_UPCAST(PCIBridge, dev, d); + PCIBridge *br =3D PCI_BRIDGE(d); PCIEPort *p =3D DO_UPCAST(PCIEPort, br, br); int rc; =20 @@ -118,9 +118,9 @@ PCIEPort *xio3130_upstream_init(PCIBus *bus, int devf= n, bool multifunction, if (!d) { return NULL; } - br =3D DO_UPCAST(PCIBridge, dev, d); + br =3D PCI_BRIDGE(d); =20 - qdev =3D &br->dev.qdev; + qdev =3D DEVICE(d); pci_bridge_map_irq(br, bus_name, map_irq); qdev_prop_set_uint8(qdev, "port", port); qdev_init_nofail(qdev); @@ -134,16 +134,17 @@ static const VMStateDescription vmstate_xio3130_ups= tream =3D { .minimum_version_id =3D 1, .minimum_version_id_old =3D 1, .fields =3D (VMStateField[]) { - VMSTATE_PCIE_DEVICE(br.dev, PCIEPort), - VMSTATE_STRUCT(br.dev.exp.aer_log, PCIEPort, 0, vmstate_pcie_aer= _log, - PCIEAERLog), + VMSTATE_PCIE_DEVICE(br.parent_obj, PCIEPort), + VMSTATE_STRUCT(br.parent_obj.exp.aer_log, PCIEPort, 0, + vmstate_pcie_aer_log, PCIEAERLog), VMSTATE_END_OF_LIST() } }; =20 static Property xio3130_upstream_properties[] =3D { DEFINE_PROP_UINT8("port", PCIEPort, port, 0), - DEFINE_PROP_UINT16("aer_log_max", PCIEPort, br.dev.exp.aer_log.log_m= ax, + DEFINE_PROP_UINT16("aer_log_max", PCIEPort, + br.parent_obj.exp.aer_log.log_max, PCIE_AER_LOG_MAX_DEFAULT), DEFINE_PROP_END_OF_LIST(), }; @@ -169,7 +170,7 @@ static void xio3130_upstream_class_init(ObjectClass *= klass, void *data) =20 static const TypeInfo xio3130_upstream_info =3D { .name =3D "x3130-upstream", - .parent =3D TYPE_PCI_DEVICE, + .parent =3D TYPE_PCI_BRIDGE, .instance_size =3D sizeof(PCIEPort), .class_init =3D xio3130_upstream_class_init, }; diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c index 06ace08..0277aa0 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/apb.c @@ -464,7 +464,7 @@ PCIBus *pci_apb_init(hwaddr special_base, /* APB secondary busses */ pci_dev =3D pci_create_multifunction(d->bus, PCI_DEVFN(1, 0), true, "pbm-bridge"); - br =3D DO_UPCAST(PCIBridge, dev, pci_dev); + br =3D PCI_BRIDGE(pci_dev); pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 1", pci_apb_map_irq); qdev_init_nofail(&pci_dev->qdev); @@ -472,7 +472,7 @@ PCIBus *pci_apb_init(hwaddr special_base, =20 pci_dev =3D pci_create_multifunction(d->bus, PCI_DEVFN(1, 1), true, "pbm-bridge"); - br =3D DO_UPCAST(PCIBridge, dev, pci_dev); + br =3D PCI_BRIDGE(pci_dev); pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 2", pci_apb_map_irq); qdev_init_nofail(&pci_dev->qdev); diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c index 02a396b..a90671d 100644 --- a/hw/pci/pci_bridge.c +++ b/hw/pci/pci_bridge.c @@ -141,8 +141,9 @@ static void pci_bridge_init_alias(PCIBridge *bridge, = MemoryRegion *alias, MemoryRegion *parent_space, bool enabled) { - pcibus_t base =3D pci_bridge_get_base(&bridge->dev, type); - pcibus_t limit =3D pci_bridge_get_limit(&bridge->dev, type); + PCIDevice *bridge_dev =3D PCI_DEVICE(bridge); + pcibus_t base =3D pci_bridge_get_base(bridge_dev, type); + pcibus_t limit =3D pci_bridge_get_limit(bridge_dev, type); /* TODO: this doesn't handle base =3D 0 limit =3D 2^64 - 1 correctly= . * Apparently no way to do this with existing memory APIs. */ pcibus_t size =3D enabled && limit >=3D base ? limit + 1 - base : 0; @@ -154,7 +155,8 @@ static void pci_bridge_init_alias(PCIBridge *bridge, = MemoryRegion *alias, static void pci_bridge_init_vga_aliases(PCIBridge *br, PCIBus *parent, MemoryRegion *alias_vga) { - uint16_t brctl =3D pci_get_word(br->dev.config + PCI_BRIDGE_CONTROL)= ; + PCIDevice *pd =3D PCI_DEVICE(br); + uint16_t brctl =3D pci_get_word(pd->config + PCI_BRIDGE_CONTROL); =20 memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_LO], OBJECT(br), "pci_bridge_vga_io_lo", &br->address_space_= io, @@ -167,7 +169,7 @@ static void pci_bridge_init_vga_aliases(PCIBridge *br= , PCIBus *parent, QEMU_PCI_VGA_MEM_BASE, QEMU_PCI_VGA_MEM_SIZ= E); =20 if (brctl & PCI_BRIDGE_CTL_VGA) { - pci_register_vga(&br->dev, &alias_vga[QEMU_PCI_VGA_MEM], + pci_register_vga(pd, &alias_vga[QEMU_PCI_VGA_MEM], &alias_vga[QEMU_PCI_VGA_IO_LO], &alias_vga[QEMU_PCI_VGA_IO_HI]); } @@ -175,9 +177,10 @@ static void pci_bridge_init_vga_aliases(PCIBridge *b= r, PCIBus *parent, =20 static PCIBridgeWindows *pci_bridge_region_init(PCIBridge *br) { - PCIBus *parent =3D br->dev.bus; + PCIDevice *pd =3D PCI_DEVICE(br); + PCIBus *parent =3D pd->bus; PCIBridgeWindows *w =3D g_new(PCIBridgeWindows, 1); - uint16_t cmd =3D pci_get_word(br->dev.config + PCI_COMMAND); + uint16_t cmd =3D pci_get_word(pd->config + PCI_COMMAND); =20 pci_bridge_init_alias(br, &w->alias_pref_mem, PCI_BASE_ADDRESS_MEM_PREFETCH, @@ -205,12 +208,13 @@ static PCIBridgeWindows *pci_bridge_region_init(PCI= Bridge *br) =20 static void pci_bridge_region_del(PCIBridge *br, PCIBridgeWindows *w) { - PCIBus *parent =3D br->dev.bus; + PCIDevice *pd =3D PCI_DEVICE(br); + PCIBus *parent =3D pd->bus; =20 memory_region_del_subregion(parent->address_space_io, &w->alias_io); memory_region_del_subregion(parent->address_space_mem, &w->alias_mem= ); memory_region_del_subregion(parent->address_space_mem, &w->alias_pre= f_mem); - pci_unregister_vga(&br->dev); + pci_unregister_vga(pd); } =20 static void pci_bridge_region_cleanup(PCIBridge *br, PCIBridgeWindows *w= ) @@ -241,7 +245,7 @@ void pci_bridge_update_mappings(PCIBridge *br) void pci_bridge_write_config(PCIDevice *d, uint32_t address, uint32_t val, int len) { - PCIBridge *s =3D container_of(d, PCIBridge, dev); + PCIBridge *s =3D PCI_BRIDGE(d); uint16_t oldctl =3D pci_get_word(d->config + PCI_BRIDGE_CONTROL); uint16_t newctl; =20 @@ -331,7 +335,7 @@ void pci_bridge_reset(DeviceState *qdev) int pci_bridge_initfn(PCIDevice *dev, const char *typename) { PCIBus *parent =3D dev->bus; - PCIBridge *br =3D DO_UPCAST(PCIBridge, dev, dev); + PCIBridge *br =3D PCI_BRIDGE(dev); PCIBus *sec_bus =3D &br->sec_bus; =20 pci_word_test_and_set_mask(dev->config + PCI_STATUS, @@ -379,7 +383,7 @@ int pci_bridge_initfn(PCIDevice *dev, const char *typ= ename) /* default qdev clean up function for PCI-to-PCI bridge */ void pci_bridge_exitfn(PCIDevice *pci_dev) { - PCIBridge *s =3D DO_UPCAST(PCIBridge, dev, pci_dev); + PCIBridge *s =3D PCI_BRIDGE(pci_dev); assert(QLIST_EMPTY(&s->sec_bus.child)); QLIST_REMOVE(&s->sec_bus, sibling); pci_bridge_region_del(s, s->windows); @@ -400,3 +404,17 @@ void pci_bridge_map_irq(PCIBridge *br, const char* b= us_name, br->map_irq =3D map_irq; br->bus_name =3D bus_name; } + +static const TypeInfo pci_bridge_type_info =3D { + .name =3D TYPE_PCI_BRIDGE, + .parent =3D TYPE_PCI_DEVICE, + .instance_size =3D sizeof(PCIBridge), + .abstract =3D true, +}; + +static void pci_bridge_register_types(void) +{ + type_register_static(&pci_bridge_type_info); +} + +type_init(pci_bridge_register_types) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 62bd0b8..50af3c1 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -305,7 +305,7 @@ void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot= ) =20 dev->exp.hpev_notified =3D false; =20 - pci_bus_hotplug(pci_bridge_get_sec_bus(DO_UPCAST(PCIBridge, dev, dev= )), + pci_bus_hotplug(pci_bridge_get_sec_bus(PCI_BRIDGE(dev)), pcie_cap_slot_hotplug, &dev->qdev); } =20 diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bus.h index 66762f6..9df1788 100644 --- a/include/hw/pci/pci_bus.h +++ b/include/hw/pci/pci_bus.h @@ -53,8 +53,13 @@ struct PCIBridgeWindows { MemoryRegion alias_vga[QEMU_PCI_VGA_NUM_REGIONS]; }; =20 +#define TYPE_PCI_BRIDGE "base-pci-bridge" +#define PCI_BRIDGE(obj) OBJECT_CHECK(PCIBridge, (obj), TYPE_PCI_BRIDGE) + struct PCIBridge { - PCIDevice dev; + /*< private >*/ + PCIDevice parent_obj; + /*< public >*/ =20 /* private member */ PCIBus sec_bus; --=20 1.8.1.4