diff for duplicates of <1374564028-11352-12-git-send-email-t-kristo@ti.com>
diff --git a/a/1.txt b/N1/1.txt
index bdc20f9..03dab64 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -29,7 +29,7 @@ index 0000000..391edee
+ clock-frequency = <12000000>;
+};
+
-+pad_clks_ck: pad_clks_ck@4a004108 {
++pad_clks_ck: pad_clks_ck at 4a004108 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&pad_clks_src_ck>;
@@ -49,7 +49,7 @@ index 0000000..391edee
+ clock-frequency = <12000000>;
+};
+
-+slimbus_clk: slimbus_clk@4a004108 {
++slimbus_clk: slimbus_clk at 4a004108 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&slimbus_src_clk>;
@@ -105,7 +105,7 @@ index 0000000..391edee
+ clock-frequency = <38400000>;
+};
+
-+sys_clkin: sys_clkin@4ae06110 {
++sys_clkin: sys_clkin at 4ae06110 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
@@ -126,7 +126,7 @@ index 0000000..391edee
+ clock-frequency = <60000000>;
+};
+
-+abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@4ae06108 {
++abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux at 4ae06108 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
@@ -134,7 +134,7 @@ index 0000000..391edee
+ bit-mask = <0x1>;
+};
+
-+abe_dpll_clk_mux: abe_dpll_clk_mux@4ae0610c {
++abe_dpll_clk_mux: abe_dpll_clk_mux at 4ae0610c {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
@@ -142,7 +142,7 @@ index 0000000..391edee
+ bit-mask = <0x1>;
+};
+
-+dpll_abe_ck: dpll_abe_ck@4a0041e0 {
++dpll_abe_ck: dpll_abe_ck at 4a0041e0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
@@ -159,7 +159,7 @@ index 0000000..391edee
+ ti,dpll-clk-x2;
+};
+
-+dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@4a0041f0 {
++dpll_abe_m2x2_ck: dpll_abe_m2x2_ck at 4a0041f0 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_abe_x2_ck>;
@@ -178,7 +178,7 @@ index 0000000..391edee
+ clock-div = <8>;
+};
+
-+abe_clk: abe_clk@4a004108 {
++abe_clk: abe_clk at 4a004108 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
@@ -203,7 +203,7 @@ index 0000000..391edee
+ clock-div = <16>;
+};
+
-+dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@4a0041f4 {
++dpll_abe_m3x2_ck: dpll_abe_m3x2_ck at 4a0041f4 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_abe_x2_ck>;
@@ -214,7 +214,7 @@ index 0000000..391edee
+ ti,autoidle-low;
+};
+
-+dpll_core_ck: dpll_core_ck@4a004120 {
++dpll_core_ck: dpll_core_ck at 4a004120 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
@@ -231,7 +231,7 @@ index 0000000..391edee
+ ti,dpll-clk-x2;
+};
+
-+dpll_core_h21x2_ck: dpll_core_h21x2_ck@4a004150 {
++dpll_core_h21x2_ck: dpll_core_h21x2_ck at 4a004150 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_core_x2_ck>;
@@ -266,7 +266,7 @@ index 0000000..391edee
+ clock-div = <2>;
+};
+
-+dpll_core_h11x2_ck: dpll_core_h11x2_ck@4a004138 {
++dpll_core_h11x2_ck: dpll_core_h11x2_ck at 4a004138 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_core_x2_ck>;
@@ -277,7 +277,7 @@ index 0000000..391edee
+ ti,autoidle-low;
+};
+
-+dpll_core_h12x2_ck: dpll_core_h12x2_ck@4a00413c {
++dpll_core_h12x2_ck: dpll_core_h12x2_ck at 4a00413c {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_core_x2_ck>;
@@ -288,7 +288,7 @@ index 0000000..391edee
+ ti,autoidle-low;
+};
+
-+dpll_core_h13x2_ck: dpll_core_h13x2_ck@4a004140 {
++dpll_core_h13x2_ck: dpll_core_h13x2_ck at 4a004140 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_core_x2_ck>;
@@ -299,7 +299,7 @@ index 0000000..391edee
+ ti,autoidle-low;
+};
+
-+dpll_core_h14x2_ck: dpll_core_h14x2_ck@4a004144 {
++dpll_core_h14x2_ck: dpll_core_h14x2_ck at 4a004144 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_core_x2_ck>;
@@ -310,7 +310,7 @@ index 0000000..391edee
+ ti,autoidle-low;
+};
+
-+dpll_core_h22x2_ck: dpll_core_h22x2_ck@4a004154 {
++dpll_core_h22x2_ck: dpll_core_h22x2_ck at 4a004154 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_core_x2_ck>;
@@ -321,7 +321,7 @@ index 0000000..391edee
+ ti,autoidle-low;
+};
+
-+dpll_core_h23x2_ck: dpll_core_h23x2_ck@4a004158 {
++dpll_core_h23x2_ck: dpll_core_h23x2_ck at 4a004158 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_core_x2_ck>;
@@ -332,7 +332,7 @@ index 0000000..391edee
+ ti,autoidle-low;
+};
+
-+dpll_core_h24x2_ck: dpll_core_h24x2_ck@4a00415c {
++dpll_core_h24x2_ck: dpll_core_h24x2_ck at 4a00415c {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_core_x2_ck>;
@@ -343,7 +343,7 @@ index 0000000..391edee
+ ti,autoidle-low;
+};
+
-+dpll_core_m2_ck: dpll_core_m2_ck@4a004130 {
++dpll_core_m2_ck: dpll_core_m2_ck at 4a004130 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_core_ck>;
@@ -354,7 +354,7 @@ index 0000000..391edee
+ ti,autoidle-low;
+};
+
-+dpll_core_m3x2_ck: dpll_core_m3x2_ck@4a004134 {
++dpll_core_m3x2_ck: dpll_core_m3x2_ck at 4a004134 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_core_x2_ck>;
@@ -373,7 +373,7 @@ index 0000000..391edee
+ clock-div = <1>;
+};
+
-+dpll_iva_ck: dpll_iva_ck@4a0041a0 {
++dpll_iva_ck: dpll_iva_ck at 4a0041a0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
@@ -389,7 +389,7 @@ index 0000000..391edee
+ ti,dpll-clk-x2;
+};
+
-+dpll_iva_h11x2_ck: dpll_iva_h11x2_ck@4a0041b8 {
++dpll_iva_h11x2_ck: dpll_iva_h11x2_ck at 4a0041b8 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_iva_x2_ck>;
@@ -400,7 +400,7 @@ index 0000000..391edee
+ ti,autoidle-low;
+};
+
-+dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@4a0041bc {
++dpll_iva_h12x2_ck: dpll_iva_h12x2_ck at 4a0041bc {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_iva_x2_ck>;
@@ -419,7 +419,7 @@ index 0000000..391edee
+ clock-div = <1>;
+};
+
-+dpll_mpu_ck: dpll_mpu_ck@4a004160 {
++dpll_mpu_ck: dpll_mpu_ck at 4a004160 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>;
@@ -428,7 +428,7 @@ index 0000000..391edee
+ ti,clk-bypass = <&mpu_dpll_hs_clk_div>;
+};
+
-+dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a004170 {
++dpll_mpu_m2_ck: dpll_mpu_m2_ck at 4a004170 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_mpu_ck>;
@@ -447,7 +447,7 @@ index 0000000..391edee
+ clock-div = <2>;
+};
+
-+dpll_per_ck: dpll_per_ck@4a008140 {
++dpll_per_ck: dpll_per_ck at 4a008140 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
@@ -463,7 +463,7 @@ index 0000000..391edee
+ ti,dpll-clk-x2;
+};
+
-+dpll_per_h11x2_ck: dpll_per_h11x2_ck@4a008158 {
++dpll_per_h11x2_ck: dpll_per_h11x2_ck at 4a008158 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_per_x2_ck>;
@@ -474,7 +474,7 @@ index 0000000..391edee
+ ti,autoidle-low;
+};
+
-+dpll_per_h12x2_ck: dpll_per_h12x2_ck@4a00815c {
++dpll_per_h12x2_ck: dpll_per_h12x2_ck at 4a00815c {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_per_x2_ck>;
@@ -485,7 +485,7 @@ index 0000000..391edee
+ ti,autoidle-low;
+};
+
-+dpll_per_h14x2_ck: dpll_per_h14x2_ck@4a008164 {
++dpll_per_h14x2_ck: dpll_per_h14x2_ck at 4a008164 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_per_x2_ck>;
@@ -496,7 +496,7 @@ index 0000000..391edee
+ ti,autoidle-low;
+};
+
-+dpll_per_m2_ck: dpll_per_m2_ck@4a008150 {
++dpll_per_m2_ck: dpll_per_m2_ck at 4a008150 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_per_ck>;
@@ -507,7 +507,7 @@ index 0000000..391edee
+ ti,autoidle-low;
+};
+
-+dpll_per_m2x2_ck: dpll_per_m2x2_ck@4a008150 {
++dpll_per_m2x2_ck: dpll_per_m2x2_ck at 4a008150 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_per_x2_ck>;
@@ -518,7 +518,7 @@ index 0000000..391edee
+ ti,autoidle-low;
+};
+
-+dpll_per_m3x2_ck: dpll_per_m3x2_ck@4a008154 {
++dpll_per_m3x2_ck: dpll_per_m3x2_ck at 4a008154 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_per_x2_ck>;
@@ -529,7 +529,7 @@ index 0000000..391edee
+ ti,autoidle-low;
+};
+
-+dpll_unipro1_ck: dpll_unipro1_ck@4a008200 {
++dpll_unipro1_ck: dpll_unipro1_ck at 4a008200 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin>;
@@ -546,7 +546,7 @@ index 0000000..391edee
+ clock-div = <1>;
+};
+
-+dpll_unipro1_m2_ck: dpll_unipro1_m2_ck@4a008210 {
++dpll_unipro1_m2_ck: dpll_unipro1_m2_ck at 4a008210 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_unipro1_ck>;
@@ -557,7 +557,7 @@ index 0000000..391edee
+ ti,autoidle-low;
+};
+
-+dpll_unipro2_ck: dpll_unipro2_ck@4a0081c0 {
++dpll_unipro2_ck: dpll_unipro2_ck at 4a0081c0 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin>;
@@ -574,7 +574,7 @@ index 0000000..391edee
+ clock-div = <1>;
+};
+
-+dpll_unipro2_m2_ck: dpll_unipro2_m2_ck@4a0081d0 {
++dpll_unipro2_m2_ck: dpll_unipro2_m2_ck at 4a0081d0 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_unipro2_ck>;
@@ -593,7 +593,7 @@ index 0000000..391edee
+ clock-div = <3>;
+};
+
-+dpll_usb_ck: dpll_usb_ck@4a008180 {
++dpll_usb_ck: dpll_usb_ck at 4a008180 {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
@@ -612,7 +612,7 @@ index 0000000..391edee
+ clock-div = <1>;
+};
+
-+dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 {
++dpll_usb_m2_ck: dpll_usb_m2_ck at 4a008190 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_usb_ck>;
@@ -687,7 +687,7 @@ index 0000000..391edee
+ clock-div = <1>;
+};
+
-+l3init_60m_fclk: l3init_60m_fclk@4a008104 {
++l3init_60m_fclk: l3init_60m_fclk at 4a008104 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_usb_m2_ck>;
@@ -696,7 +696,7 @@ index 0000000..391edee
+ bit-mask = <0x1>;
+};
+
-+wkupaon_iclk_mux: wkupaon_iclk_mux@4ae06108 {
++wkupaon_iclk_mux: wkupaon_iclk_mux at 4ae06108 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin>, <&abe_lp_clk_div>;
@@ -720,7 +720,7 @@ index 0000000..391edee
+ clock-div = <1>;
+};
+
-+dss_32khz_clk: dss_32khz_clk@4a009420 {
++dss_32khz_clk: dss_32khz_clk at 4a009420 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
@@ -728,7 +728,7 @@ index 0000000..391edee
+ reg = <0x4a009420 0x4>;
+};
+
-+dss_48mhz_clk: dss_48mhz_clk@4a009420 {
++dss_48mhz_clk: dss_48mhz_clk at 4a009420 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&func_48m_fclk>;
@@ -736,7 +736,7 @@ index 0000000..391edee
+ reg = <0x4a009420 0x4>;
+};
+
-+dss_dss_clk: dss_dss_clk@4a009420 {
++dss_dss_clk: dss_dss_clk at 4a009420 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll_per_h12x2_ck>;
@@ -744,7 +744,7 @@ index 0000000..391edee
+ reg = <0x4a009420 0x4>;
+};
+
-+dss_sys_clk: dss_sys_clk@4a009420 {
++dss_sys_clk: dss_sys_clk at 4a009420 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dss_syc_gfclk_div>;
@@ -752,7 +752,7 @@ index 0000000..391edee
+ reg = <0x4a009420 0x4>;
+};
+
-+gpio1_dbclk: gpio1_dbclk@4ae07938 {
++gpio1_dbclk: gpio1_dbclk at 4ae07938 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
@@ -760,7 +760,7 @@ index 0000000..391edee
+ reg = <0x4ae07938 0x4>;
+};
+
-+gpio2_dbclk: gpio2_dbclk@4a009060 {
++gpio2_dbclk: gpio2_dbclk at 4a009060 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
@@ -768,7 +768,7 @@ index 0000000..391edee
+ reg = <0x4a009060 0x4>;
+};
+
-+gpio3_dbclk: gpio3_dbclk@4a009068 {
++gpio3_dbclk: gpio3_dbclk at 4a009068 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
@@ -776,7 +776,7 @@ index 0000000..391edee
+ reg = <0x4a009068 0x4>;
+};
+
-+gpio4_dbclk: gpio4_dbclk@4a009070 {
++gpio4_dbclk: gpio4_dbclk at 4a009070 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
@@ -784,7 +784,7 @@ index 0000000..391edee
+ reg = <0x4a009070 0x4>;
+};
+
-+gpio5_dbclk: gpio5_dbclk@4a009078 {
++gpio5_dbclk: gpio5_dbclk at 4a009078 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
@@ -792,7 +792,7 @@ index 0000000..391edee
+ reg = <0x4a009078 0x4>;
+};
+
-+gpio6_dbclk: gpio6_dbclk@4a009080 {
++gpio6_dbclk: gpio6_dbclk at 4a009080 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
@@ -800,7 +800,7 @@ index 0000000..391edee
+ reg = <0x4a009080 0x4>;
+};
+
-+gpio7_dbclk: gpio7_dbclk@4a009110 {
++gpio7_dbclk: gpio7_dbclk at 4a009110 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
@@ -808,7 +808,7 @@ index 0000000..391edee
+ reg = <0x4a009110 0x4>;
+};
+
-+gpio8_dbclk: gpio8_dbclk@4a009118 {
++gpio8_dbclk: gpio8_dbclk at 4a009118 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
@@ -816,7 +816,7 @@ index 0000000..391edee
+ reg = <0x4a009118 0x4>;
+};
+
-+iss_ctrlclk: iss_ctrlclk@4a009320 {
++iss_ctrlclk: iss_ctrlclk at 4a009320 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&func_96m_fclk>;
@@ -824,7 +824,7 @@ index 0000000..391edee
+ reg = <0x4a009320 0x4>;
+};
+
-+lli_txphy_clk: lli_txphy_clk@4a008f20 {
++lli_txphy_clk: lli_txphy_clk at 4a008f20 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll_unipro1_clkdcoldo>;
@@ -832,7 +832,7 @@ index 0000000..391edee
+ reg = <0x4a008f20 0x4>;
+};
+
-+lli_txphy_ls_clk: lli_txphy_ls_clk@4a008f20 {
++lli_txphy_ls_clk: lli_txphy_ls_clk at 4a008f20 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll_unipro1_m2_ck>;
@@ -840,7 +840,7 @@ index 0000000..391edee
+ reg = <0x4a008f20 0x4>;
+};
+
-+mmc1_32khz_clk: mmc1_32khz_clk@4a009628 {
++mmc1_32khz_clk: mmc1_32khz_clk at 4a009628 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
@@ -848,7 +848,7 @@ index 0000000..391edee
+ reg = <0x4a009628 0x4>;
+};
+
-+sata_ref_clk: sata_ref_clk@4a009688 {
++sata_ref_clk: sata_ref_clk at 4a009688 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_clkin>;
@@ -856,7 +856,7 @@ index 0000000..391edee
+ reg = <0x4a009688 0x4>;
+};
+
-+slimbus1_slimbus_clk: slimbus1_slimbus_clk@4a004560 {
++slimbus1_slimbus_clk: slimbus1_slimbus_clk at 4a004560 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&slimbus_clk>;
@@ -864,7 +864,7 @@ index 0000000..391edee
+ reg = <0x4a004560 0x4>;
+};
+
-+usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk@4a009658 {
++usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk at 4a009658 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll_usb_m2_ck>;
@@ -872,7 +872,7 @@ index 0000000..391edee
+ reg = <0x4a009658 0x4>;
+};
+
-+usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk@4a009658 {
++usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk at 4a009658 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll_usb_m2_ck>;
@@ -880,7 +880,7 @@ index 0000000..391edee
+ reg = <0x4a009658 0x4>;
+};
+
-+usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk@4a009658 {
++usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk at 4a009658 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll_usb_m2_ck>;
@@ -888,7 +888,7 @@ index 0000000..391edee
+ reg = <0x4a009658 0x4>;
+};
+
-+usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk@4a009658 {
++usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk at 4a009658 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&l3init_60m_fclk>;
@@ -896,7 +896,7 @@ index 0000000..391edee
+ reg = <0x4a009658 0x4>;
+};
+
-+usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk@4a009658 {
++usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk at 4a009658 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&l3init_60m_fclk>;
@@ -904,7 +904,7 @@ index 0000000..391edee
+ reg = <0x4a009658 0x4>;
+};
+
-+usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk@4a009658 {
++usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk at 4a009658 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&l3init_60m_fclk>;
@@ -912,7 +912,7 @@ index 0000000..391edee
+ reg = <0x4a009658 0x4>;
+};
+
-+utmi_p1_gfclk: utmi_p1_gfclk@4a009658 {
++utmi_p1_gfclk: utmi_p1_gfclk at 4a009658 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&l3init_60m_fclk>, <&xclk60mhsp1_ck>;
@@ -921,7 +921,7 @@ index 0000000..391edee
+ bit-mask = <0x1>;
+};
+
-+usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk@4a009658 {
++usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk at 4a009658 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&utmi_p1_gfclk>;
@@ -929,7 +929,7 @@ index 0000000..391edee
+ reg = <0x4a009658 0x4>;
+};
+
-+utmi_p2_gfclk: utmi_p2_gfclk@4a009658 {
++utmi_p2_gfclk: utmi_p2_gfclk at 4a009658 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&l3init_60m_fclk>, <&xclk60mhsp2_ck>;
@@ -938,7 +938,7 @@ index 0000000..391edee
+ bit-mask = <0x1>;
+};
+
-+usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk@4a009658 {
++usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk at 4a009658 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&utmi_p2_gfclk>;
@@ -946,7 +946,7 @@ index 0000000..391edee
+ reg = <0x4a009658 0x4>;
+};
+
-+usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk@4a009658 {
++usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk at 4a009658 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&l3init_60m_fclk>;
@@ -954,7 +954,7 @@ index 0000000..391edee
+ reg = <0x4a009658 0x4>;
+};
+
-+usb_otg_ss_refclk960m: usb_otg_ss_refclk960m@4a0096f0 {
++usb_otg_ss_refclk960m: usb_otg_ss_refclk960m at 4a0096f0 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll_usb_clkdcoldo>;
@@ -962,7 +962,7 @@ index 0000000..391edee
+ reg = <0x4a0096f0 0x4>;
+};
+
-+usb_phy_cm_clk32k: usb_phy_cm_clk32k@4a008640 {
++usb_phy_cm_clk32k: usb_phy_cm_clk32k at 4a008640 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_32k_ck>;
@@ -970,7 +970,7 @@ index 0000000..391edee
+ reg = <0x4a008640 0x4>;
+};
+
-+usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk@4a009668 {
++usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk at 4a009668 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&l3init_60m_fclk>;
@@ -978,7 +978,7 @@ index 0000000..391edee
+ reg = <0x4a009668 0x4>;
+};
+
-+usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk@4a009668 {
++usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk at 4a009668 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&l3init_60m_fclk>;
@@ -986,7 +986,7 @@ index 0000000..391edee
+ reg = <0x4a009668 0x4>;
+};
+
-+usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk@4a009668 {
++usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk at 4a009668 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&l3init_60m_fclk>;
@@ -994,7 +994,7 @@ index 0000000..391edee
+ reg = <0x4a009668 0x4>;
+};
+
-+aess_fclk: aess_fclk@4a004528 {
++aess_fclk: aess_fclk at 4a004528 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&abe_clk>;
@@ -1003,7 +1003,7 @@ index 0000000..391edee
+ bit-mask = <0x1>;
+};
+
-+dmic_sync_mux_ck: dmic_sync_mux_ck@4a004538 {
++dmic_sync_mux_ck: dmic_sync_mux_ck at 4a004538 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
@@ -1012,7 +1012,7 @@ index 0000000..391edee
+ bit-mask = <0x3>;
+};
+
-+dmic_gfclk: dmic_gfclk@4a004538 {
++dmic_gfclk: dmic_gfclk at 4a004538 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
@@ -1021,7 +1021,7 @@ index 0000000..391edee
+ bit-mask = <0x3>;
+};
+
-+fdif_fclk: fdif_fclk@4a009328 {
++fdif_fclk: fdif_fclk at 4a009328 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_per_h11x2_ck>;
@@ -1030,7 +1030,7 @@ index 0000000..391edee
+ bit-mask = <0x1>;
+};
+
-+gpu_core_gclk_mux: gpu_core_gclk_mux@4a009520 {
++gpu_core_gclk_mux: gpu_core_gclk_mux at 4a009520 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
@@ -1039,7 +1039,7 @@ index 0000000..391edee
+ bit-mask = <0x1>;
+};
+
-+gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@4a009520 {
++gpu_hyd_gclk_mux: gpu_hyd_gclk_mux at 4a009520 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
@@ -1048,7 +1048,7 @@ index 0000000..391edee
+ bit-mask = <0x1>;
+};
+
-+hsi_fclk: hsi_fclk@4a009638 {
++hsi_fclk: hsi_fclk at 4a009638 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll_per_m2x2_ck>;
@@ -1057,7 +1057,7 @@ index 0000000..391edee
+ bit-mask = <0x1>;
+};
+
-+mcasp_sync_mux_ck: mcasp_sync_mux_ck@4a004540 {
++mcasp_sync_mux_ck: mcasp_sync_mux_ck at 4a004540 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
@@ -1066,7 +1066,7 @@ index 0000000..391edee
+ bit-mask = <0x3>;
+};
+
-+mcasp_gfclk: mcasp_gfclk@4a004540 {
++mcasp_gfclk: mcasp_gfclk at 4a004540 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
@@ -1075,7 +1075,7 @@ index 0000000..391edee
+ bit-mask = <0x3>;
+};
+
-+mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck@4a004548 {
++mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck at 4a004548 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
@@ -1084,7 +1084,7 @@ index 0000000..391edee
+ bit-mask = <0x3>;
+};
+
-+mcbsp1_gfclk: mcbsp1_gfclk@4a004548 {
++mcbsp1_gfclk: mcbsp1_gfclk at 4a004548 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
@@ -1093,7 +1093,7 @@ index 0000000..391edee
+ bit-mask = <0x3>;
+};
+
-+mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck@4a004550 {
++mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck at 4a004550 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
@@ -1102,7 +1102,7 @@ index 0000000..391edee
+ bit-mask = <0x3>;
+};
+
-+mcbsp2_gfclk: mcbsp2_gfclk@4a004550 {
++mcbsp2_gfclk: mcbsp2_gfclk at 4a004550 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
@@ -1111,7 +1111,7 @@ index 0000000..391edee
+ bit-mask = <0x3>;
+};
+
-+mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck@4a004558 {
++mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck at 4a004558 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
@@ -1120,7 +1120,7 @@ index 0000000..391edee
+ bit-mask = <0x3>;
+};
+
-+mcbsp3_gfclk: mcbsp3_gfclk@4a004558 {
++mcbsp3_gfclk: mcbsp3_gfclk at 4a004558 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
@@ -1129,7 +1129,7 @@ index 0000000..391edee
+ bit-mask = <0x3>;
+};
+
-+mmc1_fclk_mux: mmc1_fclk_mux@4a009628 {
++mmc1_fclk_mux: mmc1_fclk_mux at 4a009628 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
@@ -1138,7 +1138,7 @@ index 0000000..391edee
+ bit-mask = <0x1>;
+};
+
-+mmc1_fclk: mmc1_fclk@4a009628 {
++mmc1_fclk: mmc1_fclk at 4a009628 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&mmc1_fclk_mux>;
@@ -1147,7 +1147,7 @@ index 0000000..391edee
+ bit-mask = <0x1>;
+};
+
-+mmc2_fclk_mux: mmc2_fclk_mux@4a009630 {
++mmc2_fclk_mux: mmc2_fclk_mux at 4a009630 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
@@ -1156,7 +1156,7 @@ index 0000000..391edee
+ bit-mask = <0x1>;
+};
+
-+mmc2_fclk: mmc2_fclk@4a009630 {
++mmc2_fclk: mmc2_fclk at 4a009630 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&mmc2_fclk_mux>;
@@ -1165,7 +1165,7 @@ index 0000000..391edee
+ bit-mask = <0x1>;
+};
+
-+timer10_gfclk_mux: timer10_gfclk_mux@4a009028 {
++timer10_gfclk_mux: timer10_gfclk_mux at 4a009028 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
@@ -1174,7 +1174,7 @@ index 0000000..391edee
+ bit-mask = <0x1>;
+};
+
-+timer11_gfclk_mux: timer11_gfclk_mux@4a009030 {
++timer11_gfclk_mux: timer11_gfclk_mux at 4a009030 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
@@ -1183,7 +1183,7 @@ index 0000000..391edee
+ bit-mask = <0x1>;
+};
+
-+timer1_gfclk_mux: timer1_gfclk_mux@4ae07940 {
++timer1_gfclk_mux: timer1_gfclk_mux at 4ae07940 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
@@ -1192,7 +1192,7 @@ index 0000000..391edee
+ bit-mask = <0x1>;
+};
+
-+timer2_gfclk_mux: timer2_gfclk_mux@4a009038 {
++timer2_gfclk_mux: timer2_gfclk_mux at 4a009038 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
@@ -1201,7 +1201,7 @@ index 0000000..391edee
+ bit-mask = <0x1>;
+};
+
-+timer3_gfclk_mux: timer3_gfclk_mux@4a009040 {
++timer3_gfclk_mux: timer3_gfclk_mux at 4a009040 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
@@ -1210,7 +1210,7 @@ index 0000000..391edee
+ bit-mask = <0x1>;
+};
+
-+timer4_gfclk_mux: timer4_gfclk_mux@4a009048 {
++timer4_gfclk_mux: timer4_gfclk_mux at 4a009048 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
@@ -1219,7 +1219,7 @@ index 0000000..391edee
+ bit-mask = <0x1>;
+};
+
-+timer5_gfclk_mux: timer5_gfclk_mux@4a004568 {
++timer5_gfclk_mux: timer5_gfclk_mux at 4a004568 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
@@ -1228,7 +1228,7 @@ index 0000000..391edee
+ bit-mask = <0x1>;
+};
+
-+timer6_gfclk_mux: timer6_gfclk_mux@4a004570 {
++timer6_gfclk_mux: timer6_gfclk_mux at 4a004570 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
@@ -1237,7 +1237,7 @@ index 0000000..391edee
+ bit-mask = <0x1>;
+};
+
-+timer7_gfclk_mux: timer7_gfclk_mux@4a004578 {
++timer7_gfclk_mux: timer7_gfclk_mux at 4a004578 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
@@ -1246,7 +1246,7 @@ index 0000000..391edee
+ bit-mask = <0x1>;
+};
+
-+timer8_gfclk_mux: timer8_gfclk_mux@4a004580 {
++timer8_gfclk_mux: timer8_gfclk_mux at 4a004580 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
@@ -1255,7 +1255,7 @@ index 0000000..391edee
+ bit-mask = <0x1>;
+};
+
-+timer9_gfclk_mux: timer9_gfclk_mux@4a009050 {
++timer9_gfclk_mux: timer9_gfclk_mux at 4a009050 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin>, <&sys_32k_ck>;
@@ -1264,7 +1264,7 @@ index 0000000..391edee
+ bit-mask = <0x1>;
+};
+
-+auxclk0_src_mux_ck: auxclk0_src_mux_ck@4ae0a310 {
++auxclk0_src_mux_ck: auxclk0_src_mux_ck at 4ae0a310 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
@@ -1273,7 +1273,7 @@ index 0000000..391edee
+ bit-mask = <0x3>;
+};
+
-+auxclk0_src_ck: auxclk0_src_ck@4ae0a310 {
++auxclk0_src_ck: auxclk0_src_ck at 4ae0a310 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&auxclk0_src_mux_ck>;
@@ -1281,7 +1281,7 @@ index 0000000..391edee
+ reg = <0x4ae0a310 0x4>;
+};
+
-+auxclk0_ck: auxclk0_ck@4ae0a310 {
++auxclk0_ck: auxclk0_ck at 4ae0a310 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&auxclk0_src_ck>;
@@ -1290,7 +1290,7 @@ index 0000000..391edee
+ bit-mask = <0xf>;
+};
+
-+auxclk1_src_mux_ck: auxclk1_src_mux_ck@4ae0a314 {
++auxclk1_src_mux_ck: auxclk1_src_mux_ck at 4ae0a314 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
@@ -1299,7 +1299,7 @@ index 0000000..391edee
+ bit-mask = <0x3>;
+};
+
-+auxclk1_src_ck: auxclk1_src_ck@4ae0a314 {
++auxclk1_src_ck: auxclk1_src_ck at 4ae0a314 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&auxclk1_src_mux_ck>;
@@ -1307,7 +1307,7 @@ index 0000000..391edee
+ reg = <0x4ae0a314 0x4>;
+};
+
-+auxclk1_ck: auxclk1_ck@4ae0a314 {
++auxclk1_ck: auxclk1_ck at 4ae0a314 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&auxclk1_src_ck>;
@@ -1316,7 +1316,7 @@ index 0000000..391edee
+ bit-mask = <0xf>;
+};
+
-+auxclk2_src_mux_ck: auxclk2_src_mux_ck@4ae0a318 {
++auxclk2_src_mux_ck: auxclk2_src_mux_ck at 4ae0a318 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
@@ -1325,7 +1325,7 @@ index 0000000..391edee
+ bit-mask = <0x3>;
+};
+
-+auxclk2_src_ck: auxclk2_src_ck@4ae0a318 {
++auxclk2_src_ck: auxclk2_src_ck at 4ae0a318 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&auxclk2_src_mux_ck>;
@@ -1333,7 +1333,7 @@ index 0000000..391edee
+ reg = <0x4ae0a318 0x4>;
+};
+
-+auxclk2_ck: auxclk2_ck@4ae0a318 {
++auxclk2_ck: auxclk2_ck at 4ae0a318 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&auxclk2_src_ck>;
@@ -1342,7 +1342,7 @@ index 0000000..391edee
+ bit-mask = <0xf>;
+};
+
-+auxclk3_src_mux_ck: auxclk3_src_mux_ck@4ae0a31c {
++auxclk3_src_mux_ck: auxclk3_src_mux_ck at 4ae0a31c {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
@@ -1351,7 +1351,7 @@ index 0000000..391edee
+ bit-mask = <0x3>;
+};
+
-+auxclk3_src_ck: auxclk3_src_ck@4ae0a31c {
++auxclk3_src_ck: auxclk3_src_ck at 4ae0a31c {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&auxclk3_src_mux_ck>;
@@ -1359,7 +1359,7 @@ index 0000000..391edee
+ reg = <0x4ae0a31c 0x4>;
+};
+
-+auxclk3_ck: auxclk3_ck@4ae0a31c {
++auxclk3_ck: auxclk3_ck at 4ae0a31c {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&auxclk3_src_ck>;
@@ -1368,7 +1368,7 @@ index 0000000..391edee
+ bit-mask = <0xf>;
+};
+
-+auxclk4_src_mux_ck: auxclk4_src_mux_ck@4ae0a320 {
++auxclk4_src_mux_ck: auxclk4_src_mux_ck at 4ae0a320 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
@@ -1377,7 +1377,7 @@ index 0000000..391edee
+ bit-mask = <0x3>;
+};
+
-+auxclk4_src_ck: auxclk4_src_ck@4ae0a320 {
++auxclk4_src_ck: auxclk4_src_ck at 4ae0a320 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&auxclk4_src_mux_ck>;
@@ -1385,7 +1385,7 @@ index 0000000..391edee
+ reg = <0x4ae0a320 0x4>;
+};
+
-+auxclk4_ck: auxclk4_ck@4ae0a320 {
++auxclk4_ck: auxclk4_ck at 4ae0a320 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&auxclk4_src_ck>;
@@ -1394,7 +1394,7 @@ index 0000000..391edee
+ bit-mask = <0xf>;
+};
+
-+auxclkreq0_ck: auxclkreq0_ck@4ae0a210 {
++auxclkreq0_ck: auxclkreq0_ck at 4ae0a210 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
@@ -1403,7 +1403,7 @@ index 0000000..391edee
+ bit-mask = <0x7>;
+};
+
-+auxclkreq1_ck: auxclkreq1_ck@4ae0a214 {
++auxclkreq1_ck: auxclkreq1_ck at 4ae0a214 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
@@ -1412,7 +1412,7 @@ index 0000000..391edee
+ bit-mask = <0x7>;
+};
+
-+auxclkreq2_ck: auxclkreq2_ck@4ae0a218 {
++auxclkreq2_ck: auxclkreq2_ck at 4ae0a218 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
@@ -1421,7 +1421,7 @@ index 0000000..391edee
+ bit-mask = <0x7>;
+};
+
-+auxclkreq3_ck: auxclkreq3_ck@4ae0a21c {
++auxclkreq3_ck: auxclkreq3_ck at 4ae0a21c {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
diff --git a/a/content_digest b/N1/content_digest
index 634b79a..8bff8b4 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -2,7 +2,7 @@
"ref\0001374564028-11352-1-git-send-email-t-kristo\@ti.com\0"
]
[
- "From\0Tero Kristo <t-kristo\@ti.com>\0"
+ "From\0t-kristo\@ti.com (Tero Kristo)\0"
]
[
"Subject\0[PATCHv4 11/33] ARM: dts: omap5 clock data\0"
@@ -11,17 +11,7 @@
"Date\0Tue, 23 Jul 2013 10:20:06 +0300\0"
]
[
- "To\0linux-omap\@vger.kernel.org",
- " paul\@pwsan.com",
- " khilman\@linaro.org",
- " tony\@atomide.com",
- " mturquette\@linaro.org",
- " nm\@ti.com",
- " rnayak\@ti.com\0"
-]
-[
- "Cc\0linux-arm-kernel\@lists.infradead.org",
- " devicetree-discuss\@lists.ozlabs.org\0"
+ "To\0linux-arm-kernel\@lists.infradead.org\0"
]
[
"\0000:1\0"
@@ -61,7 +51,7 @@
"+\tclock-frequency = <12000000>;\n",
"+};\n",
"+\n",
- "+pad_clks_ck: pad_clks_ck\@4a004108 {\n",
+ "+pad_clks_ck: pad_clks_ck at 4a004108 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&pad_clks_src_ck>;\n",
@@ -81,7 +71,7 @@
"+\tclock-frequency = <12000000>;\n",
"+};\n",
"+\n",
- "+slimbus_clk: slimbus_clk\@4a004108 {\n",
+ "+slimbus_clk: slimbus_clk at 4a004108 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&slimbus_src_clk>;\n",
@@ -137,7 +127,7 @@
"+\tclock-frequency = <38400000>;\n",
"+};\n",
"+\n",
- "+sys_clkin: sys_clkin\@4ae06110 {\n",
+ "+sys_clkin: sys_clkin at 4ae06110 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;\n",
@@ -158,7 +148,7 @@
"+\tclock-frequency = <60000000>;\n",
"+};\n",
"+\n",
- "+abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux\@4ae06108 {\n",
+ "+abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux at 4ae06108 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&sys_clkin>, <&sys_32k_ck>;\n",
@@ -166,7 +156,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+abe_dpll_clk_mux: abe_dpll_clk_mux\@4ae0610c {\n",
+ "+abe_dpll_clk_mux: abe_dpll_clk_mux at 4ae0610c {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&sys_clkin>, <&sys_32k_ck>;\n",
@@ -174,7 +164,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+dpll_abe_ck: dpll_abe_ck\@4a0041e0 {\n",
+ "+dpll_abe_ck: dpll_abe_ck at 4a0041e0 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,omap4-dpll-clock\";\n",
"+\tclocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;\n",
@@ -191,7 +181,7 @@
"+\tti,dpll-clk-x2;\n",
"+};\n",
"+\n",
- "+dpll_abe_m2x2_ck: dpll_abe_m2x2_ck\@4a0041f0 {\n",
+ "+dpll_abe_m2x2_ck: dpll_abe_m2x2_ck at 4a0041f0 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll_abe_x2_ck>;\n",
@@ -210,7 +200,7 @@
"+\tclock-div = <8>;\n",
"+};\n",
"+\n",
- "+abe_clk: abe_clk\@4a004108 {\n",
+ "+abe_clk: abe_clk at 4a004108 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll_abe_m2x2_ck>;\n",
@@ -235,7 +225,7 @@
"+\tclock-div = <16>;\n",
"+};\n",
"+\n",
- "+dpll_abe_m3x2_ck: dpll_abe_m3x2_ck\@4a0041f4 {\n",
+ "+dpll_abe_m3x2_ck: dpll_abe_m3x2_ck at 4a0041f4 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll_abe_x2_ck>;\n",
@@ -246,7 +236,7 @@
"+\tti,autoidle-low;\n",
"+};\n",
"+\n",
- "+dpll_core_ck: dpll_core_ck\@4a004120 {\n",
+ "+dpll_core_ck: dpll_core_ck at 4a004120 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,omap4-dpll-clock\";\n",
"+\tclocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;\n",
@@ -263,7 +253,7 @@
"+\tti,dpll-clk-x2;\n",
"+};\n",
"+\n",
- "+dpll_core_h21x2_ck: dpll_core_h21x2_ck\@4a004150 {\n",
+ "+dpll_core_h21x2_ck: dpll_core_h21x2_ck at 4a004150 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll_core_x2_ck>;\n",
@@ -298,7 +288,7 @@
"+\tclock-div = <2>;\n",
"+};\n",
"+\n",
- "+dpll_core_h11x2_ck: dpll_core_h11x2_ck\@4a004138 {\n",
+ "+dpll_core_h11x2_ck: dpll_core_h11x2_ck at 4a004138 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll_core_x2_ck>;\n",
@@ -309,7 +299,7 @@
"+\tti,autoidle-low;\n",
"+};\n",
"+\n",
- "+dpll_core_h12x2_ck: dpll_core_h12x2_ck\@4a00413c {\n",
+ "+dpll_core_h12x2_ck: dpll_core_h12x2_ck at 4a00413c {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll_core_x2_ck>;\n",
@@ -320,7 +310,7 @@
"+\tti,autoidle-low;\n",
"+};\n",
"+\n",
- "+dpll_core_h13x2_ck: dpll_core_h13x2_ck\@4a004140 {\n",
+ "+dpll_core_h13x2_ck: dpll_core_h13x2_ck at 4a004140 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll_core_x2_ck>;\n",
@@ -331,7 +321,7 @@
"+\tti,autoidle-low;\n",
"+};\n",
"+\n",
- "+dpll_core_h14x2_ck: dpll_core_h14x2_ck\@4a004144 {\n",
+ "+dpll_core_h14x2_ck: dpll_core_h14x2_ck at 4a004144 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll_core_x2_ck>;\n",
@@ -342,7 +332,7 @@
"+\tti,autoidle-low;\n",
"+};\n",
"+\n",
- "+dpll_core_h22x2_ck: dpll_core_h22x2_ck\@4a004154 {\n",
+ "+dpll_core_h22x2_ck: dpll_core_h22x2_ck at 4a004154 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll_core_x2_ck>;\n",
@@ -353,7 +343,7 @@
"+\tti,autoidle-low;\n",
"+};\n",
"+\n",
- "+dpll_core_h23x2_ck: dpll_core_h23x2_ck\@4a004158 {\n",
+ "+dpll_core_h23x2_ck: dpll_core_h23x2_ck at 4a004158 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll_core_x2_ck>;\n",
@@ -364,7 +354,7 @@
"+\tti,autoidle-low;\n",
"+};\n",
"+\n",
- "+dpll_core_h24x2_ck: dpll_core_h24x2_ck\@4a00415c {\n",
+ "+dpll_core_h24x2_ck: dpll_core_h24x2_ck at 4a00415c {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll_core_x2_ck>;\n",
@@ -375,7 +365,7 @@
"+\tti,autoidle-low;\n",
"+};\n",
"+\n",
- "+dpll_core_m2_ck: dpll_core_m2_ck\@4a004130 {\n",
+ "+dpll_core_m2_ck: dpll_core_m2_ck at 4a004130 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll_core_ck>;\n",
@@ -386,7 +376,7 @@
"+\tti,autoidle-low;\n",
"+};\n",
"+\n",
- "+dpll_core_m3x2_ck: dpll_core_m3x2_ck\@4a004134 {\n",
+ "+dpll_core_m3x2_ck: dpll_core_m3x2_ck at 4a004134 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll_core_x2_ck>;\n",
@@ -405,7 +395,7 @@
"+\tclock-div = <1>;\n",
"+};\n",
"+\n",
- "+dpll_iva_ck: dpll_iva_ck\@4a0041a0 {\n",
+ "+dpll_iva_ck: dpll_iva_ck at 4a0041a0 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,omap4-dpll-clock\";\n",
"+\tclocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;\n",
@@ -421,7 +411,7 @@
"+\tti,dpll-clk-x2;\n",
"+};\n",
"+\n",
- "+dpll_iva_h11x2_ck: dpll_iva_h11x2_ck\@4a0041b8 {\n",
+ "+dpll_iva_h11x2_ck: dpll_iva_h11x2_ck at 4a0041b8 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll_iva_x2_ck>;\n",
@@ -432,7 +422,7 @@
"+\tti,autoidle-low;\n",
"+};\n",
"+\n",
- "+dpll_iva_h12x2_ck: dpll_iva_h12x2_ck\@4a0041bc {\n",
+ "+dpll_iva_h12x2_ck: dpll_iva_h12x2_ck at 4a0041bc {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll_iva_x2_ck>;\n",
@@ -451,7 +441,7 @@
"+\tclock-div = <1>;\n",
"+};\n",
"+\n",
- "+dpll_mpu_ck: dpll_mpu_ck\@4a004160 {\n",
+ "+dpll_mpu_ck: dpll_mpu_ck at 4a004160 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,omap4-dpll-clock\";\n",
"+\tclocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>;\n",
@@ -460,7 +450,7 @@
"+\tti,clk-bypass = <&mpu_dpll_hs_clk_div>;\n",
"+};\n",
"+\n",
- "+dpll_mpu_m2_ck: dpll_mpu_m2_ck\@4a004170 {\n",
+ "+dpll_mpu_m2_ck: dpll_mpu_m2_ck at 4a004170 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll_mpu_ck>;\n",
@@ -479,7 +469,7 @@
"+\tclock-div = <2>;\n",
"+};\n",
"+\n",
- "+dpll_per_ck: dpll_per_ck\@4a008140 {\n",
+ "+dpll_per_ck: dpll_per_ck at 4a008140 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,omap4-dpll-clock\";\n",
"+\tclocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;\n",
@@ -495,7 +485,7 @@
"+\tti,dpll-clk-x2;\n",
"+};\n",
"+\n",
- "+dpll_per_h11x2_ck: dpll_per_h11x2_ck\@4a008158 {\n",
+ "+dpll_per_h11x2_ck: dpll_per_h11x2_ck at 4a008158 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll_per_x2_ck>;\n",
@@ -506,7 +496,7 @@
"+\tti,autoidle-low;\n",
"+};\n",
"+\n",
- "+dpll_per_h12x2_ck: dpll_per_h12x2_ck\@4a00815c {\n",
+ "+dpll_per_h12x2_ck: dpll_per_h12x2_ck at 4a00815c {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll_per_x2_ck>;\n",
@@ -517,7 +507,7 @@
"+\tti,autoidle-low;\n",
"+};\n",
"+\n",
- "+dpll_per_h14x2_ck: dpll_per_h14x2_ck\@4a008164 {\n",
+ "+dpll_per_h14x2_ck: dpll_per_h14x2_ck at 4a008164 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll_per_x2_ck>;\n",
@@ -528,7 +518,7 @@
"+\tti,autoidle-low;\n",
"+};\n",
"+\n",
- "+dpll_per_m2_ck: dpll_per_m2_ck\@4a008150 {\n",
+ "+dpll_per_m2_ck: dpll_per_m2_ck at 4a008150 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll_per_ck>;\n",
@@ -539,7 +529,7 @@
"+\tti,autoidle-low;\n",
"+};\n",
"+\n",
- "+dpll_per_m2x2_ck: dpll_per_m2x2_ck\@4a008150 {\n",
+ "+dpll_per_m2x2_ck: dpll_per_m2x2_ck at 4a008150 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll_per_x2_ck>;\n",
@@ -550,7 +540,7 @@
"+\tti,autoidle-low;\n",
"+};\n",
"+\n",
- "+dpll_per_m3x2_ck: dpll_per_m3x2_ck\@4a008154 {\n",
+ "+dpll_per_m3x2_ck: dpll_per_m3x2_ck at 4a008154 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll_per_x2_ck>;\n",
@@ -561,7 +551,7 @@
"+\tti,autoidle-low;\n",
"+};\n",
"+\n",
- "+dpll_unipro1_ck: dpll_unipro1_ck\@4a008200 {\n",
+ "+dpll_unipro1_ck: dpll_unipro1_ck at 4a008200 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,omap4-dpll-clock\";\n",
"+\tclocks = <&sys_clkin>;\n",
@@ -578,7 +568,7 @@
"+\tclock-div = <1>;\n",
"+};\n",
"+\n",
- "+dpll_unipro1_m2_ck: dpll_unipro1_m2_ck\@4a008210 {\n",
+ "+dpll_unipro1_m2_ck: dpll_unipro1_m2_ck at 4a008210 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll_unipro1_ck>;\n",
@@ -589,7 +579,7 @@
"+\tti,autoidle-low;\n",
"+};\n",
"+\n",
- "+dpll_unipro2_ck: dpll_unipro2_ck\@4a0081c0 {\n",
+ "+dpll_unipro2_ck: dpll_unipro2_ck at 4a0081c0 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,omap4-dpll-clock\";\n",
"+\tclocks = <&sys_clkin>;\n",
@@ -606,7 +596,7 @@
"+\tclock-div = <1>;\n",
"+};\n",
"+\n",
- "+dpll_unipro2_m2_ck: dpll_unipro2_m2_ck\@4a0081d0 {\n",
+ "+dpll_unipro2_m2_ck: dpll_unipro2_m2_ck at 4a0081d0 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll_unipro2_ck>;\n",
@@ -625,7 +615,7 @@
"+\tclock-div = <3>;\n",
"+};\n",
"+\n",
- "+dpll_usb_ck: dpll_usb_ck\@4a008180 {\n",
+ "+dpll_usb_ck: dpll_usb_ck at 4a008180 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,omap4-dpll-clock\";\n",
"+\tclocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;\n",
@@ -644,7 +634,7 @@
"+\tclock-div = <1>;\n",
"+};\n",
"+\n",
- "+dpll_usb_m2_ck: dpll_usb_m2_ck\@4a008190 {\n",
+ "+dpll_usb_m2_ck: dpll_usb_m2_ck at 4a008190 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll_usb_ck>;\n",
@@ -719,7 +709,7 @@
"+\tclock-div = <1>;\n",
"+};\n",
"+\n",
- "+l3init_60m_fclk: l3init_60m_fclk\@4a008104 {\n",
+ "+l3init_60m_fclk: l3init_60m_fclk at 4a008104 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll_usb_m2_ck>;\n",
@@ -728,7 +718,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+wkupaon_iclk_mux: wkupaon_iclk_mux\@4ae06108 {\n",
+ "+wkupaon_iclk_mux: wkupaon_iclk_mux at 4ae06108 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&sys_clkin>, <&abe_lp_clk_div>;\n",
@@ -752,7 +742,7 @@
"+\tclock-div = <1>;\n",
"+};\n",
"+\n",
- "+dss_32khz_clk: dss_32khz_clk\@4a009420 {\n",
+ "+dss_32khz_clk: dss_32khz_clk at 4a009420 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&sys_32k_ck>;\n",
@@ -760,7 +750,7 @@
"+\treg = <0x4a009420 0x4>;\n",
"+};\n",
"+\n",
- "+dss_48mhz_clk: dss_48mhz_clk\@4a009420 {\n",
+ "+dss_48mhz_clk: dss_48mhz_clk at 4a009420 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&func_48m_fclk>;\n",
@@ -768,7 +758,7 @@
"+\treg = <0x4a009420 0x4>;\n",
"+};\n",
"+\n",
- "+dss_dss_clk: dss_dss_clk\@4a009420 {\n",
+ "+dss_dss_clk: dss_dss_clk at 4a009420 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&dpll_per_h12x2_ck>;\n",
@@ -776,7 +766,7 @@
"+\treg = <0x4a009420 0x4>;\n",
"+};\n",
"+\n",
- "+dss_sys_clk: dss_sys_clk\@4a009420 {\n",
+ "+dss_sys_clk: dss_sys_clk at 4a009420 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&dss_syc_gfclk_div>;\n",
@@ -784,7 +774,7 @@
"+\treg = <0x4a009420 0x4>;\n",
"+};\n",
"+\n",
- "+gpio1_dbclk: gpio1_dbclk\@4ae07938 {\n",
+ "+gpio1_dbclk: gpio1_dbclk at 4ae07938 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&sys_32k_ck>;\n",
@@ -792,7 +782,7 @@
"+\treg = <0x4ae07938 0x4>;\n",
"+};\n",
"+\n",
- "+gpio2_dbclk: gpio2_dbclk\@4a009060 {\n",
+ "+gpio2_dbclk: gpio2_dbclk at 4a009060 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&sys_32k_ck>;\n",
@@ -800,7 +790,7 @@
"+\treg = <0x4a009060 0x4>;\n",
"+};\n",
"+\n",
- "+gpio3_dbclk: gpio3_dbclk\@4a009068 {\n",
+ "+gpio3_dbclk: gpio3_dbclk at 4a009068 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&sys_32k_ck>;\n",
@@ -808,7 +798,7 @@
"+\treg = <0x4a009068 0x4>;\n",
"+};\n",
"+\n",
- "+gpio4_dbclk: gpio4_dbclk\@4a009070 {\n",
+ "+gpio4_dbclk: gpio4_dbclk at 4a009070 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&sys_32k_ck>;\n",
@@ -816,7 +806,7 @@
"+\treg = <0x4a009070 0x4>;\n",
"+};\n",
"+\n",
- "+gpio5_dbclk: gpio5_dbclk\@4a009078 {\n",
+ "+gpio5_dbclk: gpio5_dbclk at 4a009078 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&sys_32k_ck>;\n",
@@ -824,7 +814,7 @@
"+\treg = <0x4a009078 0x4>;\n",
"+};\n",
"+\n",
- "+gpio6_dbclk: gpio6_dbclk\@4a009080 {\n",
+ "+gpio6_dbclk: gpio6_dbclk at 4a009080 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&sys_32k_ck>;\n",
@@ -832,7 +822,7 @@
"+\treg = <0x4a009080 0x4>;\n",
"+};\n",
"+\n",
- "+gpio7_dbclk: gpio7_dbclk\@4a009110 {\n",
+ "+gpio7_dbclk: gpio7_dbclk at 4a009110 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&sys_32k_ck>;\n",
@@ -840,7 +830,7 @@
"+\treg = <0x4a009110 0x4>;\n",
"+};\n",
"+\n",
- "+gpio8_dbclk: gpio8_dbclk\@4a009118 {\n",
+ "+gpio8_dbclk: gpio8_dbclk at 4a009118 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&sys_32k_ck>;\n",
@@ -848,7 +838,7 @@
"+\treg = <0x4a009118 0x4>;\n",
"+};\n",
"+\n",
- "+iss_ctrlclk: iss_ctrlclk\@4a009320 {\n",
+ "+iss_ctrlclk: iss_ctrlclk at 4a009320 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&func_96m_fclk>;\n",
@@ -856,7 +846,7 @@
"+\treg = <0x4a009320 0x4>;\n",
"+};\n",
"+\n",
- "+lli_txphy_clk: lli_txphy_clk\@4a008f20 {\n",
+ "+lli_txphy_clk: lli_txphy_clk at 4a008f20 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&dpll_unipro1_clkdcoldo>;\n",
@@ -864,7 +854,7 @@
"+\treg = <0x4a008f20 0x4>;\n",
"+};\n",
"+\n",
- "+lli_txphy_ls_clk: lli_txphy_ls_clk\@4a008f20 {\n",
+ "+lli_txphy_ls_clk: lli_txphy_ls_clk at 4a008f20 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&dpll_unipro1_m2_ck>;\n",
@@ -872,7 +862,7 @@
"+\treg = <0x4a008f20 0x4>;\n",
"+};\n",
"+\n",
- "+mmc1_32khz_clk: mmc1_32khz_clk\@4a009628 {\n",
+ "+mmc1_32khz_clk: mmc1_32khz_clk at 4a009628 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&sys_32k_ck>;\n",
@@ -880,7 +870,7 @@
"+\treg = <0x4a009628 0x4>;\n",
"+};\n",
"+\n",
- "+sata_ref_clk: sata_ref_clk\@4a009688 {\n",
+ "+sata_ref_clk: sata_ref_clk at 4a009688 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&sys_clkin>;\n",
@@ -888,7 +878,7 @@
"+\treg = <0x4a009688 0x4>;\n",
"+};\n",
"+\n",
- "+slimbus1_slimbus_clk: slimbus1_slimbus_clk\@4a004560 {\n",
+ "+slimbus1_slimbus_clk: slimbus1_slimbus_clk at 4a004560 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&slimbus_clk>;\n",
@@ -896,7 +886,7 @@
"+\treg = <0x4a004560 0x4>;\n",
"+};\n",
"+\n",
- "+usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk\@4a009658 {\n",
+ "+usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk at 4a009658 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&dpll_usb_m2_ck>;\n",
@@ -904,7 +894,7 @@
"+\treg = <0x4a009658 0x4>;\n",
"+};\n",
"+\n",
- "+usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk\@4a009658 {\n",
+ "+usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk at 4a009658 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&dpll_usb_m2_ck>;\n",
@@ -912,7 +902,7 @@
"+\treg = <0x4a009658 0x4>;\n",
"+};\n",
"+\n",
- "+usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk\@4a009658 {\n",
+ "+usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk at 4a009658 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&dpll_usb_m2_ck>;\n",
@@ -920,7 +910,7 @@
"+\treg = <0x4a009658 0x4>;\n",
"+};\n",
"+\n",
- "+usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk\@4a009658 {\n",
+ "+usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk at 4a009658 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&l3init_60m_fclk>;\n",
@@ -928,7 +918,7 @@
"+\treg = <0x4a009658 0x4>;\n",
"+};\n",
"+\n",
- "+usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk\@4a009658 {\n",
+ "+usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk at 4a009658 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&l3init_60m_fclk>;\n",
@@ -936,7 +926,7 @@
"+\treg = <0x4a009658 0x4>;\n",
"+};\n",
"+\n",
- "+usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk\@4a009658 {\n",
+ "+usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk at 4a009658 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&l3init_60m_fclk>;\n",
@@ -944,7 +934,7 @@
"+\treg = <0x4a009658 0x4>;\n",
"+};\n",
"+\n",
- "+utmi_p1_gfclk: utmi_p1_gfclk\@4a009658 {\n",
+ "+utmi_p1_gfclk: utmi_p1_gfclk at 4a009658 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&l3init_60m_fclk>, <&xclk60mhsp1_ck>;\n",
@@ -953,7 +943,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk\@4a009658 {\n",
+ "+usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk at 4a009658 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&utmi_p1_gfclk>;\n",
@@ -961,7 +951,7 @@
"+\treg = <0x4a009658 0x4>;\n",
"+};\n",
"+\n",
- "+utmi_p2_gfclk: utmi_p2_gfclk\@4a009658 {\n",
+ "+utmi_p2_gfclk: utmi_p2_gfclk at 4a009658 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&l3init_60m_fclk>, <&xclk60mhsp2_ck>;\n",
@@ -970,7 +960,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk\@4a009658 {\n",
+ "+usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk at 4a009658 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&utmi_p2_gfclk>;\n",
@@ -978,7 +968,7 @@
"+\treg = <0x4a009658 0x4>;\n",
"+};\n",
"+\n",
- "+usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk\@4a009658 {\n",
+ "+usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk at 4a009658 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&l3init_60m_fclk>;\n",
@@ -986,7 +976,7 @@
"+\treg = <0x4a009658 0x4>;\n",
"+};\n",
"+\n",
- "+usb_otg_ss_refclk960m: usb_otg_ss_refclk960m\@4a0096f0 {\n",
+ "+usb_otg_ss_refclk960m: usb_otg_ss_refclk960m at 4a0096f0 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&dpll_usb_clkdcoldo>;\n",
@@ -994,7 +984,7 @@
"+\treg = <0x4a0096f0 0x4>;\n",
"+};\n",
"+\n",
- "+usb_phy_cm_clk32k: usb_phy_cm_clk32k\@4a008640 {\n",
+ "+usb_phy_cm_clk32k: usb_phy_cm_clk32k at 4a008640 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&sys_32k_ck>;\n",
@@ -1002,7 +992,7 @@
"+\treg = <0x4a008640 0x4>;\n",
"+};\n",
"+\n",
- "+usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk\@4a009668 {\n",
+ "+usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk at 4a009668 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&l3init_60m_fclk>;\n",
@@ -1010,7 +1000,7 @@
"+\treg = <0x4a009668 0x4>;\n",
"+};\n",
"+\n",
- "+usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk\@4a009668 {\n",
+ "+usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk at 4a009668 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&l3init_60m_fclk>;\n",
@@ -1018,7 +1008,7 @@
"+\treg = <0x4a009668 0x4>;\n",
"+};\n",
"+\n",
- "+usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk\@4a009668 {\n",
+ "+usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk at 4a009668 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&l3init_60m_fclk>;\n",
@@ -1026,7 +1016,7 @@
"+\treg = <0x4a009668 0x4>;\n",
"+};\n",
"+\n",
- "+aess_fclk: aess_fclk\@4a004528 {\n",
+ "+aess_fclk: aess_fclk at 4a004528 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&abe_clk>;\n",
@@ -1035,7 +1025,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+dmic_sync_mux_ck: dmic_sync_mux_ck\@4a004538 {\n",
+ "+dmic_sync_mux_ck: dmic_sync_mux_ck at 4a004538 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;\n",
@@ -1044,7 +1034,7 @@
"+\tbit-mask = <0x3>;\n",
"+};\n",
"+\n",
- "+dmic_gfclk: dmic_gfclk\@4a004538 {\n",
+ "+dmic_gfclk: dmic_gfclk at 4a004538 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;\n",
@@ -1053,7 +1043,7 @@
"+\tbit-mask = <0x3>;\n",
"+};\n",
"+\n",
- "+fdif_fclk: fdif_fclk\@4a009328 {\n",
+ "+fdif_fclk: fdif_fclk at 4a009328 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll_per_h11x2_ck>;\n",
@@ -1062,7 +1052,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+gpu_core_gclk_mux: gpu_core_gclk_mux\@4a009520 {\n",
+ "+gpu_core_gclk_mux: gpu_core_gclk_mux at 4a009520 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;\n",
@@ -1071,7 +1061,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+gpu_hyd_gclk_mux: gpu_hyd_gclk_mux\@4a009520 {\n",
+ "+gpu_hyd_gclk_mux: gpu_hyd_gclk_mux at 4a009520 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;\n",
@@ -1080,7 +1070,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+hsi_fclk: hsi_fclk\@4a009638 {\n",
+ "+hsi_fclk: hsi_fclk at 4a009638 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll_per_m2x2_ck>;\n",
@@ -1089,7 +1079,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+mcasp_sync_mux_ck: mcasp_sync_mux_ck\@4a004540 {\n",
+ "+mcasp_sync_mux_ck: mcasp_sync_mux_ck at 4a004540 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;\n",
@@ -1098,7 +1088,7 @@
"+\tbit-mask = <0x3>;\n",
"+};\n",
"+\n",
- "+mcasp_gfclk: mcasp_gfclk\@4a004540 {\n",
+ "+mcasp_gfclk: mcasp_gfclk at 4a004540 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;\n",
@@ -1107,7 +1097,7 @@
"+\tbit-mask = <0x3>;\n",
"+};\n",
"+\n",
- "+mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck\@4a004548 {\n",
+ "+mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck at 4a004548 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;\n",
@@ -1116,7 +1106,7 @@
"+\tbit-mask = <0x3>;\n",
"+};\n",
"+\n",
- "+mcbsp1_gfclk: mcbsp1_gfclk\@4a004548 {\n",
+ "+mcbsp1_gfclk: mcbsp1_gfclk at 4a004548 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;\n",
@@ -1125,7 +1115,7 @@
"+\tbit-mask = <0x3>;\n",
"+};\n",
"+\n",
- "+mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck\@4a004550 {\n",
+ "+mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck at 4a004550 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;\n",
@@ -1134,7 +1124,7 @@
"+\tbit-mask = <0x3>;\n",
"+};\n",
"+\n",
- "+mcbsp2_gfclk: mcbsp2_gfclk\@4a004550 {\n",
+ "+mcbsp2_gfclk: mcbsp2_gfclk at 4a004550 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;\n",
@@ -1143,7 +1133,7 @@
"+\tbit-mask = <0x3>;\n",
"+};\n",
"+\n",
- "+mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck\@4a004558 {\n",
+ "+mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck at 4a004558 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;\n",
@@ -1152,7 +1142,7 @@
"+\tbit-mask = <0x3>;\n",
"+};\n",
"+\n",
- "+mcbsp3_gfclk: mcbsp3_gfclk\@4a004558 {\n",
+ "+mcbsp3_gfclk: mcbsp3_gfclk at 4a004558 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;\n",
@@ -1161,7 +1151,7 @@
"+\tbit-mask = <0x3>;\n",
"+};\n",
"+\n",
- "+mmc1_fclk_mux: mmc1_fclk_mux\@4a009628 {\n",
+ "+mmc1_fclk_mux: mmc1_fclk_mux at 4a009628 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;\n",
@@ -1170,7 +1160,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+mmc1_fclk: mmc1_fclk\@4a009628 {\n",
+ "+mmc1_fclk: mmc1_fclk at 4a009628 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&mmc1_fclk_mux>;\n",
@@ -1179,7 +1169,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+mmc2_fclk_mux: mmc2_fclk_mux\@4a009630 {\n",
+ "+mmc2_fclk_mux: mmc2_fclk_mux at 4a009630 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;\n",
@@ -1188,7 +1178,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+mmc2_fclk: mmc2_fclk\@4a009630 {\n",
+ "+mmc2_fclk: mmc2_fclk at 4a009630 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&mmc2_fclk_mux>;\n",
@@ -1197,7 +1187,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+timer10_gfclk_mux: timer10_gfclk_mux\@4a009028 {\n",
+ "+timer10_gfclk_mux: timer10_gfclk_mux at 4a009028 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&sys_clkin>, <&sys_32k_ck>;\n",
@@ -1206,7 +1196,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+timer11_gfclk_mux: timer11_gfclk_mux\@4a009030 {\n",
+ "+timer11_gfclk_mux: timer11_gfclk_mux at 4a009030 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&sys_clkin>, <&sys_32k_ck>;\n",
@@ -1215,7 +1205,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+timer1_gfclk_mux: timer1_gfclk_mux\@4ae07940 {\n",
+ "+timer1_gfclk_mux: timer1_gfclk_mux at 4ae07940 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&sys_clkin>, <&sys_32k_ck>;\n",
@@ -1224,7 +1214,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+timer2_gfclk_mux: timer2_gfclk_mux\@4a009038 {\n",
+ "+timer2_gfclk_mux: timer2_gfclk_mux at 4a009038 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&sys_clkin>, <&sys_32k_ck>;\n",
@@ -1233,7 +1223,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+timer3_gfclk_mux: timer3_gfclk_mux\@4a009040 {\n",
+ "+timer3_gfclk_mux: timer3_gfclk_mux at 4a009040 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&sys_clkin>, <&sys_32k_ck>;\n",
@@ -1242,7 +1232,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+timer4_gfclk_mux: timer4_gfclk_mux\@4a009048 {\n",
+ "+timer4_gfclk_mux: timer4_gfclk_mux at 4a009048 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&sys_clkin>, <&sys_32k_ck>;\n",
@@ -1251,7 +1241,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+timer5_gfclk_mux: timer5_gfclk_mux\@4a004568 {\n",
+ "+timer5_gfclk_mux: timer5_gfclk_mux at 4a004568 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;\n",
@@ -1260,7 +1250,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+timer6_gfclk_mux: timer6_gfclk_mux\@4a004570 {\n",
+ "+timer6_gfclk_mux: timer6_gfclk_mux at 4a004570 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;\n",
@@ -1269,7 +1259,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+timer7_gfclk_mux: timer7_gfclk_mux\@4a004578 {\n",
+ "+timer7_gfclk_mux: timer7_gfclk_mux at 4a004578 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;\n",
@@ -1278,7 +1268,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+timer8_gfclk_mux: timer8_gfclk_mux\@4a004580 {\n",
+ "+timer8_gfclk_mux: timer8_gfclk_mux at 4a004580 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;\n",
@@ -1287,7 +1277,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+timer9_gfclk_mux: timer9_gfclk_mux\@4a009050 {\n",
+ "+timer9_gfclk_mux: timer9_gfclk_mux at 4a009050 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&sys_clkin>, <&sys_32k_ck>;\n",
@@ -1296,7 +1286,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+auxclk0_src_mux_ck: auxclk0_src_mux_ck\@4ae0a310 {\n",
+ "+auxclk0_src_mux_ck: auxclk0_src_mux_ck at 4ae0a310 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;\n",
@@ -1305,7 +1295,7 @@
"+\tbit-mask = <0x3>;\n",
"+};\n",
"+\n",
- "+auxclk0_src_ck: auxclk0_src_ck\@4ae0a310 {\n",
+ "+auxclk0_src_ck: auxclk0_src_ck at 4ae0a310 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&auxclk0_src_mux_ck>;\n",
@@ -1313,7 +1303,7 @@
"+\treg = <0x4ae0a310 0x4>;\n",
"+};\n",
"+\n",
- "+auxclk0_ck: auxclk0_ck\@4ae0a310 {\n",
+ "+auxclk0_ck: auxclk0_ck at 4ae0a310 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&auxclk0_src_ck>;\n",
@@ -1322,7 +1312,7 @@
"+\tbit-mask = <0xf>;\n",
"+};\n",
"+\n",
- "+auxclk1_src_mux_ck: auxclk1_src_mux_ck\@4ae0a314 {\n",
+ "+auxclk1_src_mux_ck: auxclk1_src_mux_ck at 4ae0a314 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;\n",
@@ -1331,7 +1321,7 @@
"+\tbit-mask = <0x3>;\n",
"+};\n",
"+\n",
- "+auxclk1_src_ck: auxclk1_src_ck\@4ae0a314 {\n",
+ "+auxclk1_src_ck: auxclk1_src_ck at 4ae0a314 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&auxclk1_src_mux_ck>;\n",
@@ -1339,7 +1329,7 @@
"+\treg = <0x4ae0a314 0x4>;\n",
"+};\n",
"+\n",
- "+auxclk1_ck: auxclk1_ck\@4ae0a314 {\n",
+ "+auxclk1_ck: auxclk1_ck at 4ae0a314 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&auxclk1_src_ck>;\n",
@@ -1348,7 +1338,7 @@
"+\tbit-mask = <0xf>;\n",
"+};\n",
"+\n",
- "+auxclk2_src_mux_ck: auxclk2_src_mux_ck\@4ae0a318 {\n",
+ "+auxclk2_src_mux_ck: auxclk2_src_mux_ck at 4ae0a318 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;\n",
@@ -1357,7 +1347,7 @@
"+\tbit-mask = <0x3>;\n",
"+};\n",
"+\n",
- "+auxclk2_src_ck: auxclk2_src_ck\@4ae0a318 {\n",
+ "+auxclk2_src_ck: auxclk2_src_ck at 4ae0a318 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&auxclk2_src_mux_ck>;\n",
@@ -1365,7 +1355,7 @@
"+\treg = <0x4ae0a318 0x4>;\n",
"+};\n",
"+\n",
- "+auxclk2_ck: auxclk2_ck\@4ae0a318 {\n",
+ "+auxclk2_ck: auxclk2_ck at 4ae0a318 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&auxclk2_src_ck>;\n",
@@ -1374,7 +1364,7 @@
"+\tbit-mask = <0xf>;\n",
"+};\n",
"+\n",
- "+auxclk3_src_mux_ck: auxclk3_src_mux_ck\@4ae0a31c {\n",
+ "+auxclk3_src_mux_ck: auxclk3_src_mux_ck at 4ae0a31c {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;\n",
@@ -1383,7 +1373,7 @@
"+\tbit-mask = <0x3>;\n",
"+};\n",
"+\n",
- "+auxclk3_src_ck: auxclk3_src_ck\@4ae0a31c {\n",
+ "+auxclk3_src_ck: auxclk3_src_ck at 4ae0a31c {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&auxclk3_src_mux_ck>;\n",
@@ -1391,7 +1381,7 @@
"+\treg = <0x4ae0a31c 0x4>;\n",
"+};\n",
"+\n",
- "+auxclk3_ck: auxclk3_ck\@4ae0a31c {\n",
+ "+auxclk3_ck: auxclk3_ck at 4ae0a31c {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&auxclk3_src_ck>;\n",
@@ -1400,7 +1390,7 @@
"+\tbit-mask = <0xf>;\n",
"+};\n",
"+\n",
- "+auxclk4_src_mux_ck: auxclk4_src_mux_ck\@4ae0a320 {\n",
+ "+auxclk4_src_mux_ck: auxclk4_src_mux_ck at 4ae0a320 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;\n",
@@ -1409,7 +1399,7 @@
"+\tbit-mask = <0x3>;\n",
"+};\n",
"+\n",
- "+auxclk4_src_ck: auxclk4_src_ck\@4ae0a320 {\n",
+ "+auxclk4_src_ck: auxclk4_src_ck at 4ae0a320 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&auxclk4_src_mux_ck>;\n",
@@ -1417,7 +1407,7 @@
"+\treg = <0x4ae0a320 0x4>;\n",
"+};\n",
"+\n",
- "+auxclk4_ck: auxclk4_ck\@4ae0a320 {\n",
+ "+auxclk4_ck: auxclk4_ck at 4ae0a320 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&auxclk4_src_ck>;\n",
@@ -1426,7 +1416,7 @@
"+\tbit-mask = <0xf>;\n",
"+};\n",
"+\n",
- "+auxclkreq0_ck: auxclkreq0_ck\@4ae0a210 {\n",
+ "+auxclkreq0_ck: auxclkreq0_ck at 4ae0a210 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;\n",
@@ -1435,7 +1425,7 @@
"+\tbit-mask = <0x7>;\n",
"+};\n",
"+\n",
- "+auxclkreq1_ck: auxclkreq1_ck\@4ae0a214 {\n",
+ "+auxclkreq1_ck: auxclkreq1_ck at 4ae0a214 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;\n",
@@ -1444,7 +1434,7 @@
"+\tbit-mask = <0x7>;\n",
"+};\n",
"+\n",
- "+auxclkreq2_ck: auxclkreq2_ck\@4ae0a218 {\n",
+ "+auxclkreq2_ck: auxclkreq2_ck at 4ae0a218 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;\n",
@@ -1453,7 +1443,7 @@
"+\tbit-mask = <0x7>;\n",
"+};\n",
"+\n",
- "+auxclkreq3_ck: auxclkreq3_ck\@4ae0a21c {\n",
+ "+auxclkreq3_ck: auxclkreq3_ck at 4ae0a21c {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;\n",
@@ -1465,4 +1455,4 @@
"1.7.9.5"
]
-20af36ab863dcc89adc3debf7f1c6dcbe60acaf9599b21e1528f61baaf92c39d
+380619dbfea57ab34e148ea5f05fc949ce4dd5493299040bcb4ca329dddfc299
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