diff for duplicates of <1374564028-11352-29-git-send-email-t-kristo@ti.com>
diff --git a/a/1.txt b/N1/1.txt
index 4fcfe4f..528cfb8 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -54,7 +54,7 @@ index 0000000..1d85f45
+ * published by the Free Software Foundation.
+ */
+
-+gfx_l3_fck: gfx_l3_fck@48004b40 {
++gfx_l3_fck: gfx_l3_fck at 48004b40 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&l3_ick>;
@@ -76,7 +76,7 @@ index 0000000..1d85f45
+ clock-div = <1>;
+};
+
-+gfx_cg1_ck: gfx_cg1_ck@48004b00 {
++gfx_cg1_ck: gfx_cg1_ck at 48004b00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&gfx_l3_fck>;
@@ -85,7 +85,7 @@ index 0000000..1d85f45
+ ti,enable-bit = <1>;
+};
+
-+gfx_cg2_ck: gfx_cg2_ck@48004b00 {
++gfx_cg2_ck: gfx_cg2_ck at 48004b00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&gfx_l3_fck>;
@@ -94,7 +94,7 @@ index 0000000..1d85f45
+ ti,enable-bit = <2>;
+};
+
-+d2d_26m_fck: d2d_26m_fck@48004a00 {
++d2d_26m_fck: d2d_26m_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_ck>;
@@ -103,7 +103,7 @@ index 0000000..1d85f45
+ ti,enable-bit = <3>;
+};
+
-+fshostusb_fck: fshostusb_fck@48004a00 {
++fshostusb_fck: fshostusb_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_48m_fck>;
@@ -112,7 +112,7 @@ index 0000000..1d85f45
+ ti,enable-bit = <5>;
+};
+
-+ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1@48004a40 {
++ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1 at 48004a40 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&corex2_fck>;
@@ -122,7 +122,7 @@ index 0000000..1d85f45
+ bit-mask = <0xf>;
+};
+
-+ssi_ssr_fck_3430es1: ssi_ssr_fck_3430es1@48004a00 {
++ssi_ssr_fck_3430es1: ssi_ssr_fck_3430es1 at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&ssi_ssr_div_fck_3430es1>;
@@ -138,7 +138,7 @@ index 0000000..1d85f45
+ clock-div = <2>;
+};
+
-+hsotgusb_ick_3430es1: hsotgusb_ick_3430es1@48004a10 {
++hsotgusb_ick_3430es1: hsotgusb_ick_3430es1 at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&core_l3_ick>;
@@ -148,7 +148,7 @@ index 0000000..1d85f45
+ ti,iclk-no-wait;
+};
+
-+fac_ick: fac_ick@48004a10 {
++fac_ick: fac_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&core_l4_ick>;
@@ -165,7 +165,7 @@ index 0000000..1d85f45
+ clock-div = <1>;
+};
+
-+ssi_ick_3430es1: ssi_ick_3430es1@48004a10 {
++ssi_ick_3430es1: ssi_ick_3430es1 at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&ssi_l4_ick>;
@@ -175,7 +175,7 @@ index 0000000..1d85f45
+ ti,iclk-no-wait;
+};
+
-+usb_l4_div_ick: usb_l4_div_ick@48004a40 {
++usb_l4_div_ick: usb_l4_div_ick at 48004a40 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&l4_ick>;
@@ -185,7 +185,7 @@ index 0000000..1d85f45
+ index-starts-at-one;
+};
+
-+usb_l4_ick: usb_l4_ick@48004a10 {
++usb_l4_ick: usb_l4_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&usb_l4_div_ick>;
@@ -193,7 +193,7 @@ index 0000000..1d85f45
+ reg = <0x48004a10 0x4>;
+};
+
-+dss1_alwon_fck_3430es1: dss1_alwon_fck_3430es1@48004e00 {
++dss1_alwon_fck_3430es1: dss1_alwon_fck_3430es1 at 48004e00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll4_m4x2_ck>;
@@ -201,7 +201,7 @@ index 0000000..1d85f45
+ bit-shift = <0>;
+};
+
-+dss_ick_3430es1: dss_ick_3430es1@48004e10 {
++dss_ick_3430es1: dss_ick_3430es1 at 48004e10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&l4_ick>;
@@ -234,7 +234,7 @@ index 0000000..8da7ba1
+ clock-div = <1>;
+};
+
-+aes1_ick: aes1_ick@48004a14 {
++aes1_ick: aes1_ick at 48004a14 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&security_l4_ick2>;
@@ -242,7 +242,7 @@ index 0000000..8da7ba1
+ ti,enable-bit = <3>;
+};
+
-+rng_ick: rng_ick@48004a14 {
++rng_ick: rng_ick at 48004a14 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&security_l4_ick2>;
@@ -250,7 +250,7 @@ index 0000000..8da7ba1
+ ti,enable-bit = <2>;
+};
+
-+sha11_ick: sha11_ick@48004a14 {
++sha11_ick: sha11_ick at 48004a14 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&security_l4_ick2>;
@@ -258,7 +258,7 @@ index 0000000..8da7ba1
+ ti,enable-bit = <1>;
+};
+
-+des1_ick: des1_ick@48004a14 {
++des1_ick: des1_ick at 48004a14 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&security_l4_ick2>;
@@ -266,7 +266,7 @@ index 0000000..8da7ba1
+ ti,enable-bit = <0>;
+};
+
-+cam_mclk: cam_mclk@48004f00 {
++cam_mclk: cam_mclk at 48004f00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll4_m5x2_ck>;
@@ -275,7 +275,7 @@ index 0000000..8da7ba1
+ set-rate-parent;
+};
+
-+cam_ick: cam_ick@48004f10 {
++cam_ick: cam_ick at 48004f10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&l4_ick>;
@@ -285,7 +285,7 @@ index 0000000..8da7ba1
+ ti,iclk-no-wait;
+};
+
-+csi2_96m_fck: csi2_96m_fck@48004f00 {
++csi2_96m_fck: csi2_96m_fck at 48004f00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&core_96m_fck>;
@@ -301,7 +301,7 @@ index 0000000..8da7ba1
+ clock-div = <1>;
+};
+
-+pka_ick: pka_ick@48004a14 {
++pka_ick: pka_ick at 48004a14 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&security_l3_ick>;
@@ -309,7 +309,7 @@ index 0000000..8da7ba1
+ ti,enable-bit = <4>;
+};
+
-+icr_ick: icr_ick@48004a10 {
++icr_ick: icr_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&core_l4_ick>;
@@ -318,7 +318,7 @@ index 0000000..8da7ba1
+ ti,enable-bit = <29>;
+};
+
-+des2_ick: des2_ick@48004a10 {
++des2_ick: des2_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&core_l4_ick>;
@@ -327,7 +327,7 @@ index 0000000..8da7ba1
+ ti,enable-bit = <26>;
+};
+
-+mspro_ick: mspro_ick@48004a10 {
++mspro_ick: mspro_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&core_l4_ick>;
@@ -336,7 +336,7 @@ index 0000000..8da7ba1
+ ti,enable-bit = <23>;
+};
+
-+mailboxes_ick: mailboxes_ick@48004a10 {
++mailboxes_ick: mailboxes_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&core_l4_ick>;
@@ -353,7 +353,7 @@ index 0000000..8da7ba1
+ clock-div = <1>;
+};
+
-+sr1_fck: sr1_fck@48004c00 {
++sr1_fck: sr1_fck at 48004c00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_ck>;
@@ -362,7 +362,7 @@ index 0000000..8da7ba1
+ ti,enable-bit = <6>;
+};
+
-+sr2_fck: sr2_fck@48004c00 {
++sr2_fck: sr2_fck at 48004c00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_ck>;
@@ -379,7 +379,7 @@ index 0000000..8da7ba1
+ clock-div = <1>;
+};
+
-+dpll2_fck: dpll2_fck@48004040 {
++dpll2_fck: dpll2_fck at 48004040 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&core_ck>;
@@ -389,7 +389,7 @@ index 0000000..8da7ba1
+ index-starts-at-one;
+};
+
-+dpll2_ck: dpll2_ck@48004004 {
++dpll2_ck: dpll2_ck at 48004004 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-clock";
+ clocks = <&sys_ck>;
@@ -403,7 +403,7 @@ index 0000000..8da7ba1
+ ti,recal-st-bit = <0x8>;
+};
+
-+dpll2_m2_ck: dpll2_m2_ck@48004044 {
++dpll2_m2_ck: dpll2_m2_ck at 48004044 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll2_ck>;
@@ -412,7 +412,7 @@ index 0000000..8da7ba1
+ index-starts-at-one;
+};
+
-+iva2_ck: iva2_ck@48004000 {
++iva2_ck: iva2_ck at 48004000 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll2_m2_ck>;
@@ -421,7 +421,7 @@ index 0000000..8da7ba1
+ ti,enable-bit = <0>;
+};
+
-+modem_fck: modem_fck@48004a00 {
++modem_fck: modem_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&sys_ck>;
@@ -430,7 +430,7 @@ index 0000000..8da7ba1
+ ti,enable-bit = <31>;
+};
+
-+sad2d_ick: sad2d_ick@48004a10 {
++sad2d_ick: sad2d_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&l3_ick>;
@@ -439,7 +439,7 @@ index 0000000..8da7ba1
+ ti,enable-bit = <3>;
+};
+
-+mad2d_ick: mad2d_ick@48004a18 {
++mad2d_ick: mad2d_ick at 48004a18 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&l3_ick>;
@@ -448,7 +448,7 @@ index 0000000..8da7ba1
+ ti,enable-bit = <3>;
+};
+
-+mspro_fck: mspro_fck@48004a00 {
++mspro_fck: mspro_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_96m_fck>;
@@ -490,7 +490,7 @@ index 0000000..e0bdfb3
+ * published by the Free Software Foundation.
+ */
+
-+dpll5_ck: dpll5_ck@48004d04 {
++dpll5_ck: dpll5_ck at 48004d04 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-clock";
+ clocks = <&sys_ck>;
@@ -504,7 +504,7 @@ index 0000000..e0bdfb3
+ ti,recal-st-bit = <0x19>;
+};
+
-+dpll5_m2_ck: dpll5_m2_ck@48004d50 {
++dpll5_m2_ck: dpll5_m2_ck at 48004d50 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll5_ck>;
@@ -569,7 +569,7 @@ index 0000000..e0bdfb3
+ clock-div = <5>;
+};
+
-+sgx_mux_fck: sgx_mux_fck@48004b40 {
++sgx_mux_fck: sgx_mux_fck at 48004b40 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>;
@@ -578,7 +578,7 @@ index 0000000..e0bdfb3
+ bit-mask = <0x7>;
+};
+
-+sgx_fck: sgx_fck@48004b00 {
++sgx_fck: sgx_fck at 48004b00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sgx_mux_fck>;
@@ -586,7 +586,7 @@ index 0000000..e0bdfb3
+ reg = <0x48004b00 0x4>;
+};
+
-+sgx_ick: sgx_ick@48004b10 {
++sgx_ick: sgx_ick at 48004b10 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l3_ick>;
@@ -595,7 +595,7 @@ index 0000000..e0bdfb3
+ ti,enable-bit = <0>;
+};
+
-+cpefuse_fck: cpefuse_fck@48004a08 {
++cpefuse_fck: cpefuse_fck at 48004a08 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_ck>;
@@ -603,7 +603,7 @@ index 0000000..e0bdfb3
+ bit-shift = <0>;
+};
+
-+ts_fck: ts_fck@48004a08 {
++ts_fck: ts_fck at 48004a08 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&omap_32k_fck>;
@@ -611,7 +611,7 @@ index 0000000..e0bdfb3
+ bit-shift = <1>;
+};
+
-+usbtll_fck: usbtll_fck@48004a08 {
++usbtll_fck: usbtll_fck at 48004a08 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll5_m2_ck>;
@@ -620,7 +620,7 @@ index 0000000..e0bdfb3
+ ti,enable-bit = <2>;
+};
+
-+usbtll_ick: usbtll_ick@48004a18 {
++usbtll_ick: usbtll_ick at 48004a18 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&core_l4_ick>;
@@ -629,7 +629,7 @@ index 0000000..e0bdfb3
+ ti,enable-bit = <2>;
+};
+
-+mmchs3_ick: mmchs3_ick@48004a10 {
++mmchs3_ick: mmchs3_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&core_l4_ick>;
@@ -638,7 +638,7 @@ index 0000000..e0bdfb3
+ ti,enable-bit = <30>;
+};
+
-+mmchs3_fck: mmchs3_fck@48004a00 {
++mmchs3_fck: mmchs3_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_96m_fck>;
@@ -647,7 +647,7 @@ index 0000000..e0bdfb3
+ ti,enable-bit = <30>;
+};
+
-+dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2@48004e00 {
++dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2 at 48004e00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll4_m4x2_ck>;
@@ -657,7 +657,7 @@ index 0000000..e0bdfb3
+ ti,dss-clk;
+};
+
-+dss_ick_3430es2: dss_ick_3430es2@48004e10 {
++dss_ick_3430es2: dss_ick_3430es2 at 48004e10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&l4_ick>;
@@ -667,7 +667,7 @@ index 0000000..e0bdfb3
+ ti,iclk-dss;
+};
+
-+usbhost_120m_fck: usbhost_120m_fck@48005400 {
++usbhost_120m_fck: usbhost_120m_fck at 48005400 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll5_m2_ck>;
@@ -675,7 +675,7 @@ index 0000000..e0bdfb3
+ bit-shift = <1>;
+};
+
-+usbhost_48m_fck: usbhost_48m_fck@48005400 {
++usbhost_48m_fck: usbhost_48m_fck at 48005400 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&omap_48m_fck>;
@@ -685,7 +685,7 @@ index 0000000..e0bdfb3
+ ti,dss-clk;
+};
+
-+usbhost_ick: usbhost_ick@48005410 {
++usbhost_ick: usbhost_ick at 48005410 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&l4_ick>;
@@ -710,7 +710,7 @@ index 0000000..a52faa4
+ * published by the Free Software Foundation.
+ */
+
-+dpll4_ck: dpll4_ck@48004d00 {
++dpll4_ck: dpll4_ck at 48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-clock";
+ clocks = <&sys_ck>;
@@ -730,7 +730,7 @@ index 0000000..a52faa4
+ ti,dpll-peripheral;
+};
+
-+dpll4_m2x2_ck: dpll4_m2x2_ck@48004d00 {
++dpll4_m2x2_ck: dpll4_m2x2_ck at 48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll4_m2x2_mul_ck>;
@@ -740,7 +740,7 @@ index 0000000..a52faa4
+ ti,hsdiv-restore;
+};
+
-+dpll3_m3x2_ck: dpll3_m3x2_ck@48004d00 {
++dpll3_m3x2_ck: dpll3_m3x2_ck at 48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll3_m3x2_mul_ck>;
@@ -750,7 +750,7 @@ index 0000000..a52faa4
+ ti,hsdiv-restore;
+};
+
-+dpll4_m3x2_ck: dpll4_m3x2_ck@48004d00 {
++dpll4_m3x2_ck: dpll4_m3x2_ck at 48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll4_m3x2_mul_ck>;
@@ -760,7 +760,7 @@ index 0000000..a52faa4
+ ti,hsdiv-restore;
+};
+
-+dpll4_m5x2_ck: dpll4_m5x2_ck@48004d00 {
++dpll4_m5x2_ck: dpll4_m5x2_ck at 48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll4_m5x2_mul_ck>;
@@ -771,7 +771,7 @@ index 0000000..a52faa4
+ set-bit-to-disable;
+};
+
-+dpll4_m6x2_ck: dpll4_m6x2_ck@48004d00 {
++dpll4_m6x2_ck: dpll4_m6x2_ck at 48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll4_m6x2_mul_ck>;
@@ -789,7 +789,7 @@ index 0000000..a52faa4
+ clock-div = <1>;
+};
+
-+uart4_fck: uart4_fck@48005000 {
++uart4_fck: uart4_fck at 48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&per_48m_fck>;
@@ -813,7 +813,7 @@ index 0000000..0b93647
+ * published by the Free Software Foundation.
+ */
+
-+ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2@48004a40 {
++ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 at 48004a40 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&corex2_fck>;
@@ -823,7 +823,7 @@ index 0000000..0b93647
+ bit-mask = <0xf>;
+};
+
-+ssi_ssr_fck_3430es2: ssi_ssr_fck_3430es2@48004a00 {
++ssi_ssr_fck_3430es2: ssi_ssr_fck_3430es2 at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&ssi_ssr_div_fck_3430es2>;
@@ -839,7 +839,7 @@ index 0000000..0b93647
+ clock-div = <2>;
+};
+
-+hsotgusb_ick_3430es2: hsotgusb_ick_3430es2@48004a10 {
++hsotgusb_ick_3430es2: hsotgusb_ick_3430es2 at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&core_l3_ick>;
@@ -857,7 +857,7 @@ index 0000000..0b93647
+ clock-div = <1>;
+};
+
-+ssi_ick_3430es2: ssi_ick_3430es2@48004a10 {
++ssi_ick_3430es2: ssi_ick_3430es2 at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&ssi_l4_ick>;
@@ -867,7 +867,7 @@ index 0000000..0b93647
+ ti,iclk-ssi;
+};
+
-+dpll5_ck: dpll5_ck@48004d04 {
++dpll5_ck: dpll5_ck at 48004d04 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-clock";
+ clocks = <&sys_ck>;
@@ -881,7 +881,7 @@ index 0000000..0b93647
+ ti,recal-st-bit = <0x19>;
+};
+
-+dpll5_m2_ck: dpll5_m2_ck@48004d50 {
++dpll5_m2_ck: dpll5_m2_ck at 48004d50 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll5_ck>;
@@ -962,7 +962,7 @@ index 0000000..0b93647
+ clock-div = <16>;
+};
+
-+usim_mux_fck: usim_mux_fck@48004c40 {
++usim_mux_fck: usim_mux_fck at 48004c40 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_ck>, <&dpll5_m2_d20_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>;
@@ -972,7 +972,7 @@ index 0000000..0b93647
+ bit-mask = <0xf>;
+};
+
-+usim_fck: usim_fck@48004c00 {
++usim_fck: usim_fck at 48004c00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&usim_mux_fck>;
@@ -980,7 +980,7 @@ index 0000000..0b93647
+ reg = <0x48004c00 0x4>;
+};
+
-+usim_ick: usim_ick@48004c10 {
++usim_ick: usim_ick at 48004c10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&wkup_l4_ick>;
@@ -1071,7 +1071,7 @@ index 0000000..18a723f
+ clock-frequency = <16800000>;
+};
+
-+osc_sys_ck: osc_sys_ck@48306d40 {
++osc_sys_ck: osc_sys_ck at 48306d40 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>;
@@ -1079,7 +1079,7 @@ index 0000000..18a723f
+ bit-mask = <0x7>;
+};
+
-+sys_ck: sys_ck@48307270 {
++sys_ck: sys_ck at 48307270 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&osc_sys_ck>;
@@ -1089,7 +1089,7 @@ index 0000000..18a723f
+ index-starts-at-one;
+};
+
-+dpll4_ck: dpll4_ck@48004d00 {
++dpll4_ck: dpll4_ck at 48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-clock";
+ clocks = <&sys_ck>;
@@ -1107,7 +1107,7 @@ index 0000000..18a723f
+ ti,dpll-peripheral;
+};
+
-+dpll4_m2_ck: dpll4_m2_ck@48004d48 {
++dpll4_m2_ck: dpll4_m2_ck at 48004d48 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll4_ck>;
@@ -1124,7 +1124,7 @@ index 0000000..18a723f
+ clock-div = <1>;
+};
+
-+dpll4_m2x2_ck: dpll4_m2x2_ck@48004d00 {
++dpll4_m2x2_ck: dpll4_m2x2_ck at 48004d00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll4_m2x2_mul_ck>;
@@ -1141,7 +1141,7 @@ index 0000000..18a723f
+ clock-div = <1>;
+};
+
-+dpll3_ck: dpll3_ck@48004d00 {
++dpll3_ck: dpll3_ck at 48004d00 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-clock";
+ clocks = <&sys_ck>;
@@ -1155,7 +1155,7 @@ index 0000000..18a723f
+ ti,dpll-core;
+};
+
-+dpll3_m3_ck: dpll3_m3_ck@48005140 {
++dpll3_m3_ck: dpll3_m3_ck at 48005140 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll3_ck>;
@@ -1173,7 +1173,7 @@ index 0000000..18a723f
+ clock-div = <1>;
+};
+
-+dpll3_m3x2_ck: dpll3_m3x2_ck@48004d00 {
++dpll3_m3x2_ck: dpll3_m3x2_ck at 48004d00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll3_m3x2_mul_ck>;
@@ -1202,7 +1202,7 @@ index 0000000..18a723f
+ clock-frequency = <0x0>;
+};
+
-+sys_clkout1: sys_clkout1@48306d70 {
++sys_clkout1: sys_clkout1 at 48306d70 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&osc_sys_ck>;
@@ -1210,7 +1210,7 @@ index 0000000..18a723f
+ bit-shift = <7>;
+};
+
-+dpll1_ck: dpll1_ck@48004904 {
++dpll1_ck: dpll1_ck at 48004904 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-clock";
+ clocks = <&sys_ck>;
@@ -1231,7 +1231,7 @@ index 0000000..18a723f
+ clock-div = <1>;
+};
+
-+dpll1_x2m2_ck: dpll1_x2m2_ck@48004944 {
++dpll1_x2m2_ck: dpll1_x2m2_ck at 48004944 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll1_x2_ck>;
@@ -1240,7 +1240,7 @@ index 0000000..18a723f
+ index-starts-at-one;
+};
+
-+dpll3_m2_ck: dpll3_m2_ck@48004d40 {
++dpll3_m2_ck: dpll3_m2_ck at 48004d40 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll3_ck>;
@@ -1290,7 +1290,7 @@ index 0000000..18a723f
+ clock-div = <1>;
+};
+
-+omap_96m_fck: omap_96m_fck@48004d40 {
++omap_96m_fck: omap_96m_fck at 48004d40 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&cm_96m_fck>, <&sys_ck>;
@@ -1299,7 +1299,7 @@ index 0000000..18a723f
+ bit-mask = <0x1>;
+};
+
-+dpll4_m3_ck: dpll4_m3_ck@48004e40 {
++dpll4_m3_ck: dpll4_m3_ck at 48004e40 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll4_ck>;
@@ -1317,7 +1317,7 @@ index 0000000..18a723f
+ clock-div = <1>;
+};
+
-+dpll4_m3x2_ck: dpll4_m3x2_ck@48004d00 {
++dpll4_m3x2_ck: dpll4_m3x2_ck at 48004d00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll4_m3x2_mul_ck>;
@@ -1326,7 +1326,7 @@ index 0000000..18a723f
+ set-bit-to-disable;
+};
+
-+omap_54m_fck: omap_54m_fck@48004d40 {
++omap_54m_fck: omap_54m_fck at 48004d40 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&dpll4_m3x2_ck>, <&sys_altclk>;
@@ -1343,7 +1343,7 @@ index 0000000..18a723f
+ clock-div = <2>;
+};
+
-+omap_48m_fck: omap_48m_fck@48004d40 {
++omap_48m_fck: omap_48m_fck at 48004d40 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&cm_96m_d2_fck>, <&sys_altclk>;
@@ -1361,7 +1361,7 @@ index 0000000..18a723f
+ clock-div = <4>;
+};
+
-+dpll4_m4_ck: dpll4_m4_ck@48004e40 {
++dpll4_m4_ck: dpll4_m4_ck at 48004e40 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll4_ck>;
@@ -1378,7 +1378,7 @@ index 0000000..18a723f
+ clock-div = <1>;
+};
+
-+dpll4_m4x2_ck: dpll4_m4x2_ck@48004d00 {
++dpll4_m4x2_ck: dpll4_m4x2_ck at 48004d00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll4_m4x2_mul_ck>;
@@ -1387,7 +1387,7 @@ index 0000000..18a723f
+ set-bit-to-disable;
+};
+
-+dpll4_m5_ck: dpll4_m5_ck@48004f40 {
++dpll4_m5_ck: dpll4_m5_ck at 48004f40 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll4_ck>;
@@ -1404,7 +1404,7 @@ index 0000000..18a723f
+ clock-div = <1>;
+};
+
-+dpll4_m5x2_ck: dpll4_m5x2_ck@48004d00 {
++dpll4_m5x2_ck: dpll4_m5x2_ck at 48004d00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll4_m5x2_mul_ck>;
@@ -1413,7 +1413,7 @@ index 0000000..18a723f
+ set-bit-to-disable;
+};
+
-+dpll4_m6_ck: dpll4_m6_ck@48005140 {
++dpll4_m6_ck: dpll4_m6_ck at 48005140 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&dpll4_ck>;
@@ -1431,7 +1431,7 @@ index 0000000..18a723f
+ clock-div = <1>;
+};
+
-+dpll4_m6x2_ck: dpll4_m6x2_ck@48004d00 {
++dpll4_m6x2_ck: dpll4_m6x2_ck at 48004d00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&dpll4_m6x2_mul_ck>;
@@ -1448,7 +1448,7 @@ index 0000000..18a723f
+ clock-div = <1>;
+};
+
-+clkout2_src_mux_ck: clkout2_src_mux_ck@48004d70 {
++clkout2_src_mux_ck: clkout2_src_mux_ck at 48004d70 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>;
@@ -1456,7 +1456,7 @@ index 0000000..18a723f
+ bit-mask = <0x3>;
+};
+
-+clkout2_src_ck: clkout2_src_ck@48004d70 {
++clkout2_src_ck: clkout2_src_ck at 48004d70 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&clkout2_src_mux_ck>;
@@ -1464,7 +1464,7 @@ index 0000000..18a723f
+ reg = <0x48004d70 0x4>;
+};
+
-+sys_clkout2: sys_clkout2@48004d70 {
++sys_clkout2: sys_clkout2 at 48004d70 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&clkout2_src_ck>;
@@ -1482,7 +1482,7 @@ index 0000000..18a723f
+ clock-div = <1>;
+};
+
-+dpll1_fck: dpll1_fck@48004940 {
++dpll1_fck: dpll1_fck at 48004940 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&core_ck>;
@@ -1500,7 +1500,7 @@ index 0000000..18a723f
+ clock-div = <1>;
+};
+
-+arm_fck: arm_fck@48004924 {
++arm_fck: arm_fck at 48004924 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&mpu_ck>;
@@ -1516,7 +1516,7 @@ index 0000000..18a723f
+ clock-div = <1>;
+};
+
-+l3_ick: l3_ick@48004a40 {
++l3_ick: l3_ick at 48004a40 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&core_ck>;
@@ -1525,7 +1525,7 @@ index 0000000..18a723f
+ index-starts-at-one;
+};
+
-+l4_ick: l4_ick@48004a40 {
++l4_ick: l4_ick at 48004a40 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&l3_ick>;
@@ -1535,7 +1535,7 @@ index 0000000..18a723f
+ index-starts-at-one;
+};
+
-+rm_ick: rm_ick@48004c40 {
++rm_ick: rm_ick at 48004c40 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&l4_ick>;
@@ -1545,7 +1545,7 @@ index 0000000..18a723f
+ index-starts-at-one;
+};
+
-+gpt10_mux_fck: gpt10_mux_fck@48004a40 {
++gpt10_mux_fck: gpt10_mux_fck at 48004a40 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
@@ -1554,7 +1554,7 @@ index 0000000..18a723f
+ bit-mask = <0x1>;
+};
+
-+gpt10_fck: gpt10_fck@48004a00 {
++gpt10_fck: gpt10_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&gpt10_mux_fck>;
@@ -1562,7 +1562,7 @@ index 0000000..18a723f
+ reg = <0x48004a00 0x4>;
+};
+
-+gpt11_mux_fck: gpt11_mux_fck@48004a40 {
++gpt11_mux_fck: gpt11_mux_fck at 48004a40 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
@@ -1571,7 +1571,7 @@ index 0000000..18a723f
+ bit-mask = <0x1>;
+};
+
-+gpt11_fck: gpt11_fck@48004a00 {
++gpt11_fck: gpt11_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&gpt11_mux_fck>;
@@ -1587,7 +1587,7 @@ index 0000000..18a723f
+ clock-div = <1>;
+};
+
-+mmchs2_fck: mmchs2_fck@48004a00 {
++mmchs2_fck: mmchs2_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_96m_fck>;
@@ -1596,7 +1596,7 @@ index 0000000..18a723f
+ ti,enable-bit = <25>;
+};
+
-+mmchs1_fck: mmchs1_fck@48004a00 {
++mmchs1_fck: mmchs1_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_96m_fck>;
@@ -1605,7 +1605,7 @@ index 0000000..18a723f
+ ti,enable-bit = <24>;
+};
+
-+i2c3_fck: i2c3_fck@48004a00 {
++i2c3_fck: i2c3_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_96m_fck>;
@@ -1614,7 +1614,7 @@ index 0000000..18a723f
+ ti,enable-bit = <17>;
+};
+
-+i2c2_fck: i2c2_fck@48004a00 {
++i2c2_fck: i2c2_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_96m_fck>;
@@ -1623,7 +1623,7 @@ index 0000000..18a723f
+ ti,enable-bit = <16>;
+};
+
-+i2c1_fck: i2c1_fck@48004a00 {
++i2c1_fck: i2c1_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_96m_fck>;
@@ -1632,7 +1632,7 @@ index 0000000..18a723f
+ ti,enable-bit = <15>;
+};
+
-+mcbsp5_mux_fck: mcbsp5_mux_fck@480022d8 {
++mcbsp5_mux_fck: mcbsp5_mux_fck at 480022d8 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&core_96m_fck>, <&mcbsp_clks>;
@@ -1641,7 +1641,7 @@ index 0000000..18a723f
+ bit-mask = <0x1>;
+};
+
-+mcbsp5_fck: mcbsp5_fck@48004a00 {
++mcbsp5_fck: mcbsp5_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&mcbsp5_mux_fck>;
@@ -1649,7 +1649,7 @@ index 0000000..18a723f
+ reg = <0x48004a00 0x4>;
+};
+
-+mcbsp1_mux_fck: mcbsp1_mux_fck@48002274 {
++mcbsp1_mux_fck: mcbsp1_mux_fck at 48002274 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&core_96m_fck>, <&mcbsp_clks>;
@@ -1658,7 +1658,7 @@ index 0000000..18a723f
+ bit-mask = <0x1>;
+};
+
-+mcbsp1_fck: mcbsp1_fck@48004a00 {
++mcbsp1_fck: mcbsp1_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&mcbsp1_mux_fck>;
@@ -1674,7 +1674,7 @@ index 0000000..18a723f
+ clock-div = <1>;
+};
+
-+mcspi4_fck: mcspi4_fck@48004a00 {
++mcspi4_fck: mcspi4_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_48m_fck>;
@@ -1683,7 +1683,7 @@ index 0000000..18a723f
+ ti,enable-bit = <21>;
+};
+
-+mcspi3_fck: mcspi3_fck@48004a00 {
++mcspi3_fck: mcspi3_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_48m_fck>;
@@ -1692,7 +1692,7 @@ index 0000000..18a723f
+ ti,enable-bit = <20>;
+};
+
-+mcspi2_fck: mcspi2_fck@48004a00 {
++mcspi2_fck: mcspi2_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_48m_fck>;
@@ -1701,7 +1701,7 @@ index 0000000..18a723f
+ ti,enable-bit = <19>;
+};
+
-+mcspi1_fck: mcspi1_fck@48004a00 {
++mcspi1_fck: mcspi1_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_48m_fck>;
@@ -1710,7 +1710,7 @@ index 0000000..18a723f
+ ti,enable-bit = <18>;
+};
+
-+uart2_fck: uart2_fck@48004a00 {
++uart2_fck: uart2_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_48m_fck>;
@@ -1719,7 +1719,7 @@ index 0000000..18a723f
+ ti,enable-bit = <14>;
+};
+
-+uart1_fck: uart1_fck@48004a00 {
++uart1_fck: uart1_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_48m_fck>;
@@ -1736,7 +1736,7 @@ index 0000000..18a723f
+ clock-div = <1>;
+};
+
-+hdq_fck: hdq_fck@48004a00 {
++hdq_fck: hdq_fck at 48004a00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_12m_fck>;
@@ -1753,7 +1753,7 @@ index 0000000..18a723f
+ clock-div = <1>;
+};
+
-+sdrc_ick: sdrc_ick@48004a10 {
++sdrc_ick: sdrc_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_l3_ick>;
@@ -1778,7 +1778,7 @@ index 0000000..18a723f
+ clock-div = <1>;
+};
+
-+mmchs2_ick: mmchs2_ick@48004a10 {
++mmchs2_ick: mmchs2_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&core_l4_ick>;
@@ -1787,7 +1787,7 @@ index 0000000..18a723f
+ ti,enable-bit = <25>;
+};
+
-+mmchs1_ick: mmchs1_ick@48004a10 {
++mmchs1_ick: mmchs1_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&core_l4_ick>;
@@ -1796,7 +1796,7 @@ index 0000000..18a723f
+ ti,enable-bit = <24>;
+};
+
-+hdq_ick: hdq_ick@48004a10 {
++hdq_ick: hdq_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&core_l4_ick>;
@@ -1805,7 +1805,7 @@ index 0000000..18a723f
+ ti,enable-bit = <22>;
+};
+
-+mcspi4_ick: mcspi4_ick@48004a10 {
++mcspi4_ick: mcspi4_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&core_l4_ick>;
@@ -1814,7 +1814,7 @@ index 0000000..18a723f
+ ti,enable-bit = <21>;
+};
+
-+mcspi3_ick: mcspi3_ick@48004a10 {
++mcspi3_ick: mcspi3_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&core_l4_ick>;
@@ -1823,7 +1823,7 @@ index 0000000..18a723f
+ ti,enable-bit = <20>;
+};
+
-+mcspi2_ick: mcspi2_ick@48004a10 {
++mcspi2_ick: mcspi2_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&core_l4_ick>;
@@ -1832,7 +1832,7 @@ index 0000000..18a723f
+ ti,enable-bit = <19>;
+};
+
-+mcspi1_ick: mcspi1_ick@48004a10 {
++mcspi1_ick: mcspi1_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&core_l4_ick>;
@@ -1841,7 +1841,7 @@ index 0000000..18a723f
+ ti,enable-bit = <18>;
+};
+
-+i2c3_ick: i2c3_ick@48004a10 {
++i2c3_ick: i2c3_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&core_l4_ick>;
@@ -1850,7 +1850,7 @@ index 0000000..18a723f
+ ti,enable-bit = <17>;
+};
+
-+i2c2_ick: i2c2_ick@48004a10 {
++i2c2_ick: i2c2_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&core_l4_ick>;
@@ -1859,7 +1859,7 @@ index 0000000..18a723f
+ ti,enable-bit = <16>;
+};
+
-+i2c1_ick: i2c1_ick@48004a10 {
++i2c1_ick: i2c1_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&core_l4_ick>;
@@ -1868,7 +1868,7 @@ index 0000000..18a723f
+ ti,enable-bit = <15>;
+};
+
-+uart2_ick: uart2_ick@48004a10 {
++uart2_ick: uart2_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&core_l4_ick>;
@@ -1877,7 +1877,7 @@ index 0000000..18a723f
+ ti,enable-bit = <14>;
+};
+
-+uart1_ick: uart1_ick@48004a10 {
++uart1_ick: uart1_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&core_l4_ick>;
@@ -1886,7 +1886,7 @@ index 0000000..18a723f
+ ti,enable-bit = <13>;
+};
+
-+gpt11_ick: gpt11_ick@48004a10 {
++gpt11_ick: gpt11_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&core_l4_ick>;
@@ -1895,7 +1895,7 @@ index 0000000..18a723f
+ ti,enable-bit = <12>;
+};
+
-+gpt10_ick: gpt10_ick@48004a10 {
++gpt10_ick: gpt10_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&core_l4_ick>;
@@ -1904,7 +1904,7 @@ index 0000000..18a723f
+ ti,enable-bit = <11>;
+};
+
-+mcbsp5_ick: mcbsp5_ick@48004a10 {
++mcbsp5_ick: mcbsp5_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&core_l4_ick>;
@@ -1913,7 +1913,7 @@ index 0000000..18a723f
+ ti,enable-bit = <10>;
+};
+
-+mcbsp1_ick: mcbsp1_ick@48004a10 {
++mcbsp1_ick: mcbsp1_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&core_l4_ick>;
@@ -1922,7 +1922,7 @@ index 0000000..18a723f
+ ti,enable-bit = <9>;
+};
+
-+omapctrl_ick: omapctrl_ick@48004a10 {
++omapctrl_ick: omapctrl_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&core_l4_ick>;
@@ -1931,7 +1931,7 @@ index 0000000..18a723f
+ ti,enable-bit = <6>;
+};
+
-+dss_tv_fck: dss_tv_fck@48004e00 {
++dss_tv_fck: dss_tv_fck at 48004e00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&omap_54m_fck>;
@@ -1939,7 +1939,7 @@ index 0000000..18a723f
+ bit-shift = <2>;
+};
+
-+dss_96m_fck: dss_96m_fck@48004e00 {
++dss_96m_fck: dss_96m_fck at 48004e00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&omap_96m_fck>;
@@ -1947,7 +1947,7 @@ index 0000000..18a723f
+ bit-shift = <2>;
+};
+
-+dss2_alwon_fck: dss2_alwon_fck@48004e00 {
++dss2_alwon_fck: dss2_alwon_fck at 48004e00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&sys_ck>;
@@ -1955,7 +1955,7 @@ index 0000000..18a723f
+ bit-shift = <1>;
+};
+
-+gpt1_mux_fck: gpt1_mux_fck@48004c40 {
++gpt1_mux_fck: gpt1_mux_fck at 48004c40 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
@@ -1963,7 +1963,7 @@ index 0000000..18a723f
+ bit-mask = <0x1>;
+};
+
-+gpt1_fck: gpt1_fck@48004c00 {
++gpt1_fck: gpt1_fck at 48004c00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&gpt1_mux_fck>;
@@ -1971,7 +1971,7 @@ index 0000000..18a723f
+ reg = <0x48004c00 0x4>;
+};
+
-+aes2_ick: aes2_ick@48004a10 {
++aes2_ick: aes2_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&core_l4_ick>;
@@ -1988,7 +1988,7 @@ index 0000000..18a723f
+ clock-div = <1>;
+};
+
-+gpio1_dbck: gpio1_dbck@48004c00 {
++gpio1_dbck: gpio1_dbck at 48004c00 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&wkup_32k_fck>;
@@ -1996,7 +1996,7 @@ index 0000000..18a723f
+ bit-shift = <3>;
+};
+
-+sha12_ick: sha12_ick@48004a10 {
++sha12_ick: sha12_ick at 48004a10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&core_l4_ick>;
@@ -2005,7 +2005,7 @@ index 0000000..18a723f
+ ti,enable-bit = <27>;
+};
+
-+wdt2_fck: wdt2_fck@48004c00 {
++wdt2_fck: wdt2_fck at 48004c00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&wkup_32k_fck>;
@@ -2022,7 +2022,7 @@ index 0000000..18a723f
+ clock-div = <1>;
+};
+
-+wdt2_ick: wdt2_ick@48004c10 {
++wdt2_ick: wdt2_ick at 48004c10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&wkup_l4_ick>;
@@ -2031,7 +2031,7 @@ index 0000000..18a723f
+ ti,enable-bit = <5>;
+};
+
-+wdt1_ick: wdt1_ick@48004c10 {
++wdt1_ick: wdt1_ick at 48004c10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&wkup_l4_ick>;
@@ -2040,7 +2040,7 @@ index 0000000..18a723f
+ ti,enable-bit = <4>;
+};
+
-+gpio1_ick: gpio1_ick@48004c10 {
++gpio1_ick: gpio1_ick at 48004c10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&wkup_l4_ick>;
@@ -2049,7 +2049,7 @@ index 0000000..18a723f
+ ti,enable-bit = <3>;
+};
+
-+omap_32ksync_ick: omap_32ksync_ick@48004c10 {
++omap_32ksync_ick: omap_32ksync_ick at 48004c10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&wkup_l4_ick>;
@@ -2058,7 +2058,7 @@ index 0000000..18a723f
+ ti,enable-bit = <2>;
+};
+
-+gpt12_ick: gpt12_ick@48004c10 {
++gpt12_ick: gpt12_ick at 48004c10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&wkup_l4_ick>;
@@ -2067,7 +2067,7 @@ index 0000000..18a723f
+ ti,enable-bit = <1>;
+};
+
-+gpt1_ick: gpt1_ick@48004c10 {
++gpt1_ick: gpt1_ick at 48004c10 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&wkup_l4_ick>;
@@ -2092,7 +2092,7 @@ index 0000000..18a723f
+ clock-div = <1>;
+};
+
-+uart3_fck: uart3_fck@48005000 {
++uart3_fck: uart3_fck at 48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&per_48m_fck>;
@@ -2101,7 +2101,7 @@ index 0000000..18a723f
+ ti,enable-bit = <11>;
+};
+
-+gpt2_mux_fck: gpt2_mux_fck@48005040 {
++gpt2_mux_fck: gpt2_mux_fck at 48005040 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
@@ -2109,7 +2109,7 @@ index 0000000..18a723f
+ bit-mask = <0x1>;
+};
+
-+gpt2_fck: gpt2_fck@48005000 {
++gpt2_fck: gpt2_fck at 48005000 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&gpt2_mux_fck>;
@@ -2117,7 +2117,7 @@ index 0000000..18a723f
+ reg = <0x48005000 0x4>;
+};
+
-+gpt3_mux_fck: gpt3_mux_fck@48005040 {
++gpt3_mux_fck: gpt3_mux_fck at 48005040 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
@@ -2126,7 +2126,7 @@ index 0000000..18a723f
+ bit-mask = <0x1>;
+};
+
-+gpt3_fck: gpt3_fck@48005000 {
++gpt3_fck: gpt3_fck at 48005000 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&gpt3_mux_fck>;
@@ -2134,7 +2134,7 @@ index 0000000..18a723f
+ reg = <0x48005000 0x4>;
+};
+
-+gpt4_mux_fck: gpt4_mux_fck@48005040 {
++gpt4_mux_fck: gpt4_mux_fck at 48005040 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
@@ -2143,7 +2143,7 @@ index 0000000..18a723f
+ bit-mask = <0x1>;
+};
+
-+gpt4_fck: gpt4_fck@48005000 {
++gpt4_fck: gpt4_fck at 48005000 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&gpt4_mux_fck>;
@@ -2151,7 +2151,7 @@ index 0000000..18a723f
+ reg = <0x48005000 0x4>;
+};
+
-+gpt5_mux_fck: gpt5_mux_fck@48005040 {
++gpt5_mux_fck: gpt5_mux_fck at 48005040 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
@@ -2160,7 +2160,7 @@ index 0000000..18a723f
+ bit-mask = <0x1>;
+};
+
-+gpt5_fck: gpt5_fck@48005000 {
++gpt5_fck: gpt5_fck at 48005000 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&gpt5_mux_fck>;
@@ -2168,7 +2168,7 @@ index 0000000..18a723f
+ reg = <0x48005000 0x4>;
+};
+
-+gpt6_mux_fck: gpt6_mux_fck@48005040 {
++gpt6_mux_fck: gpt6_mux_fck at 48005040 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
@@ -2177,7 +2177,7 @@ index 0000000..18a723f
+ bit-mask = <0x1>;
+};
+
-+gpt6_fck: gpt6_fck@48005000 {
++gpt6_fck: gpt6_fck at 48005000 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&gpt6_mux_fck>;
@@ -2185,7 +2185,7 @@ index 0000000..18a723f
+ reg = <0x48005000 0x4>;
+};
+
-+gpt7_mux_fck: gpt7_mux_fck@48005040 {
++gpt7_mux_fck: gpt7_mux_fck at 48005040 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
@@ -2194,7 +2194,7 @@ index 0000000..18a723f
+ bit-mask = <0x1>;
+};
+
-+gpt7_fck: gpt7_fck@48005000 {
++gpt7_fck: gpt7_fck at 48005000 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&gpt7_mux_fck>;
@@ -2202,7 +2202,7 @@ index 0000000..18a723f
+ reg = <0x48005000 0x4>;
+};
+
-+gpt8_mux_fck: gpt8_mux_fck@48005040 {
++gpt8_mux_fck: gpt8_mux_fck at 48005040 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
@@ -2211,7 +2211,7 @@ index 0000000..18a723f
+ bit-mask = <0x1>;
+};
+
-+gpt8_fck: gpt8_fck@48005000 {
++gpt8_fck: gpt8_fck at 48005000 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&gpt8_mux_fck>;
@@ -2219,7 +2219,7 @@ index 0000000..18a723f
+ reg = <0x48005000 0x4>;
+};
+
-+gpt9_mux_fck: gpt9_mux_fck@48005040 {
++gpt9_mux_fck: gpt9_mux_fck at 48005040 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
@@ -2228,7 +2228,7 @@ index 0000000..18a723f
+ bit-mask = <0x1>;
+};
+
-+gpt9_fck: gpt9_fck@48005000 {
++gpt9_fck: gpt9_fck at 48005000 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&gpt9_mux_fck>;
@@ -2244,7 +2244,7 @@ index 0000000..18a723f
+ clock-div = <1>;
+};
+
-+gpio6_dbck: gpio6_dbck@48005000 {
++gpio6_dbck: gpio6_dbck at 48005000 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&per_32k_alwon_fck>;
@@ -2252,7 +2252,7 @@ index 0000000..18a723f
+ bit-shift = <17>;
+};
+
-+gpio5_dbck: gpio5_dbck@48005000 {
++gpio5_dbck: gpio5_dbck at 48005000 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&per_32k_alwon_fck>;
@@ -2260,7 +2260,7 @@ index 0000000..18a723f
+ bit-shift = <16>;
+};
+
-+gpio4_dbck: gpio4_dbck@48005000 {
++gpio4_dbck: gpio4_dbck at 48005000 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&per_32k_alwon_fck>;
@@ -2268,7 +2268,7 @@ index 0000000..18a723f
+ bit-shift = <15>;
+};
+
-+gpio3_dbck: gpio3_dbck@48005000 {
++gpio3_dbck: gpio3_dbck at 48005000 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&per_32k_alwon_fck>;
@@ -2276,7 +2276,7 @@ index 0000000..18a723f
+ bit-shift = <14>;
+};
+
-+gpio2_dbck: gpio2_dbck@48005000 {
++gpio2_dbck: gpio2_dbck at 48005000 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&per_32k_alwon_fck>;
@@ -2284,7 +2284,7 @@ index 0000000..18a723f
+ bit-shift = <13>;
+};
+
-+wdt3_fck: wdt3_fck@48005000 {
++wdt3_fck: wdt3_fck at 48005000 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&per_32k_alwon_fck>;
@@ -2301,7 +2301,7 @@ index 0000000..18a723f
+ clock-div = <1>;
+};
+
-+gpio6_ick: gpio6_ick@48005010 {
++gpio6_ick: gpio6_ick at 48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&per_l4_ick>;
@@ -2310,7 +2310,7 @@ index 0000000..18a723f
+ ti,enable-bit = <17>;
+};
+
-+gpio5_ick: gpio5_ick@48005010 {
++gpio5_ick: gpio5_ick at 48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&per_l4_ick>;
@@ -2319,7 +2319,7 @@ index 0000000..18a723f
+ ti,enable-bit = <16>;
+};
+
-+gpio4_ick: gpio4_ick@48005010 {
++gpio4_ick: gpio4_ick at 48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&per_l4_ick>;
@@ -2328,7 +2328,7 @@ index 0000000..18a723f
+ ti,enable-bit = <15>;
+};
+
-+gpio3_ick: gpio3_ick@48005010 {
++gpio3_ick: gpio3_ick at 48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&per_l4_ick>;
@@ -2337,7 +2337,7 @@ index 0000000..18a723f
+ ti,enable-bit = <14>;
+};
+
-+gpio2_ick: gpio2_ick@48005010 {
++gpio2_ick: gpio2_ick at 48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&per_l4_ick>;
@@ -2346,7 +2346,7 @@ index 0000000..18a723f
+ ti,enable-bit = <13>;
+};
+
-+wdt3_ick: wdt3_ick@48005010 {
++wdt3_ick: wdt3_ick at 48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&per_l4_ick>;
@@ -2355,7 +2355,7 @@ index 0000000..18a723f
+ ti,enable-bit = <12>;
+};
+
-+uart3_ick: uart3_ick@48005010 {
++uart3_ick: uart3_ick at 48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&per_l4_ick>;
@@ -2364,7 +2364,7 @@ index 0000000..18a723f
+ ti,enable-bit = <11>;
+};
+
-+uart4_ick: uart4_ick@48005010 {
++uart4_ick: uart4_ick at 48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&per_l4_ick>;
@@ -2373,7 +2373,7 @@ index 0000000..18a723f
+ ti,enable-bit = <18>;
+};
+
-+gpt9_ick: gpt9_ick@48005010 {
++gpt9_ick: gpt9_ick at 48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&per_l4_ick>;
@@ -2382,7 +2382,7 @@ index 0000000..18a723f
+ ti,enable-bit = <10>;
+};
+
-+gpt8_ick: gpt8_ick@48005010 {
++gpt8_ick: gpt8_ick at 48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&per_l4_ick>;
@@ -2391,7 +2391,7 @@ index 0000000..18a723f
+ ti,enable-bit = <9>;
+};
+
-+gpt7_ick: gpt7_ick@48005010 {
++gpt7_ick: gpt7_ick at 48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&per_l4_ick>;
@@ -2400,7 +2400,7 @@ index 0000000..18a723f
+ ti,enable-bit = <8>;
+};
+
-+gpt6_ick: gpt6_ick@48005010 {
++gpt6_ick: gpt6_ick at 48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&per_l4_ick>;
@@ -2409,7 +2409,7 @@ index 0000000..18a723f
+ ti,enable-bit = <7>;
+};
+
-+gpt5_ick: gpt5_ick@48005010 {
++gpt5_ick: gpt5_ick at 48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&per_l4_ick>;
@@ -2418,7 +2418,7 @@ index 0000000..18a723f
+ ti,enable-bit = <6>;
+};
+
-+gpt4_ick: gpt4_ick@48005010 {
++gpt4_ick: gpt4_ick at 48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&per_l4_ick>;
@@ -2427,7 +2427,7 @@ index 0000000..18a723f
+ ti,enable-bit = <5>;
+};
+
-+gpt3_ick: gpt3_ick@48005010 {
++gpt3_ick: gpt3_ick at 48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&per_l4_ick>;
@@ -2436,7 +2436,7 @@ index 0000000..18a723f
+ ti,enable-bit = <4>;
+};
+
-+gpt2_ick: gpt2_ick@48005010 {
++gpt2_ick: gpt2_ick at 48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&per_l4_ick>;
@@ -2445,7 +2445,7 @@ index 0000000..18a723f
+ ti,enable-bit = <3>;
+};
+
-+mcbsp2_ick: mcbsp2_ick@48005010 {
++mcbsp2_ick: mcbsp2_ick at 48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&per_l4_ick>;
@@ -2454,7 +2454,7 @@ index 0000000..18a723f
+ ti,enable-bit = <0>;
+};
+
-+mcbsp3_ick: mcbsp3_ick@48005010 {
++mcbsp3_ick: mcbsp3_ick at 48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&per_l4_ick>;
@@ -2463,7 +2463,7 @@ index 0000000..18a723f
+ ti,enable-bit = <1>;
+};
+
-+mcbsp4_ick: mcbsp4_ick@48005010 {
++mcbsp4_ick: mcbsp4_ick at 48005010 {
+ #clock-cells = <0>;
+ compatible = "ti,interface-clock";
+ clocks = <&per_l4_ick>;
@@ -2472,7 +2472,7 @@ index 0000000..18a723f
+ ti,enable-bit = <2>;
+};
+
-+mcbsp2_mux_fck: mcbsp2_mux_fck@48002274 {
++mcbsp2_mux_fck: mcbsp2_mux_fck at 48002274 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&per_96m_fck>, <&mcbsp_clks>;
@@ -2481,7 +2481,7 @@ index 0000000..18a723f
+ bit-mask = <0x1>;
+};
+
-+mcbsp2_fck: mcbsp2_fck@48005000 {
++mcbsp2_fck: mcbsp2_fck at 48005000 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&mcbsp2_mux_fck>;
@@ -2489,7 +2489,7 @@ index 0000000..18a723f
+ reg = <0x48005000 0x4>;
+};
+
-+mcbsp3_mux_fck: mcbsp3_mux_fck@480022d8 {
++mcbsp3_mux_fck: mcbsp3_mux_fck at 480022d8 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&per_96m_fck>, <&mcbsp_clks>;
@@ -2497,7 +2497,7 @@ index 0000000..18a723f
+ bit-mask = <0x1>;
+};
+
-+mcbsp3_fck: mcbsp3_fck@48005000 {
++mcbsp3_fck: mcbsp3_fck at 48005000 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&mcbsp3_mux_fck>;
@@ -2505,7 +2505,7 @@ index 0000000..18a723f
+ reg = <0x48005000 0x4>;
+};
+
-+mcbsp4_mux_fck: mcbsp4_mux_fck@480022d8 {
++mcbsp4_mux_fck: mcbsp4_mux_fck at 480022d8 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&per_96m_fck>, <&mcbsp_clks>;
@@ -2514,7 +2514,7 @@ index 0000000..18a723f
+ bit-mask = <0x1>;
+};
+
-+mcbsp4_fck: mcbsp4_fck@48005000 {
++mcbsp4_fck: mcbsp4_fck at 48005000 {
+ #clock-cells = <0>;
+ compatible = "gate-clock";
+ clocks = <&mcbsp4_mux_fck>;
@@ -2522,7 +2522,7 @@ index 0000000..18a723f
+ reg = <0x48005000 0x4>;
+};
+
-+emu_src_mux_ck: emu_src_mux_ck@48005140 {
++emu_src_mux_ck: emu_src_mux_ck at 48005140 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
@@ -2537,7 +2537,7 @@ index 0000000..18a723f
+ ti,clkdm-name = "emu_clkdm";
+};
+
-+pclk_fck: pclk_fck@48005140 {
++pclk_fck: pclk_fck at 48005140 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&emu_src_ck>;
@@ -2547,7 +2547,7 @@ index 0000000..18a723f
+ index-starts-at-one;
+};
+
-+pclkx2_fck: pclkx2_fck@48005140 {
++pclkx2_fck: pclkx2_fck at 48005140 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&emu_src_ck>;
@@ -2557,7 +2557,7 @@ index 0000000..18a723f
+ index-starts-at-one;
+};
+
-+atclk_fck: atclk_fck@48005140 {
++atclk_fck: atclk_fck at 48005140 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&emu_src_ck>;
@@ -2567,7 +2567,7 @@ index 0000000..18a723f
+ index-starts-at-one;
+};
+
-+traceclk_src_fck: traceclk_src_fck@48005140 {
++traceclk_src_fck: traceclk_src_fck at 48005140 {
+ #clock-cells = <0>;
+ compatible = "mux-clock";
+ clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
@@ -2576,7 +2576,7 @@ index 0000000..18a723f
+ bit-mask = <0x3>;
+};
+
-+traceclk_fck: traceclk_fck@48005140 {
++traceclk_fck: traceclk_fck at 48005140 {
+ #clock-cells = <0>;
+ compatible = "divider-clock";
+ clocks = <&traceclk_src_fck>;
diff --git a/a/content_digest b/N1/content_digest
index 59e4466..f614a99 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -2,7 +2,7 @@
"ref\0001374564028-11352-1-git-send-email-t-kristo\@ti.com\0"
]
[
- "From\0Tero Kristo <t-kristo\@ti.com>\0"
+ "From\0t-kristo\@ti.com (Tero Kristo)\0"
]
[
"Subject\0[PATCHv4 28/33] ARM: dts: omap3 clock data\0"
@@ -11,17 +11,7 @@
"Date\0Tue, 23 Jul 2013 10:20:23 +0300\0"
]
[
- "To\0linux-omap\@vger.kernel.org",
- " paul\@pwsan.com",
- " khilman\@linaro.org",
- " tony\@atomide.com",
- " mturquette\@linaro.org",
- " nm\@ti.com",
- " rnayak\@ti.com\0"
-]
-[
- "Cc\0linux-arm-kernel\@lists.infradead.org",
- " devicetree-discuss\@lists.ozlabs.org\0"
+ "To\0linux-arm-kernel\@lists.infradead.org\0"
]
[
"\0000:1\0"
@@ -86,7 +76,7 @@
"+ * published by the Free Software Foundation.\n",
"+ */\n",
"+\n",
- "+gfx_l3_fck: gfx_l3_fck\@48004b40 {\n",
+ "+gfx_l3_fck: gfx_l3_fck at 48004b40 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&l3_ick>;\n",
@@ -108,7 +98,7 @@
"+\tclock-div = <1>;\n",
"+};\n",
"+\n",
- "+gfx_cg1_ck: gfx_cg1_ck\@48004b00 {\n",
+ "+gfx_cg1_ck: gfx_cg1_ck at 48004b00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,gate-clock\";\n",
"+\tclocks = <&gfx_l3_fck>;\n",
@@ -117,7 +107,7 @@
"+\tti,enable-bit = <1>;\n",
"+};\n",
"+\n",
- "+gfx_cg2_ck: gfx_cg2_ck\@48004b00 {\n",
+ "+gfx_cg2_ck: gfx_cg2_ck at 48004b00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,gate-clock\";\n",
"+\tclocks = <&gfx_l3_fck>;\n",
@@ -126,7 +116,7 @@
"+\tti,enable-bit = <2>;\n",
"+};\n",
"+\n",
- "+d2d_26m_fck: d2d_26m_fck\@48004a00 {\n",
+ "+d2d_26m_fck: d2d_26m_fck at 48004a00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,gate-clock\";\n",
"+\tclocks = <&sys_ck>;\n",
@@ -135,7 +125,7 @@
"+\tti,enable-bit = <3>;\n",
"+};\n",
"+\n",
- "+fshostusb_fck: fshostusb_fck\@48004a00 {\n",
+ "+fshostusb_fck: fshostusb_fck at 48004a00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,gate-clock\";\n",
"+\tclocks = <&core_48m_fck>;\n",
@@ -144,7 +134,7 @@
"+\tti,enable-bit = <5>;\n",
"+};\n",
"+\n",
- "+ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1\@48004a40 {\n",
+ "+ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1 at 48004a40 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&corex2_fck>;\n",
@@ -154,7 +144,7 @@
"+\tbit-mask = <0xf>;\n",
"+};\n",
"+\n",
- "+ssi_ssr_fck_3430es1: ssi_ssr_fck_3430es1\@48004a00 {\n",
+ "+ssi_ssr_fck_3430es1: ssi_ssr_fck_3430es1 at 48004a00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&ssi_ssr_div_fck_3430es1>;\n",
@@ -170,7 +160,7 @@
"+\tclock-div = <2>;\n",
"+};\n",
"+\n",
- "+hsotgusb_ick_3430es1: hsotgusb_ick_3430es1\@48004a10 {\n",
+ "+hsotgusb_ick_3430es1: hsotgusb_ick_3430es1 at 48004a10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&core_l3_ick>;\n",
@@ -180,7 +170,7 @@
"+\tti,iclk-no-wait;\n",
"+};\n",
"+\n",
- "+fac_ick: fac_ick\@48004a10 {\n",
+ "+fac_ick: fac_ick at 48004a10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&core_l4_ick>;\n",
@@ -197,7 +187,7 @@
"+\tclock-div = <1>;\n",
"+};\n",
"+\n",
- "+ssi_ick_3430es1: ssi_ick_3430es1\@48004a10 {\n",
+ "+ssi_ick_3430es1: ssi_ick_3430es1 at 48004a10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&ssi_l4_ick>;\n",
@@ -207,7 +197,7 @@
"+\tti,iclk-no-wait;\n",
"+};\n",
"+\n",
- "+usb_l4_div_ick: usb_l4_div_ick\@48004a40 {\n",
+ "+usb_l4_div_ick: usb_l4_div_ick at 48004a40 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&l4_ick>;\n",
@@ -217,7 +207,7 @@
"+\tindex-starts-at-one;\n",
"+};\n",
"+\n",
- "+usb_l4_ick: usb_l4_ick\@48004a10 {\n",
+ "+usb_l4_ick: usb_l4_ick at 48004a10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&usb_l4_div_ick>;\n",
@@ -225,7 +215,7 @@
"+\treg = <0x48004a10 0x4>;\n",
"+};\n",
"+\n",
- "+dss1_alwon_fck_3430es1: dss1_alwon_fck_3430es1\@48004e00 {\n",
+ "+dss1_alwon_fck_3430es1: dss1_alwon_fck_3430es1 at 48004e00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&dpll4_m4x2_ck>;\n",
@@ -233,7 +223,7 @@
"+\tbit-shift = <0>;\n",
"+};\n",
"+\n",
- "+dss_ick_3430es1: dss_ick_3430es1\@48004e10 {\n",
+ "+dss_ick_3430es1: dss_ick_3430es1 at 48004e10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&l4_ick>;\n",
@@ -266,7 +256,7 @@
"+\tclock-div = <1>;\n",
"+};\n",
"+\n",
- "+aes1_ick: aes1_ick\@48004a14 {\n",
+ "+aes1_ick: aes1_ick at 48004a14 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&security_l4_ick2>;\n",
@@ -274,7 +264,7 @@
"+\tti,enable-bit = <3>;\n",
"+};\n",
"+\n",
- "+rng_ick: rng_ick\@48004a14 {\n",
+ "+rng_ick: rng_ick at 48004a14 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&security_l4_ick2>;\n",
@@ -282,7 +272,7 @@
"+\tti,enable-bit = <2>;\n",
"+};\n",
"+\n",
- "+sha11_ick: sha11_ick\@48004a14 {\n",
+ "+sha11_ick: sha11_ick at 48004a14 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&security_l4_ick2>;\n",
@@ -290,7 +280,7 @@
"+\tti,enable-bit = <1>;\n",
"+};\n",
"+\n",
- "+des1_ick: des1_ick\@48004a14 {\n",
+ "+des1_ick: des1_ick at 48004a14 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&security_l4_ick2>;\n",
@@ -298,7 +288,7 @@
"+\tti,enable-bit = <0>;\n",
"+};\n",
"+\n",
- "+cam_mclk: cam_mclk\@48004f00 {\n",
+ "+cam_mclk: cam_mclk at 48004f00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&dpll4_m5x2_ck>;\n",
@@ -307,7 +297,7 @@
"+\tset-rate-parent;\n",
"+};\n",
"+\n",
- "+cam_ick: cam_ick\@48004f10 {\n",
+ "+cam_ick: cam_ick at 48004f10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&l4_ick>;\n",
@@ -317,7 +307,7 @@
"+\tti,iclk-no-wait;\n",
"+};\n",
"+\n",
- "+csi2_96m_fck: csi2_96m_fck\@48004f00 {\n",
+ "+csi2_96m_fck: csi2_96m_fck at 48004f00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&core_96m_fck>;\n",
@@ -333,7 +323,7 @@
"+\tclock-div = <1>;\n",
"+};\n",
"+\n",
- "+pka_ick: pka_ick\@48004a14 {\n",
+ "+pka_ick: pka_ick at 48004a14 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&security_l3_ick>;\n",
@@ -341,7 +331,7 @@
"+\tti,enable-bit = <4>;\n",
"+};\n",
"+\n",
- "+icr_ick: icr_ick\@48004a10 {\n",
+ "+icr_ick: icr_ick at 48004a10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&core_l4_ick>;\n",
@@ -350,7 +340,7 @@
"+\tti,enable-bit = <29>;\n",
"+};\n",
"+\n",
- "+des2_ick: des2_ick\@48004a10 {\n",
+ "+des2_ick: des2_ick at 48004a10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&core_l4_ick>;\n",
@@ -359,7 +349,7 @@
"+\tti,enable-bit = <26>;\n",
"+};\n",
"+\n",
- "+mspro_ick: mspro_ick\@48004a10 {\n",
+ "+mspro_ick: mspro_ick at 48004a10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&core_l4_ick>;\n",
@@ -368,7 +358,7 @@
"+\tti,enable-bit = <23>;\n",
"+};\n",
"+\n",
- "+mailboxes_ick: mailboxes_ick\@48004a10 {\n",
+ "+mailboxes_ick: mailboxes_ick at 48004a10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&core_l4_ick>;\n",
@@ -385,7 +375,7 @@
"+\tclock-div = <1>;\n",
"+};\n",
"+\n",
- "+sr1_fck: sr1_fck\@48004c00 {\n",
+ "+sr1_fck: sr1_fck at 48004c00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,gate-clock\";\n",
"+\tclocks = <&sys_ck>;\n",
@@ -394,7 +384,7 @@
"+\tti,enable-bit = <6>;\n",
"+};\n",
"+\n",
- "+sr2_fck: sr2_fck\@48004c00 {\n",
+ "+sr2_fck: sr2_fck at 48004c00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,gate-clock\";\n",
"+\tclocks = <&sys_ck>;\n",
@@ -411,7 +401,7 @@
"+\tclock-div = <1>;\n",
"+};\n",
"+\n",
- "+dpll2_fck: dpll2_fck\@48004040 {\n",
+ "+dpll2_fck: dpll2_fck at 48004040 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&core_ck>;\n",
@@ -421,7 +411,7 @@
"+\tindex-starts-at-one;\n",
"+};\n",
"+\n",
- "+dpll2_ck: dpll2_ck\@48004004 {\n",
+ "+dpll2_ck: dpll2_ck at 48004004 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,omap3-dpll-clock\";\n",
"+\tclocks = <&sys_ck>;\n",
@@ -435,7 +425,7 @@
"+\tti,recal-st-bit = <0x8>;\n",
"+};\n",
"+\n",
- "+dpll2_m2_ck: dpll2_m2_ck\@48004044 {\n",
+ "+dpll2_m2_ck: dpll2_m2_ck at 48004044 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll2_ck>;\n",
@@ -444,7 +434,7 @@
"+\tindex-starts-at-one;\n",
"+};\n",
"+\n",
- "+iva2_ck: iva2_ck\@48004000 {\n",
+ "+iva2_ck: iva2_ck at 48004000 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,gate-clock\";\n",
"+\tclocks = <&dpll2_m2_ck>;\n",
@@ -453,7 +443,7 @@
"+\tti,enable-bit = <0>;\n",
"+};\n",
"+\n",
- "+modem_fck: modem_fck\@48004a00 {\n",
+ "+modem_fck: modem_fck at 48004a00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&sys_ck>;\n",
@@ -462,7 +452,7 @@
"+\tti,enable-bit = <31>;\n",
"+};\n",
"+\n",
- "+sad2d_ick: sad2d_ick\@48004a10 {\n",
+ "+sad2d_ick: sad2d_ick at 48004a10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&l3_ick>;\n",
@@ -471,7 +461,7 @@
"+\tti,enable-bit = <3>;\n",
"+};\n",
"+\n",
- "+mad2d_ick: mad2d_ick\@48004a18 {\n",
+ "+mad2d_ick: mad2d_ick at 48004a18 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&l3_ick>;\n",
@@ -480,7 +470,7 @@
"+\tti,enable-bit = <3>;\n",
"+};\n",
"+\n",
- "+mspro_fck: mspro_fck\@48004a00 {\n",
+ "+mspro_fck: mspro_fck at 48004a00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,gate-clock\";\n",
"+\tclocks = <&core_96m_fck>;\n",
@@ -522,7 +512,7 @@
"+ * published by the Free Software Foundation.\n",
"+ */\n",
"+\n",
- "+dpll5_ck: dpll5_ck\@48004d04 {\n",
+ "+dpll5_ck: dpll5_ck at 48004d04 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,omap3-dpll-clock\";\n",
"+\tclocks = <&sys_ck>;\n",
@@ -536,7 +526,7 @@
"+\tti,recal-st-bit = <0x19>;\n",
"+};\n",
"+\n",
- "+dpll5_m2_ck: dpll5_m2_ck\@48004d50 {\n",
+ "+dpll5_m2_ck: dpll5_m2_ck at 48004d50 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll5_ck>;\n",
@@ -601,7 +591,7 @@
"+\tclock-div = <5>;\n",
"+};\n",
"+\n",
- "+sgx_mux_fck: sgx_mux_fck\@48004b40 {\n",
+ "+sgx_mux_fck: sgx_mux_fck at 48004b40 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>;\n",
@@ -610,7 +600,7 @@
"+\tbit-mask = <0x7>;\n",
"+};\n",
"+\n",
- "+sgx_fck: sgx_fck\@48004b00 {\n",
+ "+sgx_fck: sgx_fck at 48004b00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&sgx_mux_fck>;\n",
@@ -618,7 +608,7 @@
"+\treg = <0x48004b00 0x4>;\n",
"+};\n",
"+\n",
- "+sgx_ick: sgx_ick\@48004b10 {\n",
+ "+sgx_ick: sgx_ick at 48004b10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,gate-clock\";\n",
"+\tclocks = <&l3_ick>;\n",
@@ -627,7 +617,7 @@
"+\tti,enable-bit = <0>;\n",
"+};\n",
"+\n",
- "+cpefuse_fck: cpefuse_fck\@48004a08 {\n",
+ "+cpefuse_fck: cpefuse_fck at 48004a08 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&sys_ck>;\n",
@@ -635,7 +625,7 @@
"+\tbit-shift = <0>;\n",
"+};\n",
"+\n",
- "+ts_fck: ts_fck\@48004a08 {\n",
+ "+ts_fck: ts_fck at 48004a08 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&omap_32k_fck>;\n",
@@ -643,7 +633,7 @@
"+\tbit-shift = <1>;\n",
"+};\n",
"+\n",
- "+usbtll_fck: usbtll_fck\@48004a08 {\n",
+ "+usbtll_fck: usbtll_fck at 48004a08 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,gate-clock\";\n",
"+\tclocks = <&dpll5_m2_ck>;\n",
@@ -652,7 +642,7 @@
"+\tti,enable-bit = <2>;\n",
"+};\n",
"+\n",
- "+usbtll_ick: usbtll_ick\@48004a18 {\n",
+ "+usbtll_ick: usbtll_ick at 48004a18 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&core_l4_ick>;\n",
@@ -661,7 +651,7 @@
"+\tti,enable-bit = <2>;\n",
"+};\n",
"+\n",
- "+mmchs3_ick: mmchs3_ick\@48004a10 {\n",
+ "+mmchs3_ick: mmchs3_ick at 48004a10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&core_l4_ick>;\n",
@@ -670,7 +660,7 @@
"+\tti,enable-bit = <30>;\n",
"+};\n",
"+\n",
- "+mmchs3_fck: mmchs3_fck\@48004a00 {\n",
+ "+mmchs3_fck: mmchs3_fck at 48004a00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,gate-clock\";\n",
"+\tclocks = <&core_96m_fck>;\n",
@@ -679,7 +669,7 @@
"+\tti,enable-bit = <30>;\n",
"+};\n",
"+\n",
- "+dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2\@48004e00 {\n",
+ "+dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2 at 48004e00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,gate-clock\";\n",
"+\tclocks = <&dpll4_m4x2_ck>;\n",
@@ -689,7 +679,7 @@
"+\tti,dss-clk;\n",
"+};\n",
"+\n",
- "+dss_ick_3430es2: dss_ick_3430es2\@48004e10 {\n",
+ "+dss_ick_3430es2: dss_ick_3430es2 at 48004e10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&l4_ick>;\n",
@@ -699,7 +689,7 @@
"+\tti,iclk-dss;\n",
"+};\n",
"+\n",
- "+usbhost_120m_fck: usbhost_120m_fck\@48005400 {\n",
+ "+usbhost_120m_fck: usbhost_120m_fck at 48005400 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&dpll5_m2_ck>;\n",
@@ -707,7 +697,7 @@
"+\tbit-shift = <1>;\n",
"+};\n",
"+\n",
- "+usbhost_48m_fck: usbhost_48m_fck\@48005400 {\n",
+ "+usbhost_48m_fck: usbhost_48m_fck at 48005400 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,gate-clock\";\n",
"+\tclocks = <&omap_48m_fck>;\n",
@@ -717,7 +707,7 @@
"+\tti,dss-clk;\n",
"+};\n",
"+\n",
- "+usbhost_ick: usbhost_ick\@48005410 {\n",
+ "+usbhost_ick: usbhost_ick at 48005410 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&l4_ick>;\n",
@@ -742,7 +732,7 @@
"+ * published by the Free Software Foundation.\n",
"+ */\n",
"+\n",
- "+dpll4_ck: dpll4_ck\@48004d00 {\n",
+ "+dpll4_ck: dpll4_ck at 48004d00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,omap3-dpll-clock\";\n",
"+\tclocks = <&sys_ck>;\n",
@@ -762,7 +752,7 @@
"+\tti,dpll-peripheral;\n",
"+};\n",
"+\n",
- "+dpll4_m2x2_ck: dpll4_m2x2_ck\@48004d00 {\n",
+ "+dpll4_m2x2_ck: dpll4_m2x2_ck at 48004d00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,gate-clock\";\n",
"+\tclocks = <&dpll4_m2x2_mul_ck>;\n",
@@ -772,7 +762,7 @@
"+\tti,hsdiv-restore;\n",
"+};\n",
"+\n",
- "+dpll3_m3x2_ck: dpll3_m3x2_ck\@48004d00 {\n",
+ "+dpll3_m3x2_ck: dpll3_m3x2_ck at 48004d00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,gate-clock\";\n",
"+\tclocks = <&dpll3_m3x2_mul_ck>;\n",
@@ -782,7 +772,7 @@
"+\tti,hsdiv-restore;\n",
"+};\n",
"+\n",
- "+dpll4_m3x2_ck: dpll4_m3x2_ck\@48004d00 {\n",
+ "+dpll4_m3x2_ck: dpll4_m3x2_ck at 48004d00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,gate-clock\";\n",
"+\tclocks = <&dpll4_m3x2_mul_ck>;\n",
@@ -792,7 +782,7 @@
"+\tti,hsdiv-restore;\n",
"+};\n",
"+\n",
- "+dpll4_m5x2_ck: dpll4_m5x2_ck\@48004d00 {\n",
+ "+dpll4_m5x2_ck: dpll4_m5x2_ck at 48004d00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,gate-clock\";\n",
"+\tclocks = <&dpll4_m5x2_mul_ck>;\n",
@@ -803,7 +793,7 @@
"+\tset-bit-to-disable;\n",
"+};\n",
"+\n",
- "+dpll4_m6x2_ck: dpll4_m6x2_ck\@48004d00 {\n",
+ "+dpll4_m6x2_ck: dpll4_m6x2_ck at 48004d00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,gate-clock\";\n",
"+\tclocks = <&dpll4_m6x2_mul_ck>;\n",
@@ -821,7 +811,7 @@
"+\tclock-div = <1>;\n",
"+};\n",
"+\n",
- "+uart4_fck: uart4_fck\@48005000 {\n",
+ "+uart4_fck: uart4_fck at 48005000 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,gate-clock\";\n",
"+\tclocks = <&per_48m_fck>;\n",
@@ -845,7 +835,7 @@
"+ * published by the Free Software Foundation.\n",
"+ */\n",
"+\n",
- "+ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2\@48004a40 {\n",
+ "+ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 at 48004a40 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&corex2_fck>;\n",
@@ -855,7 +845,7 @@
"+\tbit-mask = <0xf>;\n",
"+};\n",
"+\n",
- "+ssi_ssr_fck_3430es2: ssi_ssr_fck_3430es2\@48004a00 {\n",
+ "+ssi_ssr_fck_3430es2: ssi_ssr_fck_3430es2 at 48004a00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&ssi_ssr_div_fck_3430es2>;\n",
@@ -871,7 +861,7 @@
"+\tclock-div = <2>;\n",
"+};\n",
"+\n",
- "+hsotgusb_ick_3430es2: hsotgusb_ick_3430es2\@48004a10 {\n",
+ "+hsotgusb_ick_3430es2: hsotgusb_ick_3430es2 at 48004a10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&core_l3_ick>;\n",
@@ -889,7 +879,7 @@
"+\tclock-div = <1>;\n",
"+};\n",
"+\n",
- "+ssi_ick_3430es2: ssi_ick_3430es2\@48004a10 {\n",
+ "+ssi_ick_3430es2: ssi_ick_3430es2 at 48004a10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&ssi_l4_ick>;\n",
@@ -899,7 +889,7 @@
"+\tti,iclk-ssi;\n",
"+};\n",
"+\n",
- "+dpll5_ck: dpll5_ck\@48004d04 {\n",
+ "+dpll5_ck: dpll5_ck at 48004d04 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,omap3-dpll-clock\";\n",
"+\tclocks = <&sys_ck>;\n",
@@ -913,7 +903,7 @@
"+\tti,recal-st-bit = <0x19>;\n",
"+};\n",
"+\n",
- "+dpll5_m2_ck: dpll5_m2_ck\@48004d50 {\n",
+ "+dpll5_m2_ck: dpll5_m2_ck at 48004d50 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll5_ck>;\n",
@@ -994,7 +984,7 @@
"+\tclock-div = <16>;\n",
"+};\n",
"+\n",
- "+usim_mux_fck: usim_mux_fck\@48004c40 {\n",
+ "+usim_mux_fck: usim_mux_fck at 48004c40 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&sys_ck>, <&dpll5_m2_d20_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>;\n",
@@ -1004,7 +994,7 @@
"+\tbit-mask = <0xf>;\n",
"+};\n",
"+\n",
- "+usim_fck: usim_fck\@48004c00 {\n",
+ "+usim_fck: usim_fck at 48004c00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&usim_mux_fck>;\n",
@@ -1012,7 +1002,7 @@
"+\treg = <0x48004c00 0x4>;\n",
"+};\n",
"+\n",
- "+usim_ick: usim_ick\@48004c10 {\n",
+ "+usim_ick: usim_ick at 48004c10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&wkup_l4_ick>;\n",
@@ -1103,7 +1093,7 @@
"+\tclock-frequency = <16800000>;\n",
"+};\n",
"+\n",
- "+osc_sys_ck: osc_sys_ck\@48306d40 {\n",
+ "+osc_sys_ck: osc_sys_ck at 48306d40 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>;\n",
@@ -1111,7 +1101,7 @@
"+\tbit-mask = <0x7>;\n",
"+};\n",
"+\n",
- "+sys_ck: sys_ck\@48307270 {\n",
+ "+sys_ck: sys_ck at 48307270 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&osc_sys_ck>;\n",
@@ -1121,7 +1111,7 @@
"+\tindex-starts-at-one;\n",
"+};\n",
"+\n",
- "+dpll4_ck: dpll4_ck\@48004d00 {\n",
+ "+dpll4_ck: dpll4_ck at 48004d00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,omap3-dpll-clock\";\n",
"+\tclocks = <&sys_ck>;\n",
@@ -1139,7 +1129,7 @@
"+\tti,dpll-peripheral;\n",
"+};\n",
"+\n",
- "+dpll4_m2_ck: dpll4_m2_ck\@48004d48 {\n",
+ "+dpll4_m2_ck: dpll4_m2_ck at 48004d48 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll4_ck>;\n",
@@ -1156,7 +1146,7 @@
"+\tclock-div = <1>;\n",
"+};\n",
"+\n",
- "+dpll4_m2x2_ck: dpll4_m2x2_ck\@48004d00 {\n",
+ "+dpll4_m2x2_ck: dpll4_m2x2_ck at 48004d00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&dpll4_m2x2_mul_ck>;\n",
@@ -1173,7 +1163,7 @@
"+\tclock-div = <1>;\n",
"+};\n",
"+\n",
- "+dpll3_ck: dpll3_ck\@48004d00 {\n",
+ "+dpll3_ck: dpll3_ck at 48004d00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,omap3-dpll-clock\";\n",
"+\tclocks = <&sys_ck>;\n",
@@ -1187,7 +1177,7 @@
"+\tti,dpll-core;\n",
"+};\n",
"+\n",
- "+dpll3_m3_ck: dpll3_m3_ck\@48005140 {\n",
+ "+dpll3_m3_ck: dpll3_m3_ck at 48005140 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll3_ck>;\n",
@@ -1205,7 +1195,7 @@
"+\tclock-div = <1>;\n",
"+};\n",
"+\n",
- "+dpll3_m3x2_ck: dpll3_m3x2_ck\@48004d00 {\n",
+ "+dpll3_m3x2_ck: dpll3_m3x2_ck at 48004d00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&dpll3_m3x2_mul_ck>;\n",
@@ -1234,7 +1224,7 @@
"+\tclock-frequency = <0x0>;\n",
"+};\n",
"+\n",
- "+sys_clkout1: sys_clkout1\@48306d70 {\n",
+ "+sys_clkout1: sys_clkout1 at 48306d70 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&osc_sys_ck>;\n",
@@ -1242,7 +1232,7 @@
"+\tbit-shift = <7>;\n",
"+};\n",
"+\n",
- "+dpll1_ck: dpll1_ck\@48004904 {\n",
+ "+dpll1_ck: dpll1_ck at 48004904 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,omap3-dpll-clock\";\n",
"+\tclocks = <&sys_ck>;\n",
@@ -1263,7 +1253,7 @@
"+\tclock-div = <1>;\n",
"+};\n",
"+\n",
- "+dpll1_x2m2_ck: dpll1_x2m2_ck\@48004944 {\n",
+ "+dpll1_x2m2_ck: dpll1_x2m2_ck at 48004944 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll1_x2_ck>;\n",
@@ -1272,7 +1262,7 @@
"+\tindex-starts-at-one;\n",
"+};\n",
"+\n",
- "+dpll3_m2_ck: dpll3_m2_ck\@48004d40 {\n",
+ "+dpll3_m2_ck: dpll3_m2_ck at 48004d40 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll3_ck>;\n",
@@ -1322,7 +1312,7 @@
"+\tclock-div = <1>;\n",
"+};\n",
"+\n",
- "+omap_96m_fck: omap_96m_fck\@48004d40 {\n",
+ "+omap_96m_fck: omap_96m_fck at 48004d40 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&cm_96m_fck>, <&sys_ck>;\n",
@@ -1331,7 +1321,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+dpll4_m3_ck: dpll4_m3_ck\@48004e40 {\n",
+ "+dpll4_m3_ck: dpll4_m3_ck at 48004e40 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll4_ck>;\n",
@@ -1349,7 +1339,7 @@
"+\tclock-div = <1>;\n",
"+};\n",
"+\n",
- "+dpll4_m3x2_ck: dpll4_m3x2_ck\@48004d00 {\n",
+ "+dpll4_m3x2_ck: dpll4_m3x2_ck at 48004d00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&dpll4_m3x2_mul_ck>;\n",
@@ -1358,7 +1348,7 @@
"+\tset-bit-to-disable;\n",
"+};\n",
"+\n",
- "+omap_54m_fck: omap_54m_fck\@48004d40 {\n",
+ "+omap_54m_fck: omap_54m_fck at 48004d40 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&dpll4_m3x2_ck>, <&sys_altclk>;\n",
@@ -1375,7 +1365,7 @@
"+\tclock-div = <2>;\n",
"+};\n",
"+\n",
- "+omap_48m_fck: omap_48m_fck\@48004d40 {\n",
+ "+omap_48m_fck: omap_48m_fck at 48004d40 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&cm_96m_d2_fck>, <&sys_altclk>;\n",
@@ -1393,7 +1383,7 @@
"+\tclock-div = <4>;\n",
"+};\n",
"+\n",
- "+dpll4_m4_ck: dpll4_m4_ck\@48004e40 {\n",
+ "+dpll4_m4_ck: dpll4_m4_ck at 48004e40 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll4_ck>;\n",
@@ -1410,7 +1400,7 @@
"+\tclock-div = <1>;\n",
"+};\n",
"+\n",
- "+dpll4_m4x2_ck: dpll4_m4x2_ck\@48004d00 {\n",
+ "+dpll4_m4x2_ck: dpll4_m4x2_ck at 48004d00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&dpll4_m4x2_mul_ck>;\n",
@@ -1419,7 +1409,7 @@
"+\tset-bit-to-disable;\n",
"+};\n",
"+\n",
- "+dpll4_m5_ck: dpll4_m5_ck\@48004f40 {\n",
+ "+dpll4_m5_ck: dpll4_m5_ck at 48004f40 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll4_ck>;\n",
@@ -1436,7 +1426,7 @@
"+\tclock-div = <1>;\n",
"+};\n",
"+\n",
- "+dpll4_m5x2_ck: dpll4_m5x2_ck\@48004d00 {\n",
+ "+dpll4_m5x2_ck: dpll4_m5x2_ck at 48004d00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&dpll4_m5x2_mul_ck>;\n",
@@ -1445,7 +1435,7 @@
"+\tset-bit-to-disable;\n",
"+};\n",
"+\n",
- "+dpll4_m6_ck: dpll4_m6_ck\@48005140 {\n",
+ "+dpll4_m6_ck: dpll4_m6_ck at 48005140 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&dpll4_ck>;\n",
@@ -1463,7 +1453,7 @@
"+\tclock-div = <1>;\n",
"+};\n",
"+\n",
- "+dpll4_m6x2_ck: dpll4_m6x2_ck\@48004d00 {\n",
+ "+dpll4_m6x2_ck: dpll4_m6x2_ck at 48004d00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&dpll4_m6x2_mul_ck>;\n",
@@ -1480,7 +1470,7 @@
"+\tclock-div = <1>;\n",
"+};\n",
"+\n",
- "+clkout2_src_mux_ck: clkout2_src_mux_ck\@48004d70 {\n",
+ "+clkout2_src_mux_ck: clkout2_src_mux_ck at 48004d70 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>;\n",
@@ -1488,7 +1478,7 @@
"+\tbit-mask = <0x3>;\n",
"+};\n",
"+\n",
- "+clkout2_src_ck: clkout2_src_ck\@48004d70 {\n",
+ "+clkout2_src_ck: clkout2_src_ck at 48004d70 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&clkout2_src_mux_ck>;\n",
@@ -1496,7 +1486,7 @@
"+\treg = <0x48004d70 0x4>;\n",
"+};\n",
"+\n",
- "+sys_clkout2: sys_clkout2\@48004d70 {\n",
+ "+sys_clkout2: sys_clkout2 at 48004d70 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&clkout2_src_ck>;\n",
@@ -1514,7 +1504,7 @@
"+\tclock-div = <1>;\n",
"+};\n",
"+\n",
- "+dpll1_fck: dpll1_fck\@48004940 {\n",
+ "+dpll1_fck: dpll1_fck at 48004940 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&core_ck>;\n",
@@ -1532,7 +1522,7 @@
"+\tclock-div = <1>;\n",
"+};\n",
"+\n",
- "+arm_fck: arm_fck\@48004924 {\n",
+ "+arm_fck: arm_fck at 48004924 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&mpu_ck>;\n",
@@ -1548,7 +1538,7 @@
"+\tclock-div = <1>;\n",
"+};\n",
"+\n",
- "+l3_ick: l3_ick\@48004a40 {\n",
+ "+l3_ick: l3_ick at 48004a40 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&core_ck>;\n",
@@ -1557,7 +1547,7 @@
"+\tindex-starts-at-one;\n",
"+};\n",
"+\n",
- "+l4_ick: l4_ick\@48004a40 {\n",
+ "+l4_ick: l4_ick at 48004a40 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&l3_ick>;\n",
@@ -1567,7 +1557,7 @@
"+\tindex-starts-at-one;\n",
"+};\n",
"+\n",
- "+rm_ick: rm_ick\@48004c40 {\n",
+ "+rm_ick: rm_ick at 48004c40 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&l4_ick>;\n",
@@ -1577,7 +1567,7 @@
"+\tindex-starts-at-one;\n",
"+};\n",
"+\n",
- "+gpt10_mux_fck: gpt10_mux_fck\@48004a40 {\n",
+ "+gpt10_mux_fck: gpt10_mux_fck at 48004a40 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&omap_32k_fck>, <&sys_ck>;\n",
@@ -1586,7 +1576,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+gpt10_fck: gpt10_fck\@48004a00 {\n",
+ "+gpt10_fck: gpt10_fck at 48004a00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&gpt10_mux_fck>;\n",
@@ -1594,7 +1584,7 @@
"+\treg = <0x48004a00 0x4>;\n",
"+};\n",
"+\n",
- "+gpt11_mux_fck: gpt11_mux_fck\@48004a40 {\n",
+ "+gpt11_mux_fck: gpt11_mux_fck at 48004a40 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&omap_32k_fck>, <&sys_ck>;\n",
@@ -1603,7 +1593,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+gpt11_fck: gpt11_fck\@48004a00 {\n",
+ "+gpt11_fck: gpt11_fck at 48004a00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&gpt11_mux_fck>;\n",
@@ -1619,7 +1609,7 @@
"+\tclock-div = <1>;\n",
"+};\n",
"+\n",
- "+mmchs2_fck: mmchs2_fck\@48004a00 {\n",
+ "+mmchs2_fck: mmchs2_fck at 48004a00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,gate-clock\";\n",
"+\tclocks = <&core_96m_fck>;\n",
@@ -1628,7 +1618,7 @@
"+\tti,enable-bit = <25>;\n",
"+};\n",
"+\n",
- "+mmchs1_fck: mmchs1_fck\@48004a00 {\n",
+ "+mmchs1_fck: mmchs1_fck at 48004a00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,gate-clock\";\n",
"+\tclocks = <&core_96m_fck>;\n",
@@ -1637,7 +1627,7 @@
"+\tti,enable-bit = <24>;\n",
"+};\n",
"+\n",
- "+i2c3_fck: i2c3_fck\@48004a00 {\n",
+ "+i2c3_fck: i2c3_fck at 48004a00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,gate-clock\";\n",
"+\tclocks = <&core_96m_fck>;\n",
@@ -1646,7 +1636,7 @@
"+\tti,enable-bit = <17>;\n",
"+};\n",
"+\n",
- "+i2c2_fck: i2c2_fck\@48004a00 {\n",
+ "+i2c2_fck: i2c2_fck at 48004a00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,gate-clock\";\n",
"+\tclocks = <&core_96m_fck>;\n",
@@ -1655,7 +1645,7 @@
"+\tti,enable-bit = <16>;\n",
"+};\n",
"+\n",
- "+i2c1_fck: i2c1_fck\@48004a00 {\n",
+ "+i2c1_fck: i2c1_fck at 48004a00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,gate-clock\";\n",
"+\tclocks = <&core_96m_fck>;\n",
@@ -1664,7 +1654,7 @@
"+\tti,enable-bit = <15>;\n",
"+};\n",
"+\n",
- "+mcbsp5_mux_fck: mcbsp5_mux_fck\@480022d8 {\n",
+ "+mcbsp5_mux_fck: mcbsp5_mux_fck at 480022d8 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&core_96m_fck>, <&mcbsp_clks>;\n",
@@ -1673,7 +1663,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+mcbsp5_fck: mcbsp5_fck\@48004a00 {\n",
+ "+mcbsp5_fck: mcbsp5_fck at 48004a00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&mcbsp5_mux_fck>;\n",
@@ -1681,7 +1671,7 @@
"+\treg = <0x48004a00 0x4>;\n",
"+};\n",
"+\n",
- "+mcbsp1_mux_fck: mcbsp1_mux_fck\@48002274 {\n",
+ "+mcbsp1_mux_fck: mcbsp1_mux_fck at 48002274 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&core_96m_fck>, <&mcbsp_clks>;\n",
@@ -1690,7 +1680,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+mcbsp1_fck: mcbsp1_fck\@48004a00 {\n",
+ "+mcbsp1_fck: mcbsp1_fck at 48004a00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&mcbsp1_mux_fck>;\n",
@@ -1706,7 +1696,7 @@
"+\tclock-div = <1>;\n",
"+};\n",
"+\n",
- "+mcspi4_fck: mcspi4_fck\@48004a00 {\n",
+ "+mcspi4_fck: mcspi4_fck at 48004a00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,gate-clock\";\n",
"+\tclocks = <&core_48m_fck>;\n",
@@ -1715,7 +1705,7 @@
"+\tti,enable-bit = <21>;\n",
"+};\n",
"+\n",
- "+mcspi3_fck: mcspi3_fck\@48004a00 {\n",
+ "+mcspi3_fck: mcspi3_fck at 48004a00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,gate-clock\";\n",
"+\tclocks = <&core_48m_fck>;\n",
@@ -1724,7 +1714,7 @@
"+\tti,enable-bit = <20>;\n",
"+};\n",
"+\n",
- "+mcspi2_fck: mcspi2_fck\@48004a00 {\n",
+ "+mcspi2_fck: mcspi2_fck at 48004a00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,gate-clock\";\n",
"+\tclocks = <&core_48m_fck>;\n",
@@ -1733,7 +1723,7 @@
"+\tti,enable-bit = <19>;\n",
"+};\n",
"+\n",
- "+mcspi1_fck: mcspi1_fck\@48004a00 {\n",
+ "+mcspi1_fck: mcspi1_fck at 48004a00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,gate-clock\";\n",
"+\tclocks = <&core_48m_fck>;\n",
@@ -1742,7 +1732,7 @@
"+\tti,enable-bit = <18>;\n",
"+};\n",
"+\n",
- "+uart2_fck: uart2_fck\@48004a00 {\n",
+ "+uart2_fck: uart2_fck at 48004a00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,gate-clock\";\n",
"+\tclocks = <&core_48m_fck>;\n",
@@ -1751,7 +1741,7 @@
"+\tti,enable-bit = <14>;\n",
"+};\n",
"+\n",
- "+uart1_fck: uart1_fck\@48004a00 {\n",
+ "+uart1_fck: uart1_fck at 48004a00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,gate-clock\";\n",
"+\tclocks = <&core_48m_fck>;\n",
@@ -1768,7 +1758,7 @@
"+\tclock-div = <1>;\n",
"+};\n",
"+\n",
- "+hdq_fck: hdq_fck\@48004a00 {\n",
+ "+hdq_fck: hdq_fck at 48004a00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,gate-clock\";\n",
"+\tclocks = <&core_12m_fck>;\n",
@@ -1785,7 +1775,7 @@
"+\tclock-div = <1>;\n",
"+};\n",
"+\n",
- "+sdrc_ick: sdrc_ick\@48004a10 {\n",
+ "+sdrc_ick: sdrc_ick at 48004a10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,gate-clock\";\n",
"+\tclocks = <&core_l3_ick>;\n",
@@ -1810,7 +1800,7 @@
"+\tclock-div = <1>;\n",
"+};\n",
"+\n",
- "+mmchs2_ick: mmchs2_ick\@48004a10 {\n",
+ "+mmchs2_ick: mmchs2_ick at 48004a10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&core_l4_ick>;\n",
@@ -1819,7 +1809,7 @@
"+\tti,enable-bit = <25>;\n",
"+};\n",
"+\n",
- "+mmchs1_ick: mmchs1_ick\@48004a10 {\n",
+ "+mmchs1_ick: mmchs1_ick at 48004a10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&core_l4_ick>;\n",
@@ -1828,7 +1818,7 @@
"+\tti,enable-bit = <24>;\n",
"+};\n",
"+\n",
- "+hdq_ick: hdq_ick\@48004a10 {\n",
+ "+hdq_ick: hdq_ick at 48004a10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&core_l4_ick>;\n",
@@ -1837,7 +1827,7 @@
"+\tti,enable-bit = <22>;\n",
"+};\n",
"+\n",
- "+mcspi4_ick: mcspi4_ick\@48004a10 {\n",
+ "+mcspi4_ick: mcspi4_ick at 48004a10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&core_l4_ick>;\n",
@@ -1846,7 +1836,7 @@
"+\tti,enable-bit = <21>;\n",
"+};\n",
"+\n",
- "+mcspi3_ick: mcspi3_ick\@48004a10 {\n",
+ "+mcspi3_ick: mcspi3_ick at 48004a10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&core_l4_ick>;\n",
@@ -1855,7 +1845,7 @@
"+\tti,enable-bit = <20>;\n",
"+};\n",
"+\n",
- "+mcspi2_ick: mcspi2_ick\@48004a10 {\n",
+ "+mcspi2_ick: mcspi2_ick at 48004a10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&core_l4_ick>;\n",
@@ -1864,7 +1854,7 @@
"+\tti,enable-bit = <19>;\n",
"+};\n",
"+\n",
- "+mcspi1_ick: mcspi1_ick\@48004a10 {\n",
+ "+mcspi1_ick: mcspi1_ick at 48004a10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&core_l4_ick>;\n",
@@ -1873,7 +1863,7 @@
"+\tti,enable-bit = <18>;\n",
"+};\n",
"+\n",
- "+i2c3_ick: i2c3_ick\@48004a10 {\n",
+ "+i2c3_ick: i2c3_ick at 48004a10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&core_l4_ick>;\n",
@@ -1882,7 +1872,7 @@
"+\tti,enable-bit = <17>;\n",
"+};\n",
"+\n",
- "+i2c2_ick: i2c2_ick\@48004a10 {\n",
+ "+i2c2_ick: i2c2_ick at 48004a10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&core_l4_ick>;\n",
@@ -1891,7 +1881,7 @@
"+\tti,enable-bit = <16>;\n",
"+};\n",
"+\n",
- "+i2c1_ick: i2c1_ick\@48004a10 {\n",
+ "+i2c1_ick: i2c1_ick at 48004a10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&core_l4_ick>;\n",
@@ -1900,7 +1890,7 @@
"+\tti,enable-bit = <15>;\n",
"+};\n",
"+\n",
- "+uart2_ick: uart2_ick\@48004a10 {\n",
+ "+uart2_ick: uart2_ick at 48004a10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&core_l4_ick>;\n",
@@ -1909,7 +1899,7 @@
"+\tti,enable-bit = <14>;\n",
"+};\n",
"+\n",
- "+uart1_ick: uart1_ick\@48004a10 {\n",
+ "+uart1_ick: uart1_ick at 48004a10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&core_l4_ick>;\n",
@@ -1918,7 +1908,7 @@
"+\tti,enable-bit = <13>;\n",
"+};\n",
"+\n",
- "+gpt11_ick: gpt11_ick\@48004a10 {\n",
+ "+gpt11_ick: gpt11_ick at 48004a10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&core_l4_ick>;\n",
@@ -1927,7 +1917,7 @@
"+\tti,enable-bit = <12>;\n",
"+};\n",
"+\n",
- "+gpt10_ick: gpt10_ick\@48004a10 {\n",
+ "+gpt10_ick: gpt10_ick at 48004a10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&core_l4_ick>;\n",
@@ -1936,7 +1926,7 @@
"+\tti,enable-bit = <11>;\n",
"+};\n",
"+\n",
- "+mcbsp5_ick: mcbsp5_ick\@48004a10 {\n",
+ "+mcbsp5_ick: mcbsp5_ick at 48004a10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&core_l4_ick>;\n",
@@ -1945,7 +1935,7 @@
"+\tti,enable-bit = <10>;\n",
"+};\n",
"+\n",
- "+mcbsp1_ick: mcbsp1_ick\@48004a10 {\n",
+ "+mcbsp1_ick: mcbsp1_ick at 48004a10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&core_l4_ick>;\n",
@@ -1954,7 +1944,7 @@
"+\tti,enable-bit = <9>;\n",
"+};\n",
"+\n",
- "+omapctrl_ick: omapctrl_ick\@48004a10 {\n",
+ "+omapctrl_ick: omapctrl_ick at 48004a10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&core_l4_ick>;\n",
@@ -1963,7 +1953,7 @@
"+\tti,enable-bit = <6>;\n",
"+};\n",
"+\n",
- "+dss_tv_fck: dss_tv_fck\@48004e00 {\n",
+ "+dss_tv_fck: dss_tv_fck at 48004e00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&omap_54m_fck>;\n",
@@ -1971,7 +1961,7 @@
"+\tbit-shift = <2>;\n",
"+};\n",
"+\n",
- "+dss_96m_fck: dss_96m_fck\@48004e00 {\n",
+ "+dss_96m_fck: dss_96m_fck at 48004e00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&omap_96m_fck>;\n",
@@ -1979,7 +1969,7 @@
"+\tbit-shift = <2>;\n",
"+};\n",
"+\n",
- "+dss2_alwon_fck: dss2_alwon_fck\@48004e00 {\n",
+ "+dss2_alwon_fck: dss2_alwon_fck at 48004e00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&sys_ck>;\n",
@@ -1987,7 +1977,7 @@
"+\tbit-shift = <1>;\n",
"+};\n",
"+\n",
- "+gpt1_mux_fck: gpt1_mux_fck\@48004c40 {\n",
+ "+gpt1_mux_fck: gpt1_mux_fck at 48004c40 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&omap_32k_fck>, <&sys_ck>;\n",
@@ -1995,7 +1985,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+gpt1_fck: gpt1_fck\@48004c00 {\n",
+ "+gpt1_fck: gpt1_fck at 48004c00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&gpt1_mux_fck>;\n",
@@ -2003,7 +1993,7 @@
"+\treg = <0x48004c00 0x4>;\n",
"+};\n",
"+\n",
- "+aes2_ick: aes2_ick\@48004a10 {\n",
+ "+aes2_ick: aes2_ick at 48004a10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&core_l4_ick>;\n",
@@ -2020,7 +2010,7 @@
"+\tclock-div = <1>;\n",
"+};\n",
"+\n",
- "+gpio1_dbck: gpio1_dbck\@48004c00 {\n",
+ "+gpio1_dbck: gpio1_dbck at 48004c00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&wkup_32k_fck>;\n",
@@ -2028,7 +2018,7 @@
"+\tbit-shift = <3>;\n",
"+};\n",
"+\n",
- "+sha12_ick: sha12_ick\@48004a10 {\n",
+ "+sha12_ick: sha12_ick at 48004a10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&core_l4_ick>;\n",
@@ -2037,7 +2027,7 @@
"+\tti,enable-bit = <27>;\n",
"+};\n",
"+\n",
- "+wdt2_fck: wdt2_fck\@48004c00 {\n",
+ "+wdt2_fck: wdt2_fck at 48004c00 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,gate-clock\";\n",
"+\tclocks = <&wkup_32k_fck>;\n",
@@ -2054,7 +2044,7 @@
"+\tclock-div = <1>;\n",
"+};\n",
"+\n",
- "+wdt2_ick: wdt2_ick\@48004c10 {\n",
+ "+wdt2_ick: wdt2_ick at 48004c10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&wkup_l4_ick>;\n",
@@ -2063,7 +2053,7 @@
"+\tti,enable-bit = <5>;\n",
"+};\n",
"+\n",
- "+wdt1_ick: wdt1_ick\@48004c10 {\n",
+ "+wdt1_ick: wdt1_ick at 48004c10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&wkup_l4_ick>;\n",
@@ -2072,7 +2062,7 @@
"+\tti,enable-bit = <4>;\n",
"+};\n",
"+\n",
- "+gpio1_ick: gpio1_ick\@48004c10 {\n",
+ "+gpio1_ick: gpio1_ick at 48004c10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&wkup_l4_ick>;\n",
@@ -2081,7 +2071,7 @@
"+\tti,enable-bit = <3>;\n",
"+};\n",
"+\n",
- "+omap_32ksync_ick: omap_32ksync_ick\@48004c10 {\n",
+ "+omap_32ksync_ick: omap_32ksync_ick at 48004c10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&wkup_l4_ick>;\n",
@@ -2090,7 +2080,7 @@
"+\tti,enable-bit = <2>;\n",
"+};\n",
"+\n",
- "+gpt12_ick: gpt12_ick\@48004c10 {\n",
+ "+gpt12_ick: gpt12_ick at 48004c10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&wkup_l4_ick>;\n",
@@ -2099,7 +2089,7 @@
"+\tti,enable-bit = <1>;\n",
"+};\n",
"+\n",
- "+gpt1_ick: gpt1_ick\@48004c10 {\n",
+ "+gpt1_ick: gpt1_ick at 48004c10 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&wkup_l4_ick>;\n",
@@ -2124,7 +2114,7 @@
"+\tclock-div = <1>;\n",
"+};\n",
"+\n",
- "+uart3_fck: uart3_fck\@48005000 {\n",
+ "+uart3_fck: uart3_fck at 48005000 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,gate-clock\";\n",
"+\tclocks = <&per_48m_fck>;\n",
@@ -2133,7 +2123,7 @@
"+\tti,enable-bit = <11>;\n",
"+};\n",
"+\n",
- "+gpt2_mux_fck: gpt2_mux_fck\@48005040 {\n",
+ "+gpt2_mux_fck: gpt2_mux_fck at 48005040 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&omap_32k_fck>, <&sys_ck>;\n",
@@ -2141,7 +2131,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+gpt2_fck: gpt2_fck\@48005000 {\n",
+ "+gpt2_fck: gpt2_fck at 48005000 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&gpt2_mux_fck>;\n",
@@ -2149,7 +2139,7 @@
"+\treg = <0x48005000 0x4>;\n",
"+};\n",
"+\n",
- "+gpt3_mux_fck: gpt3_mux_fck\@48005040 {\n",
+ "+gpt3_mux_fck: gpt3_mux_fck at 48005040 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&omap_32k_fck>, <&sys_ck>;\n",
@@ -2158,7 +2148,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+gpt3_fck: gpt3_fck\@48005000 {\n",
+ "+gpt3_fck: gpt3_fck at 48005000 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&gpt3_mux_fck>;\n",
@@ -2166,7 +2156,7 @@
"+\treg = <0x48005000 0x4>;\n",
"+};\n",
"+\n",
- "+gpt4_mux_fck: gpt4_mux_fck\@48005040 {\n",
+ "+gpt4_mux_fck: gpt4_mux_fck at 48005040 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&omap_32k_fck>, <&sys_ck>;\n",
@@ -2175,7 +2165,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+gpt4_fck: gpt4_fck\@48005000 {\n",
+ "+gpt4_fck: gpt4_fck at 48005000 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&gpt4_mux_fck>;\n",
@@ -2183,7 +2173,7 @@
"+\treg = <0x48005000 0x4>;\n",
"+};\n",
"+\n",
- "+gpt5_mux_fck: gpt5_mux_fck\@48005040 {\n",
+ "+gpt5_mux_fck: gpt5_mux_fck at 48005040 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&omap_32k_fck>, <&sys_ck>;\n",
@@ -2192,7 +2182,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+gpt5_fck: gpt5_fck\@48005000 {\n",
+ "+gpt5_fck: gpt5_fck at 48005000 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&gpt5_mux_fck>;\n",
@@ -2200,7 +2190,7 @@
"+\treg = <0x48005000 0x4>;\n",
"+};\n",
"+\n",
- "+gpt6_mux_fck: gpt6_mux_fck\@48005040 {\n",
+ "+gpt6_mux_fck: gpt6_mux_fck at 48005040 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&omap_32k_fck>, <&sys_ck>;\n",
@@ -2209,7 +2199,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+gpt6_fck: gpt6_fck\@48005000 {\n",
+ "+gpt6_fck: gpt6_fck at 48005000 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&gpt6_mux_fck>;\n",
@@ -2217,7 +2207,7 @@
"+\treg = <0x48005000 0x4>;\n",
"+};\n",
"+\n",
- "+gpt7_mux_fck: gpt7_mux_fck\@48005040 {\n",
+ "+gpt7_mux_fck: gpt7_mux_fck at 48005040 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&omap_32k_fck>, <&sys_ck>;\n",
@@ -2226,7 +2216,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+gpt7_fck: gpt7_fck\@48005000 {\n",
+ "+gpt7_fck: gpt7_fck at 48005000 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&gpt7_mux_fck>;\n",
@@ -2234,7 +2224,7 @@
"+\treg = <0x48005000 0x4>;\n",
"+};\n",
"+\n",
- "+gpt8_mux_fck: gpt8_mux_fck\@48005040 {\n",
+ "+gpt8_mux_fck: gpt8_mux_fck at 48005040 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&omap_32k_fck>, <&sys_ck>;\n",
@@ -2243,7 +2233,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+gpt8_fck: gpt8_fck\@48005000 {\n",
+ "+gpt8_fck: gpt8_fck at 48005000 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&gpt8_mux_fck>;\n",
@@ -2251,7 +2241,7 @@
"+\treg = <0x48005000 0x4>;\n",
"+};\n",
"+\n",
- "+gpt9_mux_fck: gpt9_mux_fck\@48005040 {\n",
+ "+gpt9_mux_fck: gpt9_mux_fck at 48005040 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&omap_32k_fck>, <&sys_ck>;\n",
@@ -2260,7 +2250,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+gpt9_fck: gpt9_fck\@48005000 {\n",
+ "+gpt9_fck: gpt9_fck at 48005000 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&gpt9_mux_fck>;\n",
@@ -2276,7 +2266,7 @@
"+\tclock-div = <1>;\n",
"+};\n",
"+\n",
- "+gpio6_dbck: gpio6_dbck\@48005000 {\n",
+ "+gpio6_dbck: gpio6_dbck at 48005000 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&per_32k_alwon_fck>;\n",
@@ -2284,7 +2274,7 @@
"+\tbit-shift = <17>;\n",
"+};\n",
"+\n",
- "+gpio5_dbck: gpio5_dbck\@48005000 {\n",
+ "+gpio5_dbck: gpio5_dbck at 48005000 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&per_32k_alwon_fck>;\n",
@@ -2292,7 +2282,7 @@
"+\tbit-shift = <16>;\n",
"+};\n",
"+\n",
- "+gpio4_dbck: gpio4_dbck\@48005000 {\n",
+ "+gpio4_dbck: gpio4_dbck at 48005000 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&per_32k_alwon_fck>;\n",
@@ -2300,7 +2290,7 @@
"+\tbit-shift = <15>;\n",
"+};\n",
"+\n",
- "+gpio3_dbck: gpio3_dbck\@48005000 {\n",
+ "+gpio3_dbck: gpio3_dbck at 48005000 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&per_32k_alwon_fck>;\n",
@@ -2308,7 +2298,7 @@
"+\tbit-shift = <14>;\n",
"+};\n",
"+\n",
- "+gpio2_dbck: gpio2_dbck\@48005000 {\n",
+ "+gpio2_dbck: gpio2_dbck at 48005000 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&per_32k_alwon_fck>;\n",
@@ -2316,7 +2306,7 @@
"+\tbit-shift = <13>;\n",
"+};\n",
"+\n",
- "+wdt3_fck: wdt3_fck\@48005000 {\n",
+ "+wdt3_fck: wdt3_fck at 48005000 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,gate-clock\";\n",
"+\tclocks = <&per_32k_alwon_fck>;\n",
@@ -2333,7 +2323,7 @@
"+\tclock-div = <1>;\n",
"+};\n",
"+\n",
- "+gpio6_ick: gpio6_ick\@48005010 {\n",
+ "+gpio6_ick: gpio6_ick at 48005010 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&per_l4_ick>;\n",
@@ -2342,7 +2332,7 @@
"+\tti,enable-bit = <17>;\n",
"+};\n",
"+\n",
- "+gpio5_ick: gpio5_ick\@48005010 {\n",
+ "+gpio5_ick: gpio5_ick at 48005010 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&per_l4_ick>;\n",
@@ -2351,7 +2341,7 @@
"+\tti,enable-bit = <16>;\n",
"+};\n",
"+\n",
- "+gpio4_ick: gpio4_ick\@48005010 {\n",
+ "+gpio4_ick: gpio4_ick at 48005010 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&per_l4_ick>;\n",
@@ -2360,7 +2350,7 @@
"+\tti,enable-bit = <15>;\n",
"+};\n",
"+\n",
- "+gpio3_ick: gpio3_ick\@48005010 {\n",
+ "+gpio3_ick: gpio3_ick at 48005010 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&per_l4_ick>;\n",
@@ -2369,7 +2359,7 @@
"+\tti,enable-bit = <14>;\n",
"+};\n",
"+\n",
- "+gpio2_ick: gpio2_ick\@48005010 {\n",
+ "+gpio2_ick: gpio2_ick at 48005010 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&per_l4_ick>;\n",
@@ -2378,7 +2368,7 @@
"+\tti,enable-bit = <13>;\n",
"+};\n",
"+\n",
- "+wdt3_ick: wdt3_ick\@48005010 {\n",
+ "+wdt3_ick: wdt3_ick at 48005010 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&per_l4_ick>;\n",
@@ -2387,7 +2377,7 @@
"+\tti,enable-bit = <12>;\n",
"+};\n",
"+\n",
- "+uart3_ick: uart3_ick\@48005010 {\n",
+ "+uart3_ick: uart3_ick at 48005010 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&per_l4_ick>;\n",
@@ -2396,7 +2386,7 @@
"+\tti,enable-bit = <11>;\n",
"+};\n",
"+\n",
- "+uart4_ick: uart4_ick\@48005010 {\n",
+ "+uart4_ick: uart4_ick at 48005010 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&per_l4_ick>;\n",
@@ -2405,7 +2395,7 @@
"+\tti,enable-bit = <18>;\n",
"+};\n",
"+\n",
- "+gpt9_ick: gpt9_ick\@48005010 {\n",
+ "+gpt9_ick: gpt9_ick at 48005010 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&per_l4_ick>;\n",
@@ -2414,7 +2404,7 @@
"+\tti,enable-bit = <10>;\n",
"+};\n",
"+\n",
- "+gpt8_ick: gpt8_ick\@48005010 {\n",
+ "+gpt8_ick: gpt8_ick at 48005010 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&per_l4_ick>;\n",
@@ -2423,7 +2413,7 @@
"+\tti,enable-bit = <9>;\n",
"+};\n",
"+\n",
- "+gpt7_ick: gpt7_ick\@48005010 {\n",
+ "+gpt7_ick: gpt7_ick at 48005010 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&per_l4_ick>;\n",
@@ -2432,7 +2422,7 @@
"+\tti,enable-bit = <8>;\n",
"+};\n",
"+\n",
- "+gpt6_ick: gpt6_ick\@48005010 {\n",
+ "+gpt6_ick: gpt6_ick at 48005010 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&per_l4_ick>;\n",
@@ -2441,7 +2431,7 @@
"+\tti,enable-bit = <7>;\n",
"+};\n",
"+\n",
- "+gpt5_ick: gpt5_ick\@48005010 {\n",
+ "+gpt5_ick: gpt5_ick at 48005010 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&per_l4_ick>;\n",
@@ -2450,7 +2440,7 @@
"+\tti,enable-bit = <6>;\n",
"+};\n",
"+\n",
- "+gpt4_ick: gpt4_ick\@48005010 {\n",
+ "+gpt4_ick: gpt4_ick at 48005010 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&per_l4_ick>;\n",
@@ -2459,7 +2449,7 @@
"+\tti,enable-bit = <5>;\n",
"+};\n",
"+\n",
- "+gpt3_ick: gpt3_ick\@48005010 {\n",
+ "+gpt3_ick: gpt3_ick at 48005010 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&per_l4_ick>;\n",
@@ -2468,7 +2458,7 @@
"+\tti,enable-bit = <4>;\n",
"+};\n",
"+\n",
- "+gpt2_ick: gpt2_ick\@48005010 {\n",
+ "+gpt2_ick: gpt2_ick at 48005010 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&per_l4_ick>;\n",
@@ -2477,7 +2467,7 @@
"+\tti,enable-bit = <3>;\n",
"+};\n",
"+\n",
- "+mcbsp2_ick: mcbsp2_ick\@48005010 {\n",
+ "+mcbsp2_ick: mcbsp2_ick at 48005010 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&per_l4_ick>;\n",
@@ -2486,7 +2476,7 @@
"+\tti,enable-bit = <0>;\n",
"+};\n",
"+\n",
- "+mcbsp3_ick: mcbsp3_ick\@48005010 {\n",
+ "+mcbsp3_ick: mcbsp3_ick at 48005010 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&per_l4_ick>;\n",
@@ -2495,7 +2485,7 @@
"+\tti,enable-bit = <1>;\n",
"+};\n",
"+\n",
- "+mcbsp4_ick: mcbsp4_ick\@48005010 {\n",
+ "+mcbsp4_ick: mcbsp4_ick at 48005010 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"ti,interface-clock\";\n",
"+\tclocks = <&per_l4_ick>;\n",
@@ -2504,7 +2494,7 @@
"+\tti,enable-bit = <2>;\n",
"+};\n",
"+\n",
- "+mcbsp2_mux_fck: mcbsp2_mux_fck\@48002274 {\n",
+ "+mcbsp2_mux_fck: mcbsp2_mux_fck at 48002274 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&per_96m_fck>, <&mcbsp_clks>;\n",
@@ -2513,7 +2503,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+mcbsp2_fck: mcbsp2_fck\@48005000 {\n",
+ "+mcbsp2_fck: mcbsp2_fck at 48005000 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&mcbsp2_mux_fck>;\n",
@@ -2521,7 +2511,7 @@
"+\treg = <0x48005000 0x4>;\n",
"+};\n",
"+\n",
- "+mcbsp3_mux_fck: mcbsp3_mux_fck\@480022d8 {\n",
+ "+mcbsp3_mux_fck: mcbsp3_mux_fck at 480022d8 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&per_96m_fck>, <&mcbsp_clks>;\n",
@@ -2529,7 +2519,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+mcbsp3_fck: mcbsp3_fck\@48005000 {\n",
+ "+mcbsp3_fck: mcbsp3_fck at 48005000 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&mcbsp3_mux_fck>;\n",
@@ -2537,7 +2527,7 @@
"+\treg = <0x48005000 0x4>;\n",
"+};\n",
"+\n",
- "+mcbsp4_mux_fck: mcbsp4_mux_fck\@480022d8 {\n",
+ "+mcbsp4_mux_fck: mcbsp4_mux_fck at 480022d8 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&per_96m_fck>, <&mcbsp_clks>;\n",
@@ -2546,7 +2536,7 @@
"+\tbit-mask = <0x1>;\n",
"+};\n",
"+\n",
- "+mcbsp4_fck: mcbsp4_fck\@48005000 {\n",
+ "+mcbsp4_fck: mcbsp4_fck at 48005000 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"gate-clock\";\n",
"+\tclocks = <&mcbsp4_mux_fck>;\n",
@@ -2554,7 +2544,7 @@
"+\treg = <0x48005000 0x4>;\n",
"+};\n",
"+\n",
- "+emu_src_mux_ck: emu_src_mux_ck\@48005140 {\n",
+ "+emu_src_mux_ck: emu_src_mux_ck at 48005140 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;\n",
@@ -2569,7 +2559,7 @@
"+\tti,clkdm-name = \"emu_clkdm\";\n",
"+};\n",
"+\n",
- "+pclk_fck: pclk_fck\@48005140 {\n",
+ "+pclk_fck: pclk_fck at 48005140 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&emu_src_ck>;\n",
@@ -2579,7 +2569,7 @@
"+\tindex-starts-at-one;\n",
"+};\n",
"+\n",
- "+pclkx2_fck: pclkx2_fck\@48005140 {\n",
+ "+pclkx2_fck: pclkx2_fck at 48005140 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&emu_src_ck>;\n",
@@ -2589,7 +2579,7 @@
"+\tindex-starts-at-one;\n",
"+};\n",
"+\n",
- "+atclk_fck: atclk_fck\@48005140 {\n",
+ "+atclk_fck: atclk_fck at 48005140 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&emu_src_ck>;\n",
@@ -2599,7 +2589,7 @@
"+\tindex-starts-at-one;\n",
"+};\n",
"+\n",
- "+traceclk_src_fck: traceclk_src_fck\@48005140 {\n",
+ "+traceclk_src_fck: traceclk_src_fck at 48005140 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"mux-clock\";\n",
"+\tclocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;\n",
@@ -2608,7 +2598,7 @@
"+\tbit-mask = <0x3>;\n",
"+};\n",
"+\n",
- "+traceclk_fck: traceclk_fck\@48005140 {\n",
+ "+traceclk_fck: traceclk_fck at 48005140 {\n",
"+\t#clock-cells = <0>;\n",
"+\tcompatible = \"divider-clock\";\n",
"+\tclocks = <&traceclk_src_fck>;\n",
@@ -2643,4 +2633,4 @@
"1.7.9.5"
]
-1554ec0875ca511241540164f6b95c4f879547917b34877737d9c7c974d2dc44
+d8d292625ca9ce1ba7151bbc959bb789a1ea1e7a95b2c6206e39af0cd774dc91
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