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diff for duplicates of <1374564028-11352-34-git-send-email-t-kristo@ti.com>

diff --git a/a/1.txt b/N1/1.txt
index d4b45a2..266f89a 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -13,12 +13,12 @@ diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clo
 index fcc14d4..32b9985 100644
 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
 +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
-@@ -2087,3 +2087,27 @@ vip3_gclk_mux: vip3_gclk_mux@4a009030 {
+@@ -2087,3 +2087,27 @@ vip3_gclk_mux: vip3_gclk_mux at 4a009030 {
  	reg = <0x4a009030 0x4>;
  	bit-mask = <0x1>;
  };
 +
-+optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
++optfclk_pciephy_div: optfclk_pciephy_div at 4a00821c {
 +	compatible = "divider-clock";
 +	clocks = <&apll_pcie_ck>;
 +	#clock-cells = <0>;
@@ -26,7 +26,7 @@ index fcc14d4..32b9985 100644
 +	bit-mask = <0x100>;
 +};
 +
-+optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 {
++optfclk_pciephy_clk: optfclk_pciephy_clk at 4a0093b0 {
 +	compatible = "gate-clock";
 +	clocks = <&apll_pcie_ck>;
 +	#clock-cells = <0>;
@@ -34,7 +34,7 @@ index fcc14d4..32b9985 100644
 +	bit-shift = <9>;
 +};
 +
-+optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 {
++optfclk_pciephy_div_clk: optfclk_pciephy_div_clk at 4a0093b0 {
 +	compatible = "gate-clock";
 +	clocks = <&optfclk_pciephy_div>;
 +	#clock-cells = <0>;
diff --git a/a/content_digest b/N1/content_digest
index 918625e..d0bbce5 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -2,7 +2,7 @@
   "ref\0001374564028-11352-1-git-send-email-t-kristo\@ti.com\0"
 ]
 [
-  "From\0Tero Kristo <t-kristo\@ti.com>\0"
+  "From\0t-kristo\@ti.com (Tero Kristo)\0"
 ]
 [
   "Subject\0[PATCHv4 33/33] clk: DTS: DRA7: Add PCIe related clock nodes\0"
@@ -11,18 +11,7 @@
   "Date\0Tue, 23 Jul 2013 10:20:28 +0300\0"
 ]
 [
-  "To\0linux-omap\@vger.kernel.org",
-  " paul\@pwsan.com",
-  " khilman\@linaro.org",
-  " tony\@atomide.com",
-  " mturquette\@linaro.org",
-  " nm\@ti.com",
-  " rnayak\@ti.com\0"
-]
-[
-  "Cc\0linux-arm-kernel\@lists.infradead.org",
-  " devicetree-discuss\@lists.ozlabs.org",
-  " Keerthy <j-keerthy\@ti.com>\0"
+  "To\0linux-arm-kernel\@lists.infradead.org\0"
 ]
 [
   "\0000:1\0"
@@ -46,12 +35,12 @@
   "index fcc14d4..32b9985 100644\n",
   "--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi\n",
   "+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi\n",
-  "\@\@ -2087,3 +2087,27 \@\@ vip3_gclk_mux: vip3_gclk_mux\@4a009030 {\n",
+  "\@\@ -2087,3 +2087,27 \@\@ vip3_gclk_mux: vip3_gclk_mux at 4a009030 {\n",
   " \treg = <0x4a009030 0x4>;\n",
   " \tbit-mask = <0x1>;\n",
   " };\n",
   "+\n",
-  "+optfclk_pciephy_div: optfclk_pciephy_div\@4a00821c {\n",
+  "+optfclk_pciephy_div: optfclk_pciephy_div at 4a00821c {\n",
   "+\tcompatible = \"divider-clock\";\n",
   "+\tclocks = <&apll_pcie_ck>;\n",
   "+\t#clock-cells = <0>;\n",
@@ -59,7 +48,7 @@
   "+\tbit-mask = <0x100>;\n",
   "+};\n",
   "+\n",
-  "+optfclk_pciephy_clk: optfclk_pciephy_clk\@4a0093b0 {\n",
+  "+optfclk_pciephy_clk: optfclk_pciephy_clk at 4a0093b0 {\n",
   "+\tcompatible = \"gate-clock\";\n",
   "+\tclocks = <&apll_pcie_ck>;\n",
   "+\t#clock-cells = <0>;\n",
@@ -67,7 +56,7 @@
   "+\tbit-shift = <9>;\n",
   "+};\n",
   "+\n",
-  "+optfclk_pciephy_div_clk: optfclk_pciephy_div_clk\@4a0093b0 {\n",
+  "+optfclk_pciephy_div_clk: optfclk_pciephy_div_clk at 4a0093b0 {\n",
   "+\tcompatible = \"gate-clock\";\n",
   "+\tclocks = <&optfclk_pciephy_div>;\n",
   "+\t#clock-cells = <0>;\n",
@@ -78,4 +67,4 @@
   "1.7.9.5"
 ]
 
-f70cb368ca44bfde028d56d1d1c39c994bcf5c8418b9ac6125f3bb323c7fcb61
+8a3f515dc3be369ffa4ba13174811fd5fadc671410aa65551e76463ccaf1daf8
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