From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47184) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aTGbe-0004PM-Pv for qemu-devel@nongnu.org; Tue, 09 Feb 2016 17:17:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aTGbZ-0001EM-Vv for qemu-devel@nongnu.org; Tue, 09 Feb 2016 17:17:58 -0500 Received: from mail-sn1nam02on0048.outbound.protection.outlook.com ([104.47.36.48]:55760 helo=NAM02-SN1-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aTGbZ-0001Dx-Os for qemu-devel@nongnu.org; Tue, 09 Feb 2016 17:17:53 -0500 From: Alistair Francis Date: Tue, 9 Feb 2016 14:15:15 -0800 Message-ID: <1379d26a566c79cd46ff6c1be6ae3aca774d2f18.1455055858.git.alistair.francis@xilinx.com> In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH v4 16/16] xlnx-zynqmp: Connect the ZynqMP IOU SLCR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: edgar.iglesias@xilinx.com, alistair.francis@xilinx.com, crosthwaitepeter@gmail.com, edgar.iglesias@gmail.com, alex.bennee@linaro.org, afaerber@suse.de, fred.konrad@greensocs.com Connect the I/O Unit System Level Control Registers device to the ZynqMP model. Unfortunatly the GPIO links can not be connected yet as the SD device is not yet attached to the ZynqMP machine. Signed-off-by: Alistair Francis --- V2: - Fix up device connection hw/arm/xlnx-zynqmp.c | 13 +++++++++++++ include/hw/arm/xlnx-zynqmp.h | 2 ++ 2 files changed, 15 insertions(+) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 1508d08..6d1b797 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -33,6 +33,8 @@ #define SATA_ADDR 0xFD0C0000 #define SATA_NUM_PORTS 2 +#define IOU_SLCR_ADDR 0xFF180000 + static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = { 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000, }; @@ -132,6 +134,10 @@ static void xlnx_zynqmp_init(Object *obj) TYPE_XILINX_SPIPS); qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default()); } + + object_initialize(&s->iou_slcr, sizeof(s->iou_slcr), + TYPE_XLNX_ZYNQMP_IOU_SLCR); + qdev_set_parent_bus(DEVICE(&s->iou_slcr), sysbus_get_default()); } static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) @@ -355,6 +361,13 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) &error_abort); g_free(bus_name); } + + object_property_set_bool(OBJECT(&s->iou_slcr), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->iou_slcr), 0, IOU_SLCR_ADDR); } static Property xlnx_zynqmp_props[] = { diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 2332596..8fff0ae 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -22,6 +22,7 @@ #include "hw/intc/arm_gic.h" #include "hw/net/cadence_gem.h" #include "hw/char/cadence_uart.h" +#include "hw/misc/xlnx-zynqmp-iou-slcr.h" #include "hw/ide/pci.h" #include "hw/ide/ahci.h" #include "hw/sd/sdhci.h" @@ -81,6 +82,7 @@ typedef struct XlnxZynqMPState { SysbusAHCIState sata; SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI]; XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS]; + XlnxZynqMPIOUSLCR iou_slcr; char *boot_cpu; ARMCPU *boot_cpu_ptr; -- 2.5.0